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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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        <META HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
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        <TITLE>socgen_prj_description</TITLE>
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        <META NAME="CLASSIFICATION" CONTENT="socgen project description">
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        <META NAME="DESCRIPTION" CONTENT="socgen is a laboratory for the development of a opensource design for reuse toolset">
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        <META NAME="KEYWORDS" CONTENT="eda design for reuse opensource tools">
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        <META NAME="date" CONTENT="2010-01-08T12:01:41-0500">
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<DIV ID="toc__header" DIR="LTR">
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<H1><A NAME="socgen_project"></A>SOCGEN Project</H1>
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<H2>Design for Reuse</H2>
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<P>The SOCGEN project is a laboratory for developing and
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demonstrating the methods and processes needed to create and reuse
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digital components. The goal of the project is to create a open
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source set of eda tools that will enable a designer to configure and
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assemble a complete System_on_a_chip (SOC) in a quick, easy and error
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free manner.</P>
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<P>I am hosting this project on Opencores due to the availability of
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free opensourced ip modules and a user community that is in dire need
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of a good design for reuse solution. I will be taking various
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opencores modules and reworking them into the socgen repository.
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Design for reuse is all about efficiency. Any code can be reused if
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you devote enough time and energy to it but paying attention to the
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details can make a huge difference in how easy it is to reuse a
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module. Any one is welcome to use these versions of the modules and
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the scripts that I am creating. Feedback is always welcome.</P>
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<P>The entire industry is about to experience a change in the way
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that  chips are designed  that will be as dramatic as it was back in
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the early 90's. Before that point the most common tool for  design
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entry was schematic capture. But designs had grown to the point where
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that was far to inefficient and it was replaced with a rtl to
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synthesis process.</P>
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<P>That happened 20 years ago and chips have continued to grow to the
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point where you can no longer design and verify the rtl code in a
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reasonable time.
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</P>
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<P>My approach to this problem is to introduce modern hi volume
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production line theory into the IC design process.  The designs are
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too complex to simply get a group together and hand craft  rtl code.
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Socgen will develop the tools and processes needed to  assemble cores
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together in quick and predictable manner.</P>
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<P>
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</P>
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<P>A good deal of this effort involves understanding database design
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and usage.  Most designers simply construct their databases based
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only on their immediate and past needs. Socgen will provide a
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repository of various projects that have been converted to show how
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small changes in where you store files can make a big difference in
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how easily those files can be reused.</P>
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<P><BR><BR>
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</P>
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<P>All socgen tools and components are released under LGPL. Any other
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opencores projects used in the repository will retain their original
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license.</P>
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</P>
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</P>
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</P>
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</P>
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</P>
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</P>
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<P>Socgen will provide:</P>
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<OL>
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        <LI><P>Installation instructions for any and all external tools
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        needed</P>
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        <LI><P>Proper data base design and management tools and techniques</P>
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        <LI><P>Proper design verification</P>
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        <LI><P>All modules will be proven in silicon</P>
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</OL>
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<P><BR><BR>
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</P>
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<P>Socgen is a work in process so expect to see frequent changes. All
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socgen tools are run under Makefiles and I will try to keep the top
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level commands constant.</P>
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<P><BR><BR>
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</P>
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<P>Till Later</P>
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<P><BR><BR>
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</P>
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<P>John Eaton</P>
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</P>
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