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//////////////////////////////////////////////////////////////////////////////
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// Copyright 2010 by Iztok Jeras (based on code by Terasic Technologies Inc.)
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//////////////////////////////////////////////////////////////////////////////
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module DE1_soc_nios2 (
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// Clock Input
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input [1:0] CLOCK_24, // 24 MHz
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input [1:0] CLOCK_27, // 27 MHz
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input CLOCK_50, // 50 MHz
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input EXT_CLOCK, // External Clock
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// Push Button
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input [3:0] KEY, // Pushbutton[3:0]
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// DPDT Switch
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input [9:0] SW, // Toggle Switch[9:0]
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// 7-SEG Dispaly
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output [6:0] HEX0, // Seven Segment Digit 0
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output [6:0] HEX1, // Seven Segment Digit 1
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output [6:0] HEX2, // Seven Segment Digit 2
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output [6:0] HEX3, // Seven Segment Digit 3
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// LED
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output [7:0] LEDG, // LED Green[7:0]
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output [9:0] LEDR, // LED Red[9:0]
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// UART
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output UART_TXD, // UART Transmitter
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input UART_RXD, // UART Receiver
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// SDRAM Interface
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output DRAM_CLK, // SDRAM Clock
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output DRAM_CKE, // SDRAM Clock Enable
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output DRAM_CS_N, // SDRAM Chip Select
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output DRAM_WE_N, // SDRAM Write Enable
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output DRAM_CAS_N, // SDRAM Column Address Strobe
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output DRAM_RAS_N, // SDRAM Row Address Strobe
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output [1:0] DRAM_BA, // SDRAM Bank Address
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output [11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits
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inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits
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output [1:0] DRAM_DQM, // SDRAM Byte Data Mask
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// Flash Interface
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output FL_RST_N, // FLASH Reset
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output FL_CE_N, // FLASH Chip Enable
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output FL_WE_N, // FLASH Write Enable
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output FL_OE_N, // FLASH Output Enable
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output [21:0] FL_ADDR, // FLASH Address bus 22 Bits
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inout [7:0] FL_DQ, // FLASH Data bus 8 Bits
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// SRAM Interface
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output SRAM_CE_N, // SRAM Chip Enable
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output SRAM_WE_N, // SRAM Write Enable
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output SRAM_OE_N, // SRAM Output Enable
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output [17:0] SRAM_ADDR, // SRAM Address bus 18 Bits
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output [1:0] SRAM_B_N, // SRAM Byte Data Mask
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inout [15:0] SRAM_DQ, // SRAM Data bus 16 Bits
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// SD_Card Interface
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inout SD_DAT, // SD Card Data
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inout SD_DAT3, // SD Card Data 3
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inout SD_CMD, // SD Card Command Signal
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output SD_CLK, // SD Card Clock
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// USB JTAG link
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input TDI, // CPLD -> FPGA (data in)
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input TCK, // CPLD -> FPGA (clk)
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input TCS, // CPLD -> FPGA (CS)
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output TDO, // FPGA -> CPLD (data out)
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// I2C
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inout I2C_SDAT, // I2C Data
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output I2C_SCLK, // I2C Clock
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// PS2
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inout PS2_DAT, // PS2 Data
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inout PS2_CLK, // PS2 Clock
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// VGA
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output VGA_HS, // VGA H_SYNC
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output VGA_VS, // VGA V_SYNC
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output [3:0] VGA_R, // VGA Red[3:0]
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output [3:0] VGA_G, // VGA Green[3:0]
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output [3:0] VGA_B, // VGA Blue[3:0]
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// Audio CODEC
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inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
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input AUD_ADCDAT, // Audio CODEC ADC Data
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inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
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output AUD_DACDAT, // Audio CODEC DAC Data
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inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
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output AUD_XCK, // Audio CODEC Chip Clock
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// GPIO
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inout [35:0] GPIO_0, // GPIO Connection 0
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inout [35:0] GPIO_1 // GPIO Connection 1
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);
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localparam FRQ = 24000000; // 24MHz
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// system clock and reset
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wire clk, rst;
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// debounced button signals
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wire [3:0] btn;
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// 7 segment display negated signals
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wire [31:0] seg7;
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// 1-wire
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wire [1:0] owr_p;
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wire [1:0] owr_e;
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wire [1:0] owr_i;
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// All inout port turn to tri-state
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assign SD_DAT = 1'bz;
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//assign I2C_SDAT = 1'bz;
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assign AUD_ADCLRCK = 1'bz;
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assign AUD_DACLRCK = 1'bz;
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assign AUD_BCLK = 1'bz;
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assign GPIO_0 = 36'hzzzzzzzzz;
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assign GPIO_1 = 36'hzzzzzzzzz;
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// set system clock to 24MHz
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assign clk = CLOCK_24[0];
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assign rst = btn[0];
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// debouncing of command buttons (buttons are active low)
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debouncer #(.CN (FRQ/100)) debouncer_i [3:0] (.clk (clk), .d_i (~KEY), .d_o (btn));
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// soc_nios RTL instance
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soc soc_i (
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// 1) global signals:
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.clk (clk),
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.reset_n (~rst),
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// the_epcs_flash
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.ds_MISO_from_the_epcs_flash (),
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// the_pio_7seg
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.out_port_from_the_pio_7seg (seg7),
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// the_pio_ledg
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.out_port_from_the_pio_ledg (LEDG),
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// the_pio_ledr
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.out_port_from_the_pio_ledr (LEDR),
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// the_sdram
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.zs_cke_from_the_sdram (DRAM_CKE),
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.zs_cs_n_from_the_sdram (DRAM_CS_N),
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.zs_we_n_from_the_sdram (DRAM_WE_N),
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.zs_cas_n_from_the_sdram (DRAM_CAS_N),
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.zs_ras_n_from_the_sdram (DRAM_RAS_N),
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.zs_ba_from_the_sdram (DRAM_BA),
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.zs_addr_from_the_sdram (DRAM_ADDR),
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.zs_dq_to_and_from_the_sdram (DRAM_DQ),
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.zs_dqm_from_the_sdram (DRAM_DQM),
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// the_tri_state_bridge_flash_avalon_slave
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.select_n_to_the_cfi_flash (FL_CE_N),
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.write_n_to_the_cfi_flash (FL_WE_N),
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.read_n_to_the_cfi_flash (FL_OE_N),
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.address_to_the_cfi_flash (FL_ADDR),
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.data_to_and_from_the_cfi_flash (FL_DQ),
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// the_uart
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.rxd_to_the_uart (UART_TXD),
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.txd_from_the_uart (UART_RXD),
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// onewire
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.owr_p_from_the_onewire (owr_p),
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.owr_e_from_the_onewire (owr_e),
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.owr_i_to_the_onewire (owr_i)
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);
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// 1-wire
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assign PS2_DAT = (owr_p [0] | owr_e [0]) ? owr_p [0] : 1'bz;
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assign PS2_CLK = (owr_p [1] | owr_e [1]) ? owr_p [1] : 1'bz;
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assign owr_i = {PS2_CLK, PS2_DAT};
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// SDRAM Interface
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assign DRAM_CLK = ~clk; // SDRAM Clock
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// Flash Interface
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assign FL_RST_N = ~rst; // FLASH Reset
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// active low 7 segment outputs
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assign HEX0 = ~seg7[0*8+:7];
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assign HEX1 = ~seg7[1*8+:7];
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assign HEX2 = ~seg7[2*8+:7];
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assign HEX3 = ~seg7[3*8+:7];
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endmodule
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