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btltz |
//File name=Module=SwitchMatrix 2005-04-10 btltz@mail.china.com btltz from CASIC
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//Description: buffered digital SwitchMatrix
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// * 16 x 16 switch connecting sixteen 9-bit FIFO I/O ports to
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// sixteen 9-bit output ports with 16 x 16 x ?? = 256 syn buffers. buffered each point
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//Abbreviations: crd --- credit
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// alw --- allow
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//Origin: SpaceWire Std - Draft-1(Clause 8)of ECSS(European Cooperation for Space Standardization),ESTEC,ESA.
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// SpaceWire Router Requirements Specification Issue 1 Rev 5. Astrium & University of Dundee
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//TODO: make rtl faster
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////////////////////////////////////////////////////////////////////////////////////
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//
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/*synthesis translate off*/
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`timescale 1ns/100ps
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/*synthesis translate on */
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`define reset 1 // WISHBONE standard reset
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module SwitchMatrix #(parameter BW=10, PORTNUM=16, AW=4, // (1byte + 1)Byte-WIDTH 16x16 crossbar swith
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CellDepth =255, // 16x16 beffers x (255Byte x 10-bit / Cell)
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WCCNT = (CellDepth ==255 ? 8 :
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(CellDepth ==511 ? 9 :
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(CellDepth == 1023 ? 10 : 'bx )) ),
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WIDTH_CRD = (CellDepth ==255 && PORTNUM ==16) ? 12 : //255depth x16ports = 4080 Bbytes/column
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((CellDepth ==511 && PORTNUM ==16) ? 13 : //511depth x 16ports = 8176 Bbytes/column
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((CellDepth == 1023 && PORTNUM == 16) ? 14 :
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((CellDepth ==255 && PORTNUM ==8) ? 11 :
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((CellDepth ==511 && PORTNUM ==8) ? 12 :
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((CellDepth ==1023 && PORTNUM ==8) ? 13 :'bx )))))
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)
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( // Byte width data input(output) from(to) FIFO
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output reg [BW-1:0] do [0:PORTNUM-1],
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input [BW-1:0] di [0:PORTNUM-1],
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output [PORTNUM-1:0] PHasData_o, //a output port has data to transmit
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// Configuration Port
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//output [WIDTH_CRD-1:0] crd_o [0:PORTNUM-1], // credit output back to each in line
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output reg [PORTNUM-1:0] sop_ack_o, //level
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input [PORTNUM-1:0] sop_req_i, //pulse
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input [PORTNUM-1:0] eop_i, //pulse
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input [AW-1:0] out_addr_i [0:PORTNUM], //select output column
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//input [PORTNUM-1:0] ld_inaddr_i, ld_outaddr_i,
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//System interface
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input reset, gclk
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);
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parameter True = 1;
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parameter False = 0;
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// unsuported ports array declaration
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input [BW-1:0] do [0:PORTNUM-1];
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wire [BW-1:0] di [0:PORTNUM-1];
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// Register to provide address when write(read) line(column).
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// Each output port = 1 column
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reg [AW-1:0] SelColumn [0:PORTNUM-1]; // for line cells selection//bit width ,depth
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reg [AW-1:0] SelColine [0:PORTNUM-1]; // for MUXes select lines in a column
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wire [PORTNUM-1:0] ld_SelColumn = sop_req_i;
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wire [PORTNUM-1:0] ld_SelColine; // load select lines in a column
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wire [AW1:0] ScheOut; //output from the schedule.Determine which line in a column has priority
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//opposite line| each column
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wire [BW-1:0] CellOut [0:PORTNUM] [0:PORTNUM]; //16x16 *9 from cell fifo to MUXes
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wire [WCCNT-1:0] CellCnt [0:PORTNUM] [0:PORTNUM]; //data num(vectors) in each switch cell
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// Cell Control Lines
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reg [PORTNUM-1:0] wr_en [0:PORTNUM-1];
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reg [PORTNUM-1:0] rd_en [0:PORTNUM-1];
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wire [PORTNUM-1:0] clrCell[0:PORTNUM];
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wire [PORTNUM-1:0] CellEmpty [0:PORTNUM];
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wire [PORTNUM-1:0] CellFull [0:PORTNUM];
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wire [PORTNUM-1:0] CellAfull [0:PORTNUM]; // buffer cell almost full
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wire [PORTNUM-1:0] CellAempty [0:PORTNUM]; // buffer cell almost empty
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wire [PORTNUM-1:0] CellHasData [0:PORTNUM] = ~CellEmpty; //? is the syntax right ?
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wire [PORTNUM-1:0] CellHasSpc [0:PORTNUM] = ~CellFull;
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// signal for Matrix Output management
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reg [PORTNUM-1:0] columnHasData;
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wire [PORTNUM-1:0] ColumnOE = columnHasData;
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assign PHasData_o = columnHasData; //Port Has Data.Synchronous output to write Tx FIFO
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// reg [WIDTH_CRD-1:0] crdcnt [0:PORTNUM-1];//credit counter
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// assign crd_o = crdcnt;
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/////////////////////////////////////
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// Config input/output address REGs
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//
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always @(posedge gclk)
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begin
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integer i=0;
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if(reset)
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begin
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SelColumn <= 0;
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SelLine <= 0;
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end
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else begin
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for (i=0; i<PORTNUM; i=i+1 )
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begin
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if( ld_SelColumn[i] == True ) // ld_SelColumn = sop_req_i; Note taht the addr must be valid.
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SelColumn[i] <= out_addr_i[i]; // Address Vector load
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if( ld_SelColine[i] == True ) // if the scheduler load output address.
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SelColine[i] <= ScheOut [i]; // Address Vector load
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end
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end
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end
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///////////////////////
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// Matrix Cell buffers
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//
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// note: should select devices that have true dual port RAM
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generate
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begin:GEN_Cell
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genvar i,k;
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for (i=0; i<PORTNUM; i=i+1) // i : each column
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begin
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for (k=0; k<PORTNUM; k=k+1) // k : in a column(sel line)
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begin
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eth_fifo #(parameter DATA_WIDTH=BW, DEPTH=CellDepth) // byte width=9, depth=? undetermined
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Cell_Fifo_Array
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(.data_in ( di[k] ), // different colum has same data input line
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.data_out( CellOut[i][k] ),// k assign to 1 column,i assign to n columns.L<-R
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.write ( wr_en[i][k] ),
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.read ( rd_en[i][k] ),
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.clear ( clrCell[i][k] ),
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.almost_full ( CellAfull[i][k] ),
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.full ( CellFull[i][k] ),
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.almost_empty( CellAempty[i][k] ),
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.empty ( CellEmpty[i][k] ),
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.gclk ( gclk ),
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.reset( reset ),
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.cnt( CellCnt[i][k] ) //may be usable
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);
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end //end 1 column (16x1 )
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end //end 1 array (16x16)
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end //end GEN_Cell
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/////////////////////////////////////////
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// Distribute lines data
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// to the Matrix Cell
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reg [PORTNUM-1:0] wpen ; // Write Packages Enable
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//register sop_req_i or eop_i pulse
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always @(posedge gclk)
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begin
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integer k;
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if(reset==`reset)
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wpen <= 0;
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else begin
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for(k=0; k<PORTNUM; k=k+1)
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begin
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if(eop_i[k])
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wpen[k] <= 1'b0;
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else if(sop_req_i[k])
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wpen[k] <= 1'b1;
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end
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end
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end
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reg [PORTNUM-1:0] wr__; // level signal
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always @(*)
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begin
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for (k =0; k <PORTNUM; k =k+1)
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wr__[k] = ( wpen[k] ==False || eop_i[k]) ? 0 :
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( ( wpen[k] ==True && eop_i[k] ==False ) ? 1'b1 : 'bx );
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end
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//decode config addr according to the external controller
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//(and the package addr head). Generate cell "we" signals array.
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always @(*)
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begin
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integer i,k;
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for (i=0; i<PORTNUM; i=i+1) // i : each column
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begin
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for (k=0; k<PORTNUM; k=k+1) // k : lines in a column(sel line)
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begin
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wr_en[i][k] = ( wr__[i] // write to x column
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&& SelColine[i] ==k // select a line in a column
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&& CellHasSpc[i][k] ==True // that cell is not full
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)
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? 1'b1 : 1'b0;
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sop_ack_o[i] = (SelColine[i] ==k // "select a line" must has been configed
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&& CellHasSpc[i][k] ==True // that cell is not full
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)
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? 1'b1 : 1'b0;
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end
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end
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end
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/////////////////////////
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// Read enable to Tx Fifo
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//
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////////////////////
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// Credit collecting credit information to The Input Line
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// Output Schedulers are responsible for selecting eligible
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always @ (*)
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begin
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integer m;
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for(m=0; m<PORTNUM; m=m+1)
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columnHasData[m] = | celHasData[m];
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// cellHasData[m][0] || cellHasData[m][1] || ...|| cellHasData[m][15]
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end
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//////////////////////////////
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// 16 Output column Schedulers
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//
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//////////////////////////////
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// 1 scheduler is responsible to 32 cell in a column
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generate
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begin:GEN_Schedulers
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for (i=0; i<PORTNUM; i=i+1) // i : each column
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begin
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for (k=0; k<PORTNUM; k=k+1) // k : in a column(sel line)
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begin
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CSer #() inst_CSer
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( .ld_SelCoLine_o( ld_SelColine ),
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.empty_i(CellEmpty[i][k] ), // one-hot input
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.Aempty_i(CellAfull[i][k]), // one-hot
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.addr_o( ScheOut[i] ),
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.reset(reset)
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.gclk(gclk)
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);
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end // end lines in a column
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end // end columns
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end
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endgenerate
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////////////////////////////
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// 16 outputs
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//
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always @(*)
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begin
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integer n;
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for (n=0; n<PORTNUM; n=n+1)
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begin
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if(columOE)
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do[n] = CellOut[SelLine][n]; // n : (port0 -> port15)
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else
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do[n] = 'b0; // 10'b p0_0000_0000
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end // EOP = 10'b p1_0000_0000
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end
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/*///////////////
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// Functions
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//
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function [15:0] greyiDEC4_16; //Grey code input decoder
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input [3:0] in;
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begin
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case (in)
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4'b0000 : greyiDEC4_16 = 16'h1;
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4'b0001 : greyiDEC4_16 = 16'h2;
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4'b0011 : greyiDEC4_16 = 16'h4;
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4'b0010 : greyiDEC4_16 = 16'h8;
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4'b0110 : greyiDEC4_16 = 16'h10;
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4'b0111 : greyiDEC4_16 = 16'h20;
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4'b0101 : greyiDEC4_16 = 16'h40;
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4'b0100 : greyiDEC4_16 = 16'h80;
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4'b1100 : greyiDEC4_16 = 16'h100;
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4'b1101 : greyiDEC4_16 = 16'h200;
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4'b1111 : greyiDEC4_16 = 16'h400;
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4'b1110 : greyiDEC4_16 = 16'h800;
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4'b1010 : greyiDEC4_16 = 16'h1000;
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4'b1011 : greyiDEC4_16 = 16'h2000;
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4'b1001 : greyiDEC4_16 = 16'h4000;
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4'b1000 : greyiDEC4_16 = 16'h8000;
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default : greyiDEC4_16 = 'bx;
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endcase
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end
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endfunction */
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endmodule
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`undef reset
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