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btltz |
//File name=Module name=SPW_FSM 2005-2-18 btltz@mail.china.com btltz from CASIC
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//Description: The state exit conditions for SpaceWire encoder-decoder state machine:
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// Coder/Decoder FSM,also called the PPU(Protocol Processing Unit) Controls the overall operation of the link interface
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//Abbreviations: FCT: flow control token
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// N-Char: normal characters(data or EOP or EEP). L_Chars:Link characters.
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// EOP: End_of_packet marcker; EEP: error End_of_packet marcker.
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//Origin: SpaceWire Std - Draft-1 of ECSS(European Cooperation for Space Standardization),ESTEC,ESA.
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//-- TODO: make rtl faster
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////////////////////////////////////////////////////////////////////////////////////
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//
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//
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/*synthesis translate off*/
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`timescale 1ns/100ps
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/*synthesis translate on */
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`define gFreq 80
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`define ErrorReset 6'b000001
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`define ErrorWait 6'b000010
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`define Ready 6'b000100
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`define Started 6'b001000
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`define Connecting 6'b010000
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`define Run 6'b100000
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`define reset 1 // WISHBONE standard reset
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`define FOR_SIM
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//`define FOR_REAL
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module SPW_FSM //#(parameter DW=8)
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(output [5:0] state_o , //state is a global vector signal of the CODEC
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output active_o, //Active interface
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input lnk_start,lnk_dis, //Link enable interface, set by software or hardware
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input AUTOSTART,
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output reg LINK_ERR_o,
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output reg err_sqc, //err_Nchar or err_FCT as sequence err "should be detected by PPU"
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//Interface with Transmitter
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output RST_tx_o,
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output reg enTx_o, //control output to Transmitter
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input err_crd_i,
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//Interface with Receiver
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output RST_rx_o,
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output reg enRx_o, //control output to Receiver
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input Lnk_dsc_i,
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input gotBit_i,
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gotFCT_i,gotNchar_i,gotTime_i,gotNULL_i,
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err_par_i,err_esc_i,err_dsc_i, //input from receiver
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//global signal input
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input reset,
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input gclk /* synthesis syn_isclock = 1 */
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);
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parameter StateNum = 6;
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parameter ErrorReset = `ErrorReset; //6'b000001;
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parameter ErrorWait = `ErrorWait; //6'b000010;
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parameter Ready = `Ready; //6'b000100;
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parameter Started = `Started; //6'b001000;
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parameter Connecting = `Connecting; //6'b010000;
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parameter Run = `Run; //6'b100000;
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parameter DEFLT = 6'bxxxxxx;//6'bxxxxxx;
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parameter True = 1, False = 0;
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`ifdef FOR_SIM
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parameter NUM_T6_4uS = 10 , NUM_T12_8uS = 20;
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`else
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parameter NUM_T6_4uS = (`gFreq==80) ? (64*8-1) :
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(`gFreq==100) ? (64*10-1) :
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(`gFreq==120) ? (64*12-1) :
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(`gFreq==50) ? (64*5-1);
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parameter NUM_T12_8uS =(`gFreq==80) ? (128*8-1) :
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(`gFreq==100) ? (128*10-1) :
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(`gFreq==120) ? (128*12-1) :
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(`gFreq==50) ? (128*5-1);
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`endif
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parameter TIMERW = 14; //Timer width MAX=16,384. *1ns for 16us
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reg [StateNum-1:0] state, next_state/* synthesis syn_encoding="safe,onhot" */;
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reg t6_4us,t12_8us; //The output of the timer indicate if adequate time has elapsed
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///////////////////
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// Output Generate
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//
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reg HASgotNULL;
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reg HASgotBit;
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always @(posedge gclk)
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if(reset ||state==ErrorReset)
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begin
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HASgotNULL <= 0;
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HASgotBit <= 0;
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end
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else begin
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if(gotNULL_i)
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HASgotNULL <= 1'b1;
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if(gotBit_i)
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HASgotBit <= 1'b1;
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end
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assign RST_tx_o = reset || (state == ErrorReset || state==ErrorWait || state==Ready);
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assign RST_rx_o = reset || (state == ErrorReset);
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assign state_o = state;
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assign lnk_en = ~lnk_dis && ( lnk_start || (AUTOSTART && HASgotNULL) );//internal "lnk_en" to enable link
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assign active_o = lnk_en &&
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( !Lnk_dsc_i //indicate Rx is receiving
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|| state==Started || state==Connecting || state==Run );//indicate Tx is transmitting
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////////////////////////////
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// err_sqc made
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// Charactor sequence error
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always @(posedge gclk)
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if(reset)
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err_sqc <= 0;
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else begin
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err_sqc <= 0;
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if( gotFCT_i && (state==ErrorWait || state==Ready || state==Started)
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|| gotNchar_i && state!=Run )
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err_sqc <= 1; //character sequence error can only occur during initialization.
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end
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//////////////////////
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// PPU (fsm)
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//
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always @(posedge gclk)
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begin:STATES_TRANSFER
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if (reset || lnk_dis || Lnk_dsc_i)
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state <= ErrorReset; //Initialized state
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else // state transfer
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state <= next_state;
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end //end block "STATES_TRANSFER"
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//------ next_state assignment
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always @(*)
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begin:NEXT_ASSIGN
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//Default Values for FSM outputs:
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/*RST_tx_o = 1'b0; //not reset
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RST_rx_o = 1'b0; */
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enRx_o = 1'b1;
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enTx_o = 1'b0;
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LINK_ERR_o = 1'b0;
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//Use "Default next_state" style ->
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next_state = state;
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case(state) /* synthesis parallel_case */
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ErrorReset : begin/*Time-lapse*///Entered when the link interface is reset, when the link is disabled [Link Disabled] in the
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//Run state, or when error conditions occur in any other state.
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enRx_o = 1'b0;
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//The error detecting end shall be reset and re-initialized to recover character synchronization and flow control status.
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if(lnk_en && t6_4us==True)
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next_state = ErrorWait;
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end
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ErrorWait: begin/*Time-lapse*///Entered from ErrorReset state after being in ErrorReset state for 6,4us
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if(HASgotBit && lnk_dis
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|| HASgotNULL && (err_par_i || err_esc_i || gotFCT_i || gotNchar_i || gotTime_i) )
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next_state = ErrorReset;
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else if(lnk_en && t12_8us==True)
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next_state = Ready;
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end
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Ready/*Temp*/ : begin //Entered from ErrorWait state after being in ErrorWait state for 12,8us
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if( HASgotBit && err_dsc_i
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|| HASgotNULL && (err_par_i || err_esc_i || gotFCT_i || gotNchar_i || gotTime_i) )
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next_state = ErrorReset;
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else if(lnk_en)
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next_state = Started;
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end
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Started : begin //Entered from Ready state when [LinkEnabled] guard is TRUE
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enTx_o = 1'b1;
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if( (t12_8us==True) || //after 12,8us
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HASgotBit && err_dsc_i ||
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HASgotNULL && (err_par_i || err_esc_i || gotFCT_i || gotNchar_i || gotTime_i) )
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next_state = ErrorReset; //GotNULL Timeout
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else if (gotNULL_i ==True)
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next_state = Connecting;
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end
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Connecting : begin //Entered from Started state on receipt of gotNULL (which also satisfies First Bit Received)
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enTx_o = 1'b1;
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if( (t12_8us==True) || //gotFCT Timeout
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(err_dsc_i==True) || //First Bit Received as part of the gotNULL
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err_par_i || //First NULL Received is already True in order to enter this state
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err_esc_i || //First NULL Received is already True in order to enter this state
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gotNchar_i || //First NULL Received is already True in order to enter this state
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gotTime_i ) //First NULL Received is already True in order to enter this state
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next_state = ErrorReset;
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else if(gotFCT_i==True)
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next_state = Run;
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end
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Run : begin //Entered from Connecting state when FCT received. First Bit Received and
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//gotNULL conditions are TRUE since they were True in Connecting state.
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enTx_o = 1'b1;
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if( lnk_dis
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|| err_dsc_i //First Bit Received is already True since passed through Connecting State
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|| err_par_i //First NULL Received is already True since passed through Connecting State
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|| err_esc_i //First NULL Received is already True since passed through Connecting State
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|| err_crd_i //First NULL Received is already True since passed through Connecting State
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|| err_sqc )//If the escape error occurs in the Run state then the escape error shall be flagged up to the Network Level as a "link error"
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begin
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LINK_ERR_o = 1'b1;
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next_state = ErrorReset;
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end
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end
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/* Default assignment for simulation */
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default : next_state = DEFLT;
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endcase
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end //end block NEXT_ASSIGN(and output assignment)
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//////////////////////////////////
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// The Timer for 6.4us & 12.8us
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reg [TIMERW-1:0] timer;
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always @(posedge gclk)
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begin:TIMER
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if(reset || (state==Run) || (state==Ready) || ( (state==Started) && gotNULL_i ) )
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begin
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t6_4us <= 1'b0;
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t12_8us <= 1'b0;
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timer <= 0;
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end
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else if (timer == NUM_T12_8uS)
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begin
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t12_8us <= 1'b1; //Timer overflow pulse to trigger states transform
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t6_4us <= 1'b0;
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timer <= 0;
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end
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else if ( (state==ErrorReset) && (timer ==NUM_T6_4uS ) )
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begin
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t6_4us <= 1'b1;
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timer <= 0;
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t12_8us <= 1'b0;
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end
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else
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begin
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t6_4us <= 1'b0;
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t12_8us <= 1'b0;
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timer <= timer + 1'b1;
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end
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end //End block "TIMER" ...
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//...................................................................................
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endmodule
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`undef ErrorReset
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`undef ErrorWait
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`undef Ready
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`undef Started
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`undef Connecting
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`undef Run
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`undef reset
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