| 1 |
2 |
btltz |
//File name=Module=SwitchCore 2005-3-18 btltz@mail.china.com btltz from CASIC
|
| 2 |
|
|
//Description: The SpaceWire Routing Switch core(routing matrix).
|
| 3 |
|
|
// Can be used as a standalone module or connected to the CODEC Core to
|
| 4 |
|
|
// form a complete SpaceWire Routing Switch (Router).
|
| 5 |
|
|
//Origin: SpaceWire Std - Draft-1(Clause 9/10) of ECSS(European Cooperation for Space Standardization),ESTEC,ESA.
|
| 6 |
|
|
// SpaceWire Router Requirements Specification Issue 1 Rev 5. Astrium & University of Dundee
|
| 7 |
|
|
//-- TODO: make the rtl faster
|
| 8 |
|
|
////////////////////////////////////////////////////////////////////////////////////
|
| 9 |
|
|
//
|
| 10 |
6 |
btltz |
/*synthesize translate_off*/
|
| 11 |
2 |
btltz |
`timescale 1ns/10ps
|
| 12 |
6 |
btltz |
/*synthesize translate_on */
|
| 13 |
|
|
`define reset 1 // WISHBONE standard reset
|
| 14 |
|
|
`define TOOL_NOTSUP_PORT_ARRAY //if the tools not support port array declaration
|
| 15 |
2 |
btltz |
|
| 16 |
6 |
btltz |
module SwitchCore #(parameter DW=10,PORTNUM=16,GPIO_NUM=3) // Actual 17 ==16 +1(external port)
|
| 17 |
|
|
( // Input data interface
|
| 18 |
|
|
output[PORTNUM-1:0] full_o,
|
| 19 |
|
|
`ifdef TOOL_NOTSUP_PORT_ARRAY
|
| 20 |
|
|
output [DW-1:0] dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7,
|
| 21 |
|
|
dout8,dout9,dout10,dout11,dout12,dout13,dout14,dout15, // Note that these is physical order.
|
| 22 |
|
|
input [DW-1:0] din0,din1,din2,din3,din4,din5,din6,din7, // eg. dout0 is routing logical port1
|
| 23 |
|
|
din8,din9,din10,din11,din12,din13,din14,din15, // because port0 is reserved for config
|
| 24 |
|
|
`else
|
| 25 |
|
|
output [DW-1:0] dout [PORTNUM-1:0],
|
| 26 |
|
|
input [DW-1:0] din [PORTNUM-1:0],
|
| 27 |
|
|
`endif
|
| 28 |
2 |
btltz |
|
| 29 |
6 |
btltz |
input [PORTNUM-1:0] wr_i,
|
| 30 |
|
|
// Output data interface
|
| 31 |
|
|
output [PORTNUM-1:0] empty_o,
|
| 32 |
2 |
btltz |
input rd_i,
|
| 33 |
|
|
input active_i,
|
| 34 |
6 |
btltz |
// GPIO ports
|
| 35 |
|
|
inout [GPIO_NUM-1:0] GPIO,
|
| 36 |
|
|
// global signal input
|
| 37 |
|
|
input reset, gclk // approximate 120Mhz, could also drive Xilinx gigabit transceiver.
|
| 38 |
2 |
btltz |
);
|
| 39 |
|
|
|
| 40 |
|
|
// parameter ;
|
| 41 |
|
|
|
| 42 |
6 |
btltz |
////////////////////
|
| 43 |
|
|
// Instantiation
|
| 44 |
|
|
//
|
| 45 |
2 |
btltz |
|
| 46 |
6 |
btltz |
SwitchMatrix #() inst_SwitchMatrix (
|
| 47 |
2 |
btltz |
);
|
| 48 |
|
|
|
| 49 |
6 |
btltz |
// 16 inputs Line Schedulers
|
| 50 |
|
|
// 1 scheduler is responsible to 1 input line, distribute data into one column
|
| 51 |
|
|
generate
|
| 52 |
|
|
begin:GEN_LSers
|
| 53 |
|
|
genvar i, k;
|
| 54 |
|
|
for (i=0; i<PORTNUM; i=i+1) // i : each column
|
| 55 |
|
|
begin
|
| 56 |
|
|
for (k=0; k<PORTNUM; k=k+1) // k : in a column(sel line)
|
| 57 |
|
|
begin
|
| 58 |
|
|
LSer #() inst_LSer
|
| 59 |
|
|
( .ld_SelColumn_o( ld_SelColumn ),
|
| 60 |
|
|
.empty_i(CellEmpty[i][k] ), // one-hot input
|
| 61 |
|
|
.Aempty_i(CellAfull[i][k]), // one-hot
|
| 62 |
|
|
.addr_o( ScheOut[i] ),
|
| 63 |
|
|
.reset(reset)
|
| 64 |
|
|
.gclk(gclk)
|
| 65 |
|
|
);
|
| 66 |
|
|
end // end lines in a column
|
| 67 |
|
|
end // end columns
|
| 68 |
|
|
end
|
| 69 |
|
|
endgenerate
|
| 70 |
|
|
|
| 71 |
|
|
endmodule
|
| 72 |
|
|
|
| 73 |
|
|
`undef reset
|
| 74 |
|
|
`undef TOOL_NOTSUP_PORT_ARRAY
|
