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//File name=Module=SwitchMatrix  2005-04-10      btltz@mail.china.com    btltz from CASIC  
//Description:     buffered digital SwitchMatrix  to simplify design, avoid HOL.
//                 * 16 x 16 switch connecting sixteen 9-bit FIFO I/O ports to 
//                      sixteen 10-bit output ports with  16 x 16 (x depth) = 256 syn buffers. buffered each point
//Abbreviations:         crd  --- credit
//                                               alw  --- allow
//Origin:  SpaceWire Std - Draft-1(Clause 8)of ECSS(European Cooperation for Space Standardization),ESTEC,ESA.
//         SpaceWire Router Requirements Specification Issue 1 Rev 5. Astrium & University of Dundee 
//TODO:   make rtl faster
////////////////////////////////////////////////////////////////////////////////////
//
/*synthesis translate_off*/
`include "timescale.v"
/*synthesis translate_on */
`define reset  1                // WISHBONE standard reset
`define TOOL_NOTSUP_PORT_ARRAY //if the tool's support port array declaration  
 
module SwitchMatrix #(parameter BW=10, PORTNUM=16, AW=4,  // (1byte + 1)Byte-WIDTH 16x16 crossbar swith
                                CellDepth =255,           // 16x16 beffers x (255Byte x 10-bit / Cell) 
                                                                                  WCCNT = (CellDepth ==255 ? 8 :
                                                                                           (CellDepth ==511 ? 9  :
                                                                                                           (CellDepth == 1023 ? 10 : 'bx  )) ),
                                                                                  WIDTH_CRD = (CellDepth ==255 && PORTNUM ==16) ? 12 :  //255depth x16ports = 4080 Bbytes/column
                                                                                                           (CellDepth ==511 && PORTNUM ==16 ? 13 : //511depth x 16ports = 8176  Bbytes/column
                                                                                                                         (CellDepth == 1023 && PORTNUM == 16 ? 14 :
                                            (CellDepth ==255 && PORTNUM ==8 ? 11 :
                                                                                                                   (CellDepth ==511 && PORTNUM ==8 ? 12 :
                                                                                                                         (CellDepth ==1023 && PORTNUM ==8 ? 13 :'bx )))))
                                                         )
                ( // Byte width data input(output) from(to) FIFO
                                  `ifdef TOOL_NOTSUP_PORT_ARRAY
                                                                 output [BW-1:0] do0,do1,do2,do3,do4,do5,do6,do7,
                                                                                 do8,do9,do10,do11,d12,do13,do14,do15,
                         input  [BW-1:0] di0,di1,di2,di3,di4,di5,di6,di7,
                                                                                 di8,di9,di10,di11,di12,di13,di14,di15,
                         `else
                                                            output reg [BW-1:0] do [0:PORTNUM-1],
                                                            input  [BW-1:0] di [0:PORTNUM-1],
                                                                `endif
 
                                                                 output [PORTNUM-1:0] PHasData_o,   //a output port has data to transmit
                 // Configuration Port
                                  //output [WIDTH_CRD-1:0] crd_o [0:PORTNUM-1], // credit output back to each in line
                                   output reg [PORTNUM-1:0] sop_ack_o,       //level
                                                                 input [PORTNUM-1:0] sop_req_i,       //pulse                                                            
                                                                 input [PORTNUM-1:0]     eop_i,               //pulse
                                                                `ifdef TOOL_NOTSUP_PORT_ARRAY
                                                                 input cfg_data0_i,  cfg_data1_i,  cfg_data2_i,  cfg_data3_i,
                                                                                 cfg_data4_i,  cfg_data5_i,  cfg_data6_i,  cfg_data7_i,
                                                                                 cfg_data8_i,  cfg_data9_i,  cfg_data10_i, cfg_data11_i,
                                                                                 cfg_data12_i, cfg_data13_i, cfg_data14_i, cfg_data15_i,
                        `else
                                                                 input [PORTNUM-1:0] cfg_data_i [0:PORTNUM-1],
                        `endif
 
                                                                `ifdef TOOL_NOTSUP_PORT_ARRAY
                                                                 input [AW-1:0] out_addr0_i,out_addr1_i,out_addr2_i,out_addr3_i,
                                                                                out_addr4_i,out_addr5_i,out_addr6_i,out_addr7_i,
                                                                                                         out_addr8_i,out_addr9_i,out_addr10_i,out_addr11_i,
                                                                                                         out_addr12_i,out_addr13_i,out_addr14_i,out_addr15_i,
                                                                `else
                                                                 input [AW-1:0] out_addr_i [0:PORTNUM],   //select output column                                                           
                                                                `endif
                                                            //input [PORTNUM-1:0] ld_inaddr_i, ld_outaddr_i,
       // System interface
                                                                 input reset, gclk
                                                          );
                                                              parameter True  = 1;
                                                              parameter False = 0;
 
`ifdef TOOL_NOTSUP_PORT_ARRAY
reg [BW-1:0] do [0:PORTNUM-1];
wire [BW-1:0] di [0:PORTNUM-1];
assign di0 = di[0],   di1 = di[1],   di2 = di[2],   di3 = di[3],
       di4 = di[4],   di5 = di[5],   di6 = di[6],   di7 = di[7],
                 di8 = di[9],   di9 = di[9],   di10 = di[10], di11 = di[11],
                 di12 = di[12], di13 = di[13], di14 = di[14], di15 = di[15];
assign do0 = do[0],   do1 = do[1],   do2 = do[2],   do3 = do[3],
       do4 = do[4],   do5 = do[5],   do6 = do[6],   do7 = do[7],
                 do8 = do[9],   do9 = do[9],   do10 = do[10], do11 = do[11],
                 do12 = do[12], do13 = do[13], do14 = do[14], do15 = do[15];
`endif
 
// Register to provide address when write(read) line(column).
// Each output port = 1 column
reg [AW-1:0] SelColumn [0:PORTNUM-1];       // for line cells selection//bit width ,depth
reg [AW-1:0] SelColine [0:PORTNUM-1];          // for MUXes        select lines in a column 
wire [PORTNUM-1:0] ld_SelColumn = sop_req_i;
wire [PORTNUM-1:0] ld_SelColine;             // load select lines in a column
 
wire [AW-1:0] ScheOut;  //output from the schedule.Determine which line in a column has priority 
 
                                                          //opposite line| each column
wire [BW-1:0] CellOut    [0:PORTNUM]    [0:PORTNUM];        //16x16 *9 from cell fifo to MUXes                           
wire [WCCNT-1:0] CellCnt [0:PORTNUM]    [0:PORTNUM];  //data num(vectors) in each switch cell     
// Cell Control Lines
reg [PORTNUM-1:0] wr_en  [0:PORTNUM-1];
reg [PORTNUM-1:0] rd_en  [0:PORTNUM-1];
wire [PORTNUM-1:0] clrCell[0:PORTNUM-1];
wire [PORTNUM-1:0] CellEmpty [0:PORTNUM-1];
wire [PORTNUM-1:0] CellFull  [0:PORTNUM-1];
wire [PORTNUM-1:0] CellAfull  [0:PORTNUM-1];                    // buffer cell almost full 
wire [PORTNUM-1:0] CellAempty  [0:PORTNUM-1];                                               // buffer cell almost empty
 
wire [PORTNUM-1:0] CellHasData [0:PORTNUM-1] = ~CellEmpty;      //? is the syntax right ? 
wire [PORTNUM-1:0] CellHasSpc  [0:PORTNUM-1] = ~CellFull;
 
 
// signal for Matrix Output management
reg [PORTNUM-1:0] columnHasData;
wire [PORTNUM-1:0] ColumnOE = columnHasData;
assign PHasData_o           = columnHasData; //Port Has Data.Synchronous output to write Tx FIFO
 
// reg [WIDTH_CRD-1:0] crdcnt [0:PORTNUM-1];//credit counter
// assign crd_o = crdcnt;
 
/////////////////////////////////////
// Config input/output address REGs
//  
always @(posedge gclk)
begin
integer i=0;
if(reset)
     begin
     SelColumn <= 0;
     SelLine <= 0;
     end
else begin
     for (i=0; i<PORTNUM; i=i+1 )
       begin
                 if( ld_SelColumn[i] == True )      // ld_SelColumn = sop_req_i; Note taht the addr must be valid.
              SelColumn[i] <= out_addr_i[i];     //   Address Vector load
            if( ld_SelColine[i] == True )           // if the scheduler load output address.
              SelColine[i] <= ScheOut [i];          //   Address Vector load
            end
     end
end
 
///////////////////////
// Matrix Cell buffers
//
// note: should select devices that have true dual port RAM       
 
generate
begin:GEN_Cell
genvar i,k;
for (i=0; i<PORTNUM; i=i+1)       // i : each column
begin
   for (k=0; k<PORTNUM; k=k+1)    // k : in a column(sel line)
        begin
        eth_fifo  #(parameter DATA_WIDTH=BW, DEPTH=CellDepth)     // byte width=9, depth=? undetermined
                 Cell_Fifo_Array
                 (.data_in ( di[k] ),          // different colum has same data input line
                                 .data_out( CellOut[i][k] ),// k assign to 1 column,i assign to n columns.L<-R                   
                                 .write   ( wr_en[i][k] ),
                                 .read    ( rd_en[i][k] ),
                                 .clear   ( clrCell[i][k] ),
                                 .almost_full ( CellAfull[i][k] ),
                                 .full        ( CellFull[i][k] ),
                                 .almost_empty( CellAempty[i][k] ),
                                 .empty       ( CellEmpty[i][k] ),
                                 .gclk  ( gclk ),
                                 .reset( reset ),
                                 .cnt( CellCnt[i][k] )      //may be usable
                                 );
    end  //end 1 column (16x1 )
end        //end 1 array  (16x16) 
end      //end GEN_Cell 
 
 
 
/////////////////////////////////////////
// Distribute lines data 
//     to the Matrix Cell       
reg [PORTNUM-1:0] wpen ;     // Write Packages Enable
 
//register sop_req_i or eop_i pulse
always @(posedge gclk)
begin
integer k;
if(reset==`reset)
  wpen <= 0;
else begin
     for(k=0; k<PORTNUM; k=k+1)
          begin
              if(eop_i[k])
                     wpen[k] <= 1'b0;
         else if(sop_req_i[k])
                     wpen[k] <= 1'b1;
        end
           end
end
 
reg [PORTNUM-1:0] wr__;            // level signal
 
always @(*)
begin
 for (k =0; k <PORTNUM; k =k+1)
  wr__[k] =  ( wpen[k] ==False || eop_i[k])  ?   0   :
             ( ( wpen[k] ==True && eop_i[k] ==False )  ?   1'b1 : 'bx       );
end
 
//decode config addr according to the external controller
//(and the package addr head). Generate cell "we" signals array.
always @(*)
begin
integer i,k;
  for (i=0; i<PORTNUM; i=i+1)       // i : each column
  begin
    for (k=0; k<PORTNUM; k=k+1)     // k : lines in a column(sel line)
         begin
      wr_en[i][k] = ( wr__[i]                     // write to x column 
                                &&  SelColine[i] ==k              // select a line in a column
                                                         &&  CellHasSpc[i][k] ==True // that cell is not full
                                                   )
                                                           ?   1'b1  :  1'b0;
     sop_ack_o[i] = (SelColine[i] ==k                   // "select a line" must has been configed
                                                         &&  CellHasSpc[i][k] ==True // that cell is not full
                                                        )
                                                           ?   1'b1  :  1'b0;
         end
  end
end
 
 
/////////////////////////
// Read enable to Tx Fifo
//
////////////////////
// Credit collecting credit information to The Input Line
// Output Schedulers    are responsible for selecting eligible 
 
always @ (*)
begin
integer m;
  for(m=0; m<PORTNUM; m=m+1)
        columnHasData[m] = | celHasData[m];
        // cellHasData[m][0] || cellHasData[m][1] || ...|| cellHasData[m][15]                                           
end
 
 
//////////////////////////////
// 16 outputs Column Schedulers 
//
//////////////////////////////
// 1 scheduler is responsible to 32 cell in a column
 
generate
begin:GEN_CSers
genvar i, k;
 for (i=0; i<PORTNUM; i=i+1)       // i : each column
 begin:inst_column
   for (k=0; k<PORTNUM; k=k+1)     // k : in a column(sel line)
        begin:inst_line
     CSer    inst_CSer
                     ( .ld_SelCoLine_o( ld_SelColine ),
                                           .empty_i(CellEmpty[i][k] ),      // one-hot input
                                                .Aempty_i(CellAfull[i][k]),             // one-hot
                                           .addr_o( ScheOut[i] ),
                                                .reset(reset)
                                                .gclk(gclk)
                                          );
   end  // end lines in a column
 end    // end columns
end
endgenerate
 
////////////////////////////
//      16 outputs
// 
always @(*)
begin
integer n;
 for (n=0; n<PORTNUM; n=n+1)
    begin
         if(columOE)
         do[n] = CellOut[SelLine][n];     // n : (port0 -> port15)
         else
         do[n] = 'b0;                   //       10'b p0_0000_0000  
    end                                                                   // EOP = 10'b p1_0000_0000
end
 
 
/*///////////////
// Functions
//
function [15:0] greyiDEC4_16;  //Grey code input decoder
input [3:0] in;
begin
case (in)
        4'b0000 : greyiDEC4_16 = 16'h1;
        4'b0001 : greyiDEC4_16 = 16'h2;
        4'b0011 : greyiDEC4_16 = 16'h4;
        4'b0010 : greyiDEC4_16 = 16'h8;
        4'b0110 : greyiDEC4_16 = 16'h10;
        4'b0111 : greyiDEC4_16 = 16'h20;
        4'b0101 : greyiDEC4_16 = 16'h40;
        4'b0100 : greyiDEC4_16 = 16'h80;
        4'b1100 : greyiDEC4_16 = 16'h100;
        4'b1101 : greyiDEC4_16 = 16'h200;
        4'b1111 : greyiDEC4_16 = 16'h400;
        4'b1110 : greyiDEC4_16 = 16'h800;
        4'b1010 : greyiDEC4_16 = 16'h1000;
        4'b1011 : greyiDEC4_16 = 16'h2000;
        4'b1001 : greyiDEC4_16 = 16'h4000;
        4'b1000 : greyiDEC4_16 = 16'h8000;
        default : greyiDEC4_16 = 'bx;
endcase
end
endfunction     */
 
endmodule
 
`undef reset
`undef TOOL_NOTSUP_PORT_ARRAY

Line No.	Rev	Author	Line
1	2	btltz	`//File name=Module=SwitchMatrix 2005-04-10 btltz@mail.china.com btltz from CASIC`
2	6	btltz	`//Description: buffered digital SwitchMatrix to simplify design, avoid HOL.`
3	2	btltz	`// * 16 x 16 switch connecting sixteen 9-bit FIFO I/O ports to`
4	6	btltz	`// sixteen 10-bit output ports with 16 x 16 (x depth) = 256 syn buffers. buffered each point`
5	2	btltz	`//Abbreviations: crd --- credit`
6			`// alw --- allow`
7			`//Origin: SpaceWire Std - Draft-1(Clause 8)of ECSS(European Cooperation for Space Standardization),ESTEC,ESA.`
8			`// SpaceWire Router Requirements Specification Issue 1 Rev 5. Astrium & University of Dundee`
9			`//TODO: make rtl faster`
10			`////////////////////////////////////////////////////////////////////////////////////`
11			`//`
12	6	btltz	`/synthesis translate_off/`
13			`include "timescale.v"
14			`/synthesis translate_on /`
15	2	btltz	`define reset 1 // WISHBONE standard reset
16	6	btltz	`define TOOL_NOTSUP_PORT_ARRAY //if the tool's support port array declaration
17	2	btltz
18			`module SwitchMatrix #(parameter BW=10, PORTNUM=16, AW=4, // (1byte + 1)Byte-WIDTH 16x16 crossbar swith`
19			`CellDepth =255, // 16x16 beffers x (255Byte x 10-bit / Cell)`
20			`WCCNT = (CellDepth ==255 ? 8 :`
21			`(CellDepth ==511 ? 9 :`
22			`(CellDepth == 1023 ? 10 : 'bx )) ),`
23			`WIDTH_CRD = (CellDepth ==255 && PORTNUM ==16) ? 12 : //255depth x16ports = 4080 Bbytes/column`
24	6	btltz	`(CellDepth ==511 && PORTNUM ==16 ? 13 : //511depth x 16ports = 8176 Bbytes/column`
25			`(CellDepth == 1023 && PORTNUM == 16 ? 14 :`
26			`(CellDepth ==255 && PORTNUM ==8 ? 11 :`
27			`(CellDepth ==511 && PORTNUM ==8 ? 12 :`
28			`(CellDepth ==1023 && PORTNUM ==8 ? 13 :'bx )))))`
29	2	btltz	`)`
30			`( // Byte width data input(output) from(to) FIFO`
31	6	btltz	`ifdef TOOL_NOTSUP_PORT_ARRAY
32			`output [BW-1:0] do0,do1,do2,do3,do4,do5,do6,do7,`
33			`do8,do9,do10,do11,d12,do13,do14,do15,`
34			`input [BW-1:0] di0,di1,di2,di3,di4,di5,di6,di7,`
35			`di8,di9,di10,di11,di12,di13,di14,di15,`
36			`else
37	2	btltz	`output reg [BW-1:0] do [0:PORTNUM-1],`
38	6	btltz	`input [BW-1:0] di [0:PORTNUM-1],`
39			`endif
40	2	btltz
41			`output [PORTNUM-1:0] PHasData_o, //a output port has data to transmit`
42	6	btltz	`// Configuration Port`
43	2	btltz	`//output [WIDTH_CRD-1:0] crd_o [0:PORTNUM-1], // credit output back to each in line`
44	6	btltz	`output reg [PORTNUM-1:0] sop_ack_o, //level`
45	2	btltz	`input [PORTNUM-1:0] sop_req_i, //pulse`
46	6	btltz	`input [PORTNUM-1:0] eop_i, //pulse`
47			`ifdef TOOL_NOTSUP_PORT_ARRAY
48			`input cfg_data0_i, cfg_data1_i, cfg_data2_i, cfg_data3_i,`
49			`cfg_data4_i, cfg_data5_i, cfg_data6_i, cfg_data7_i,`
50			`cfg_data8_i, cfg_data9_i, cfg_data10_i, cfg_data11_i,`
51			`cfg_data12_i, cfg_data13_i, cfg_data14_i, cfg_data15_i,`
52			`else
53			`input [PORTNUM-1:0] cfg_data_i [0:PORTNUM-1],`
54			`endif
55
56			`ifdef TOOL_NOTSUP_PORT_ARRAY
57			`input [AW-1:0] out_addr0_i,out_addr1_i,out_addr2_i,out_addr3_i,`
58			`out_addr4_i,out_addr5_i,out_addr6_i,out_addr7_i,`
59			`out_addr8_i,out_addr9_i,out_addr10_i,out_addr11_i,`
60			`out_addr12_i,out_addr13_i,out_addr14_i,out_addr15_i,`
61			`else
62			`input [AW-1:0] out_addr_i [0:PORTNUM], //select output column`
63			`endif
64	2	btltz	`//input [PORTNUM-1:0] ld_inaddr_i, ld_outaddr_i,`
65	6	btltz	`// System interface`
66	2	btltz	`input reset, gclk`
67	6	btltz	`);`
68			`parameter True = 1;`
69			`parameter False = 0;`
70	2	btltz
71	6	btltz	`ifdef TOOL_NOTSUP_PORT_ARRAY
72			`reg [BW-1:0] do [0:PORTNUM-1];`
73			`wire [BW-1:0] di [0:PORTNUM-1];`
74			`assign di0 = di[0], di1 = di[1], di2 = di[2], di3 = di[3],`
75			`di4 = di[4], di5 = di[5], di6 = di[6], di7 = di[7],`
76			`di8 = di[9], di9 = di[9], di10 = di[10], di11 = di[11],`
77			`di12 = di[12], di13 = di[13], di14 = di[14], di15 = di[15];`
78			`assign do0 = do[0], do1 = do[1], do2 = do[2], do3 = do[3],`
79			`do4 = do[4], do5 = do[5], do6 = do[6], do7 = do[7],`
80			`do8 = do[9], do9 = do[9], do10 = do[10], do11 = do[11],`
81			`do12 = do[12], do13 = do[13], do14 = do[14], do15 = do[15];`
82			`endif
83	2	btltz
84			`// Register to provide address when write(read) line(column).`
85			`// Each output port = 1 column`
86			`reg [AW-1:0] SelColumn [0:PORTNUM-1]; // for line cells selection//bit width ,depth`
87			`reg [AW-1:0] SelColine [0:PORTNUM-1]; // for MUXes select lines in a column`
88			`wire [PORTNUM-1:0] ld_SelColumn = sop_req_i;`
89			`wire [PORTNUM-1:0] ld_SelColine; // load select lines in a column`
90
91	6	btltz	`wire [AW-1:0] ScheOut; //output from the schedule.Determine which line in a column has priority`
92	2	btltz
93			`//opposite line\| each column`
94			`wire [BW-1:0] CellOut [0:PORTNUM] [0:PORTNUM]; //16x16 *9 from cell fifo to MUXes`
95			`wire [WCCNT-1:0] CellCnt [0:PORTNUM] [0:PORTNUM]; //data num(vectors) in each switch cell`
96			`// Cell Control Lines`
97			`reg [PORTNUM-1:0] wr_en [0:PORTNUM-1];`
98			`reg [PORTNUM-1:0] rd_en [0:PORTNUM-1];`
99	6	btltz	`wire [PORTNUM-1:0] clrCell[0:PORTNUM-1];`
100			`wire [PORTNUM-1:0] CellEmpty [0:PORTNUM-1];`
101			`wire [PORTNUM-1:0] CellFull [0:PORTNUM-1];`
102			`wire [PORTNUM-1:0] CellAfull [0:PORTNUM-1]; // buffer cell almost full`
103			`wire [PORTNUM-1:0] CellAempty [0:PORTNUM-1]; // buffer cell almost empty`
104	2	btltz
105	6	btltz	`wire [PORTNUM-1:0] CellHasData [0:PORTNUM-1] = ~CellEmpty; //? is the syntax right ?`
106			`wire [PORTNUM-1:0] CellHasSpc [0:PORTNUM-1] = ~CellFull;`
107	2	btltz
108
109			`// signal for Matrix Output management`
110			`reg [PORTNUM-1:0] columnHasData;`
111			`wire [PORTNUM-1:0] ColumnOE = columnHasData;`
112			`assign PHasData_o = columnHasData; //Port Has Data.Synchronous output to write Tx FIFO`
113
114			`// reg [WIDTH_CRD-1:0] crdcnt [0:PORTNUM-1];//credit counter`
115			`// assign crd_o = crdcnt;`
116
117			`/////////////////////////////////////`
118			`// Config input/output address REGs`
119			`//`
120			`always @(posedge gclk)`
121			`begin`
122			`integer i=0;`
123			`if(reset)`
124			`begin`
125			`SelColumn <= 0;`
126			`SelLine <= 0;`
127			`end`
128			`else begin`
129			`for (i=0; i<PORTNUM; i=i+1 )`
130			`begin`
131			`if( ld_SelColumn[i] == True ) // ld_SelColumn = sop_req_i; Note taht the addr must be valid.`
132			`SelColumn[i] <= out_addr_i[i]; // Address Vector load`
133			`if( ld_SelColine[i] == True ) // if the scheduler load output address.`
134			`SelColine[i] <= ScheOut [i]; // Address Vector load`
135			`end`
136			`end`
137			`end`
138
139			`///////////////////////`
140			`// Matrix Cell buffers`
141			`//`
142			`// note: should select devices that have true dual port RAM`
143
144			`generate`
145			`begin:GEN_Cell`
146			`genvar i,k;`
147			`for (i=0; i<PORTNUM; i=i+1) // i : each column`
148			`begin`
149			`for (k=0; k<PORTNUM; k=k+1) // k : in a column(sel line)`
150			`begin`
151			`eth_fifo #(parameter DATA_WIDTH=BW, DEPTH=CellDepth) // byte width=9, depth=? undetermined`
152			`Cell_Fifo_Array`
153			`(.data_in ( di[k] ), // different colum has same data input line`
154			`.data_out( CellOut[i][k] ),// k assign to 1 column,i assign to n columns.L<-R`
155			`.write ( wr_en[i][k] ),`
156			`.read ( rd_en[i][k] ),`
157			`.clear ( clrCell[i][k] ),`
158			`.almost_full ( CellAfull[i][k] ),`
159			`.full ( CellFull[i][k] ),`
160			`.almost_empty( CellAempty[i][k] ),`
161			`.empty ( CellEmpty[i][k] ),`
162			`.gclk ( gclk ),`
163			`.reset( reset ),`
164			`.cnt( CellCnt[i][k] ) //may be usable`
165			`);`
166			`end //end 1 column (16x1 )`
167			`end //end 1 array (16x16)`
168			`end //end GEN_Cell`
169
170
171
172			`/////////////////////////////////////////`
173			`// Distribute lines data`
174			`// to the Matrix Cell`
175			`reg [PORTNUM-1:0] wpen ; // Write Packages Enable`
176
177			`//register sop_req_i or eop_i pulse`
178			`always @(posedge gclk)`
179			`begin`
180			`integer k;`
181			if(reset==`reset)
182			`wpen <= 0;`
183			`else begin`
184			`for(k=0; k<PORTNUM; k=k+1)`
185			`begin`
186			`if(eop_i[k])`
187			`wpen[k] <= 1'b0;`
188			`else if(sop_req_i[k])`
189			`wpen[k] <= 1'b1;`
190			`end`
191			`end`
192			`end`
193
194			`reg [PORTNUM-1:0] wr__; // level signal`
195
196			`always @(*)`
197			`begin`
198			`for (k =0; k <PORTNUM; k =k+1)`
199			`wr__[k] = ( wpen[k] ==False \|\| eop_i[k]) ? 0 :`
200			`( ( wpen[k] ==True && eop_i[k] ==False ) ? 1'b1 : 'bx );`
201			`end`
202
203			`//decode config addr according to the external controller`
204			`//(and the package addr head). Generate cell "we" signals array.`
205			`always @(*)`
206			`begin`
207			`integer i,k;`
208			`for (i=0; i<PORTNUM; i=i+1) // i : each column`
209			`begin`
210			`for (k=0; k<PORTNUM; k=k+1) // k : lines in a column(sel line)`
211			`begin`
212			`wr_en[i][k] = ( wr__[i] // write to x column`
213			`&& SelColine[i] ==k // select a line in a column`
214			`&& CellHasSpc[i][k] ==True // that cell is not full`
215			`)`
216			`? 1'b1 : 1'b0;`
217			`sop_ack_o[i] = (SelColine[i] ==k // "select a line" must has been configed`
218			`&& CellHasSpc[i][k] ==True // that cell is not full`
219			`)`
220			`? 1'b1 : 1'b0;`
221			`end`
222			`end`
223			`end`
224
225
226			`/////////////////////////`
227			`// Read enable to Tx Fifo`
228			`//`
229			`////////////////////`
230			`// Credit collecting credit information to The Input Line`
231			`// Output Schedulers are responsible for selecting eligible`
232
233			`always @ (*)`
234			`begin`
235			`integer m;`
236			`for(m=0; m<PORTNUM; m=m+1)`
237			`columnHasData[m] = \| celHasData[m];`
238			`// cellHasData[m][0] \|\| cellHasData[m][1] \|\| ...\|\| cellHasData[m][15]`
239			`end`
240
241	6	btltz
242	2	btltz	`//////////////////////////////`
243	6	btltz	`// 16 outputs Column Schedulers`
244	2	btltz	`//`
245			`//////////////////////////////`
246			`// 1 scheduler is responsible to 32 cell in a column`
247
248			`generate`
249	6	btltz	`begin:GEN_CSers`
250			`genvar i, k;`
251	2	btltz	`for (i=0; i<PORTNUM; i=i+1) // i : each column`
252	6	btltz	`begin:inst_column`
253	2	btltz	`for (k=0; k<PORTNUM; k=k+1) // k : in a column(sel line)`
254	6	btltz	`begin:inst_line`
255			`CSer inst_CSer`
256	2	btltz	`( .ld_SelCoLine_o( ld_SelColine ),`
257			`.empty_i(CellEmpty[i][k] ), // one-hot input`
258			`.Aempty_i(CellAfull[i][k]), // one-hot`
259			`.addr_o( ScheOut[i] ),`
260			`.reset(reset)`
261			`.gclk(gclk)`
262			`);`
263			`end // end lines in a column`
264			`end // end columns`
265			`end`
266			`endgenerate`
267
268			`////////////////////////////`
269			`// 16 outputs`
270			`//`
271			`always @(*)`
272			`begin`
273			`integer n;`
274			`for (n=0; n<PORTNUM; n=n+1)`
275			`begin`
276			`if(columOE)`
277			`do[n] = CellOut[SelLine][n]; // n : (port0 -> port15)`
278			`else`
279			`do[n] = 'b0; // 10'b p0_0000_0000`
280			`end // EOP = 10'b p1_0000_0000`
281			`end`
282
283
284			`/*///////////////`
285			`// Functions`
286			`//`
287			`function [15:0] greyiDEC4_16; //Grey code input decoder`
288			`input [3:0] in;`
289			`begin`
290			`case (in)`
291			`4'b0000 : greyiDEC4_16 = 16'h1;`
292			`4'b0001 : greyiDEC4_16 = 16'h2;`
293			`4'b0011 : greyiDEC4_16 = 16'h4;`
294			`4'b0010 : greyiDEC4_16 = 16'h8;`
295			`4'b0110 : greyiDEC4_16 = 16'h10;`
296			`4'b0111 : greyiDEC4_16 = 16'h20;`
297			`4'b0101 : greyiDEC4_16 = 16'h40;`
298			`4'b0100 : greyiDEC4_16 = 16'h80;`
299			`4'b1100 : greyiDEC4_16 = 16'h100;`
300			`4'b1101 : greyiDEC4_16 = 16'h200;`
301			`4'b1111 : greyiDEC4_16 = 16'h400;`
302			`4'b1110 : greyiDEC4_16 = 16'h800;`
303			`4'b1010 : greyiDEC4_16 = 16'h1000;`
304			`4'b1011 : greyiDEC4_16 = 16'h2000;`
305			`4'b1001 : greyiDEC4_16 = 16'h4000;`
306			`4'b1000 : greyiDEC4_16 = 16'h8000;`
307			`default : greyiDEC4_16 = 'bx;`
308			`endcase`
309			`end`
310			`endfunction */`
311
312			`endmodule`
313
314			`undef reset
315	6	btltz	`undef TOOL_NOTSUP_PORT_ARRAY

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