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//File name=Module name=WB_COMI_HOCI   2005-3-18      btltz@mail.china.com      btltz from CASIC,China  
//Description:   SpaceWire WISHBONE interface for communication mem(COMI) and Host controller(HOCI)  
//Spec       :   Use Little Endian internal
//Abbreviations: WB     --- WISHBONE (SoC interconnection architecture)
//               COMI   --- COmmunication Memory Interface
//               HOCI   --- HOst Control Interface 
//Origin:        WISHBONE Specification Revision B.3; SpaceWire Std - Draft-1 of ESTEC,ESA
//--     TODO:
////////////////////////////////////////////////////////////////////////////////////
//
/*synthesis translate_off*/
`include "timescale.v"
/*synthesis translate_on */
`define reset    1        // WISHBONE Style reset 
 
module WB_COMI_HOCI #(parameter CM_AW=16,CM_DW=32,
                                H_DW=32,H_AW=5,    // width==3 to select max 16 registers(include 2*3 transceiver FIFO) 
                                IOBUF_DW=9)
                 (
// COMI interface(WISHBONE MASTER interface) to a "communication memory",a dpRAM                     
                                     output [CM_AW-1:0] CM_ADR_o,
                                     output [CM_DW-1:0] CM_DAT_o, //because some FPGA and ASIC devices do not support bi-directional signals so have not use "inout" 
                                     output [3:0] CM_SEL_o,
                                     output CM_WE_o,
                                                 //output CM_STB0_o,
                                     //output CM_STB1_o, 
                                     output CM_STB_o,
                                                 input [CM_DW-1:0]  CM_DAT_i,
                                                 input CM_ACK_i,
                                  // Pins to Support sharing a communication memory between 2 SpW interfaces. 
                                     output COC_o,
                                     input COC_i,
                                     // note that memory circuit does not have a reset input.   
 
// HOCI interface(WISHBONE SLAVE interface) to host such as a uP 
                                  output [H_DW-1:0] H_DAT_o,
                            output [3:0] TGD_o,                         // data tag type output
                                     output reg H_ACK_o,
                                     output reg H_ERR_o,
                                     output reg H_RTY_o,
                                     input  [H_AW-1:0] H_ADR_i,
                                     input  [H_DW-1:0] H_DAT_i,
                                     input  [3:0] H_TGD_i,                 // data tag type input
                                     input  [3:0] H_SEL_i,
                                                 input  H_WE_i,
                                     input  H_CYC_i,
                                                 input  H_STB_i,
 
                                                 output reg H_INT_o,                     // TAG. interrupt request line
 
// interface to 3 channels( CODEC + Glue Logic ) 
                               output     wr_tx1buf_o,
                                             output [IOBUF_DW-1:0] tx1buf_data_o,
                                             input  tx1buf_full_i,
                               output     wr_tx2buf_o,
                                             output [IOBUF_DW-1:0] tx2buf_data_o,
                                             input  tx2buf_full_i,
                               output     wr_tx3buf_o,
                                             output [IOBUF_DW-1:0] tx3buf_data_o,
                                             input  tx3buf_full_i,
 
                                         output    rd_rx1buf_o,
                                             input [IOBUF_DW-1:0] rx1buf_data_i,
                                             input rx1buf_empty_i,
                                   input rx1buf_Afull_i,
                               output    rd_rx2buf_o,
                                             input [IOBUF_DW-1:0] rx2buf_data_i,
                                             input rx2buf_empty_i,
                                   input rx2buf_Afull_i,
                               output    rd_rx3buf_o,
                                             input [IOBUF_DW-1:0] rx3buf_data_i,
                                             input rx3buf_empty_i,
                                   input rx3buf_Afull_i,
// global input signals
                   input RST_i, CLK_i
                                                 );
 
                             parameter DFLT_LOC_LOC = 16'h10;
                             parameter DFLT_SPE = 40;
                             parameter DFLT_CTR_TX = ;
                             parameter DFLT_CTR_RX = ;
                             parameter DFLT_WB_CTR = ;
                             parameter DFLT_COMI_ACR = ;
                             parameter DFLT_PKT_SIZE = 8;
                             parameter DFLT_COMI_CH_SEL = 0;
 
                             parameter ADDR_LOC_LOC   = 4'h00;
                             parameter ADDR_SPE1      = 4'h01;
                             parameter ADDR_CTR_STA1  = 4'h02;
                             parameter ADDR_SPE2      = 4'h03;
                             parameter ADDR_CTR_STA2  = 4'h04;
                             parameter ADDR_SPE3      = 4'h05;
                             parameter ADDR_CTR_STA3  = 4'h06;
                             parameter ADDR_WB_CTR    = 4'h07;
                             parameter ADDR_CH1T_FIFO = 4'h0A;
                             parameter ADDR_CH1R_FIFO = 4'h0B;
                             parameter ADDR_CH2T_FIFO = 4'h0C;
                             parameter ADDR_CH2R_FIFO = 4'h0D;
                             parameter ADDR_CH3T_FIFO = 4'h0E;
                             parameter ADDR_CH3R_FIFO = 4'h0F;
                             paremeter ADDR_CH1TXSE   = 4'h11;
                             parameter ADDR_CH1RXSE   = 4'h12;
                             parameter ADDR_CH2TXSE   = 4'h13;
                             parameter ADDR_CH2RXSE   = 4'h14;
                             parameter ADDR_CH3TXSE   = 4'h15;
                             parameter ADDR_CH3RXSE   = 4'h16;
                        parameter EOP = 9'b1_0000_0000;
                        parameter EEP = 9'b1_0000_0001;
parameter True = 1;
parameter False = 0;
 
 
////////////////////
// registers  
//
 
`inculde  "RegSpW.v"
 
wire COMI_DIS = (COMI_ACR ==0);                     // disable COMI interface
 
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// WISHBONE memory interface form "COMI"( COmmunication Memory Interface ).
// The mem may be a dpMEM which could be considered as "FASM":FPGA and ASIC Subset Model(asynchronous read).
//
reg [CM_AW-1:0] Agen_rx;                     // COMI receiver address generator
reg [CM_AW-1:0] Agen_tx;                     // COMI transmitter address generator  
wire CM_wr_txbuf1, CM_wr_txbuf2, CM_wr_txbuf3;
wire CM_rd_rxbuf1, CM_rd_rxbuf2, CM_rd_rxbuf3;
 
/////// COMI autonomous accesses to the communication memory or read data to be transmitted //////////////
reg [1:0] gracnt_DI ;                           // granularity = 8  for WISHBONE 'DAT_I'
reg ov_gra_DI;
reg CM_STB_RD;
 
 
always @(posedge CLK_i)
if(CM_AB2TX_GO ==True)
  gracnt <= 0;
else if(CM_STB_RD ==True)
  begin
    gracnt_DI <= gracnt_DI + 1;
    if(gracnt_DI==3)
       ov_gra_DI <= 1;
    else
       ov_gra_DI <= 0;
  end
 
// read data to be transmitted 
always @(posedge CLK_i)
if(reset)
  CM_STB_RD <= 0;
else if( |CM_AB2TX_GO == 1)
  begin
  CM_AB2TX_GO <= 0;                          // clear first
  CM_RD_itl <= 1'b1;
  end
else if( (   COMI_CH_SEL ==1 && Agen_tx ==CH1_TX_EAR
          || COMI_CH_SEL ==2 && Agen_tx ==CH2_TX_EAR
          || COMI_CH_SEL ==3 && Agen_tx ==Ch3_TX_EAR
         )  && CM_SEL_o[3] ==1'b1
       )
  CM_RD_itl <= 0;
always @(posedge CLK_i)
if(reset)
  CM_STB_RD <= 0;
else if (  (   |CM_AB2TX_GO ==1    ||   CM_RD_itl ==1     )  &&
           (  COMI_CH_SEL ==1 && tx1buf_full_i ==False
             || COMI_CH_SEL ==2 && tx2buf_full_i ==False
             || COMI_CH_SEL ==3 && tx3buf_full_i ==False  )
        )
     CM_STB_RD <= 1;
else
     CM_STB_RD <= 0;
 
 
        // Agen_tx
always @(posedge CLK_i)
if( |CM_AB2TX_GO == 1)   // load 'Agen_tx'
  begin
    case(COMI_CH_SEL)    // synthesis parallel_case full_case
      2'b01    :     Agen_tx <= CH1_TX_SAR;
      2'b10    :     Agen_tx <= CH2_TX_SAR;
      2'b11    :     Agen_tx <= CH3_TX_SAR;
      default  :     Agen_tx <= 'bx;
    endcase
  end
else if(   CM_STB_RD ==True                       // 1 clk latency after 'CM_AB2TX_GO'
        && ov_gra_DI )
     Agen_tx <= Agen_tx + 1;
 
assign CM_ADDR_o = Agen_tx;                       // address output
assign CM_SEL_o = ( CM_STB_o ==1'b1 )  ?
                                       ( gracnt_DI ==0   ?   4'b0001  :
                                           ( gracnt_DI ==1   ?   4'b0010  :
                                           ( gracnt_DI ==2   ?   4'b0100  :
                                           ( gracnt_DI ==3   ?   4'b1000  :   4'hx )))
                                        )
                                       : 4'b'b0;         // note i assume that the synthesis tool support to translate it to be parallel. Most tools do this now. 
 
assign CM_wr_txbuf1 = ( COMI_CH_SEL ==1 && CM_STB_RD )  ?  1'b1  :  1'b0;
assign CM_wr_txbuf2 = ( COMI_CH_SEL ==2 && CM_STB_RD )  ?  1'b1  :  1'b0;
assign CM_wr_txbuf3 = ( COMI_CH_SEL ==3 && CM_STB_RD )  ?  1'b1  :  1'b0;
 
 
// write to the communication memory from RX FIFO
reg [1:0] gracnt_DO;                          // granularity = 8 for WISHBONE 'DAT_O'
reg ov_gra_DO,
reg CM_STB_WR;
reg CM_WE_itl;
 
always @(posedge CLK_i)
if(CM_RX2AB_GO ==True)
  gracnt_DO <= 0;
else if(CM_STB_WR ==True)
  begin
    gracnt_DO <= gracnt_DO + 1;
    if(gracnt_DO==3)
       ov_gra_DO <= 1;
    else
       ov_gra_DO <= 0;
  end
 
always @(posedge CLK_i)
if(reset)
  begin
  CM_WE_itl <= 0;
  CM_R <= 0;
  end
else if( |CM_AB2TX_GO == 1)
  begin
  CM_RX2AB_GO <= 0;                          // clear first
  CM_STB_WR <= 1;
 
  end
else if(  (    COMI_CH_SEL ==1 && Agen_rx ==CH1_RX_EAR
            || COMI_CH_SEL ==2 && Agen_rx ==CH2_RX_EAR
            || COMI_CH_SEL ==3 && Agen_rx ==Ch3_RX_EAR
          ) && CM_SEL_o[3] ==1'b1
         )
     begin
       CM_WE_itl <= 0;
  CM_STB_WR <= 0;
 
 
always @(posedge CLK_i)
if( |CM_RX2AB_GO == 1)   // load 'Agen_tx'
  begin
    case(COMI_CH_SEL)    // synthesis parallel_case full_case
      2'b01    :     Agen_rx <= CH1_RX_SAR;
      2'b10    :     Agen_rx <= CH2_RX_SAR;
      2'b11    :     Agen_rx <= CH3_RX_SAR;
      default  :     Agen_rx <= 'bx;
    endcase
  end
else if(   CM_STB_WR ==True                       // 1 clk latency after 'CM_AB2TX_GO'
        && ov_gra_DO )
     Agen_rx <= Agen_rx + 1;
 
assign CM_ADDR_o = Agen_tx;                       // address output
assign CM_SEL_o = ( CM_STB_o ==1'b1 )  ?
                                       ( gracnt_DI ==0   ?   4'b0001  :
                                           ( gracnt_DI ==1   ?   4'b0010  :
                                           ( gracnt_DI ==2   ?   4'b0100  :
                                           ( gracnt_DI ==3   ?   4'b1000  :   4'hx )))
                                        )
                                       : 4'b'b0;
 
 
 
 
 
 
 
assign CM_WE_o = CM_WE_itl;                  // default 'CM_WE_o' is 'read'(low level)
assign CM_DAT_o = ();
assign CM_STB_o = CM_STB_RD || CM_STB_WR;
 
function [31:0] SEL_RX2CM_SRC;                      // From Channel ? to COMI; COMI only access FIFOs.  
input [1:0] COMI_CH_SEL;
input [8:0] rxbuf1_data_i;
input [8:0] rxbuf2_data_i;
input [8:0] rxbuf3_data_i;
begin
 case(COMI_CH_SEL)  // synthesis parallel_case 
  2'b01  :    SEL_RX2CM_SRC[31:0]  =  { rxbuf1_data_i[7:0], rxbuf1_data_i[7:0], rxbuf1_data_i[7:0], rxbuf1_data_i[7:0] };
  2'b10  :    SEL_RX2CM_SRC[31:0]  =  { rxbuf2_data_i[7:0], rxbuf2_data_i[7:0], rxbuf2_data_i[7:0], rxbuf2_data_i[7:0] };
  2'b11  :    SEL_RX2CM_SRC[31:0]  =  { rxbuf3_data_i[7:0], rxbuf3_data_i[7:0], rxbuf3_data_i[7:0], rxbuf3_data_i[7:0] };
 default :    SEL_RX2CM_SRC[31:0]  =  32'hxxxx;
end
endfunction
////////////end channel sel/////////
 
 
 
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// WISHBONE Slave to form "HOCI"( HOst Control Interface ).
// The host may be a uP, FPGA, etc.
//
 
/*reg [31:0] H_SLV_LATCH;
 
// latch HOCI WISHBONE Slave DAT&TGD input
always @(posedge CLK_i)
if( H_CYC_i && H_WE_i && H_STB_i )
  begin
  case(H_SEL_i)    // synthesis parallel_case
  4'b0001    :    H_SLV_LATCH[7:0]   <= H_DAT_i[7:0];
  4'b0010    :    H_SLV_LATCH[15:8]  <= H_DAT_i[15:8];
  4'b0100    :    H_SLV_LATCH[23:16] <= H_DAT_i[23:16];
  4'b1000    :    H_SLV_LATCH[31:24] <= H_DAT_i[31:24];
   default   :    H_SLV_LATCH  <= 'bx;
  end
*/
 
reg H_wr_txbuf1, H_wr_txbuf2, H_wr_txbuf3;
reg H_rd_rxbuf1, H_rd_rxbuf2, H_rd_rxbuf3;
 
 
////////////////////// HOCI Write SpW registers /////////////////////////////////
always @(posedge CLK_i)
begin
  if(RST_i==`reset)
    begin
    LOC_LOC  <= DFLT_LOC_LOC;
    SPE_CTL1 <= DFLT_SPE ;
    SPE_CTL2 <= DFLT_SPE ;
    SPE_CTL3 <= DFLT_SPE ;
         CTL_TX1 <= DFLT_CTR_TX;
         CTL_RX1 <= DFLT_CTR_RX;
                 CTL_TX2 <= DFLT_CTR_TX;
                 CTL_RX2 <= DFLT_CTR_RX;
                         CTL_TX3 <= DFLT_CTR_TX;
                         CTL_RX3 <= DFLT_CTR_RX;
    WB_CTR <= DFLT_WB_CTR;
    COMI_ACR <= DFLT_COMI_ACR;
    COMI_CH_SEL <= DFLT_COMI_CH_SEL;
    end
 
  else if( H_CYC_i && H_WE_i && H_STB_i )     // Write
       begin
        case( {H_ADR_i,    H_SEL_i} )     // synthesis full_case   parallel_case  // here full_case directive to substitute long default assignment
            {ADDR_LOC_LOC, 4'b0001}    :     LOC_LOC <= H_DAT_i[ 7:0];
            {ADDR_LOC_LOC, 4'b0010}    :     LOC_LOC <= H_DAT_i[15:8];
            {ADDR_SPE1,    4'b0001}    :   SPE_CTL1[7:0] <= H_DAT_i[ 7:0];
            {ADDR_SPE1,    4'b0010}    :   SPE_CTL1[15:8] <= H_DAT_i[15:8];       // write to status register results no effect
            {ADDR_CTR_STA1,4'b0001}    :     CTL_RX1 <= H_DAT_i[ 7:0];
            {ADDR_CTR_STA1,4'b0010}    :     CTL_TX1 <= H_DAT_i[15:8];
            {ADDR_SPE2,    4'b0001}    :   SPE_CTL2[7:0] <= H_DAT_i[ 7:0];
            {ADDR_SPE2,    4'b0010}    :   SPE_CTL2[15:8] <= H_DAT_i[15:8];
            {ADDR_CTR_STA2,4'b0001}    :     CTL_RX2 <= H_DAT_i[ 7:0];
            {ADDR_CTR_STA2,4'b0010}    :     CTL_TX2 <= H_DAT_i[15:8];
            {ADDR_SPE3    ,4'b0001}    :   SPE_CTL3[7:0] <= H_DAT_i[ 7:0];
            {ADDR_SPE3    ,4'b0010}    :   SPE_CTL3[15:8] <= H_DAT_i[15:8];
            {ADDR_CTR_STA3,4'b0001}    :     CTL_RX3 <= H_DAT_i[ 7:0];
            {ADDR_CTR_STA3,4'b0010}    :     CTL_TX3 <= H_DAT_i[15:8];
            {ADDR_WB_CTR,  4'b0001}    :   begin
                                             COMI_CH_SEL <= H_DAT_i[ 7:6];
                                             CM_AB2TX_GO <= H_DAT_i[ 3:2];
                                             CM_RX2AB_GO <= H_DAT_i[ 1:0];
                                           end
            {ADDR_WB_CTR,  4'b0010}    :   PKT_SIZE <= H_DAT_i[15:14];
            {ADDR_WB_CTR,  4'b0100}    :   COMI_ACR <= H_DAT_i[23:20];
            {ADDR_WB_CTR,  4'b1000}    :   WB_CTR   <= H_DAT_i[31:30];
 
            /*writing FIFO is not performed here*/
 
            {ADDR_CH1TXSE, 4'b0001}    :   CH1_TX_SAR[ 7:0]  <= H_DAT_i[7:0];
            {ADDR_CH1TXSE, 4'b0010}    :   CH1_TX_SAR[15:8]  <= H_DAT_i[15:8];
            {ADDR_CH1TXSE, 4'b0100}    :   CH1_TX_SAR[23:16] <= H_DAT_i[23:16];
            {ADDR_CH1TXSE, 4'b1000}    :   CH1_TX_SAR[31:24] <= H_DAT_i[31:24];
            {ADDR_CH1RXSE, 4'b0001}    :   CH1_RX_SAR[ 7:0]  <= H_DAT_i[7:0];
            {ADDR_CH1RXSE, 4'b0010}    :   CH1_RX_SAR[15:8]  <= H_DAT_i[15:8];
            {ADDR_CH1RXSE, 4'b0100}    :   CH1_RX_SAR[23:16] <= H_DAT_i[23:16];
            {ADDR_CH1RXSE, 4'b1000}    :   CH1_RX_SAR[31:24] <= H_DAT_i[31:24];
 
            {ADDR_CH2TXSE, 4'b0001}    :   CH2_TX_SAR[ 7:0]  <= H_DAT_i[7:0];
            {ADDR_CH2TXSE, 4'b0010}    :   CH2_TX_SAR[15:8]  <= H_DAT_i[15:8];
            {ADDR_CH2TXSE, 4'b0100}    :   CH2_TX_SAR[23:16] <= H_DAT_i[23:16];
            {ADDR_CH2TXSE, 4'b1000}    :   CH2_TX_SAR[31:24] <= H_DAT_i[31:24];
            {ADDR_CH2RXSE, 4'b0001}    :   CH2_RX_SAR[ 7:0]  <= H_DAT_i[7:0];
            {ADDR_CH2RXSE, 4'b0010}    :   CH2_RX_SAR[15:8]  <= H_DAT_i[15:8];
            {ADDR_CH2RXSE, 4'b0100}    :   CH2_RX_SAR[23:16] <= H_DAT_i[23:16];
            {ADDR_CH2RXSE, 4'b1000}    :   CH2_RX_SAR[31:24] <= H_DAT_i[31:24];
 
            {ADDR_CH3TXSE, 4'b0001}    :   CH3_TX_SAR[ 7:0]  <= H_DAT_i[7:0];
            {ADDR_CH3TXSE, 4'b0010}    :   CH3_TX_SAR[15:8]  <= H_DAT_i[15:8];
            {ADDR_CH3TXSE, 4'b0100}    :   CH3_TX_SAR[23:16] <= H_DAT_i[23:16];
            {ADDR_CH3TXSE, 4'b1000}    :   CH3_TX_SAR[31:24] <= H_DAT_i[31:24];
            {ADDR_CH3RXSE, 4'b0001}    :   CH3_RX_SAR[ 7:0]  <= H_DAT_i[7:0];
            {ADDR_CH3RXSE, 4'b0010}    :   CH3_RX_SAR[15:8]  <= H_DAT_i[15:8];
            {ADDR_CH3RXSE, 4'b0100}    :   CH3_RX_SAR[23:16] <= H_DAT_i[23:16];
            {ADDR_CH3RXSE, 4'b1000}    :   CH3_RX_SAR[31:24] <= H_DAT_i[31:24];
 
            default:  $display("Warning : missing write objective. h%, h%", H_ADR_i, H_SEL_i);
 
        endcase
       end
end // end always @...
 
/////////////////////////// HOCI read registers////////////////////////////////////
 
// Read SpW registers - include FIFOs of RX/TX
 
always @(*)
if( H_CYC_i && !H_WE_i && H_STB_i )    // Read
       begin
          case (H_ADR_i)   // synthesis parallel_case
            ADDR_SPE1      :    H_DAT_o =  SPE_CTL1;
            ADDR_CTR_STA1  :    H_DAT_o =  { STA_TX1, STA_RX1, CTL_TX1, CTL_RX1 };
            ADDR_SPE2      :    H_DAT_o =  SPE_CTL2;
            ADDR_CTR_STA2  :    H_DAT_o =  { STA_TX2, STA_RX2, CTL_TX2, CTL_RX2 };
            ADDR_SPE3      :    H_DAT_o =  SPE_CTL3;
            ADDR_CTR_STA3  :    H_DAT_o =  { STA_TX3, STA_RX3, CTL_TX3, CTL_RX3 };
            ADDR_WB_CTR    :    H_DAT_o =  { WB_CTR, COMI_ACR, PKT_SIZE, COMI_CH_SEL };
            ADDR_CH1R_FIFO :    H_DAT_o =  { rxbuf1_data_i[7:0], rxbuf1_data_i[7:0], rxbuf1_data_i[7:0], rxbuf1_data_i[7:0] };
            ADDR_CH2R_FIFO :    H_DAT_o =  { rxbuf2_data_i[7:0], rxbuf2_data_i[7:0], rxbuf2_data_i[7:0], rxbuf2_data_i[7:0] };
            ADDR_CH3R_FIFO :    H_DAT_o =  { rxbuf3_data_i[7:0], rxbuf3_data_i[7:0], rxbuF3_data_i[7:0], rxbuf3_data_i[7:0] };
            ADDR_CH1TXSE   :    H_DAT_o =  { CH1_TX_SAR, CH1_TX_EAR };
            ADDR_CH1RXSE   :    H_DAT_o =  { CH1_RX_SAR, CH1_RX_EAR };
            ADDR_CH2TXSE   :    H_DAT_o =  { CH2_TX_SAR, CH2_TX_EAR };
            ADDR_CH2RXSE   :    H_DAT_o =  { CH2_RX_SAR, CH2_RX_EAR };
            ADDR_CH3TXSE   :    H_DAT_o =  { CH3_TX_SAR, CH3_TX_EAR };
            ADDR_CH3RXSE   :    H_DAT_o =  { CH3_RX_SAR, CH3_RX_EAR };
          default          :    H_DAT_o =  32'hxxxx;
          endcase
       end
 
 
 
 
                             ///////////////////////////
                             // LET'S TALK ABOUT FIFO //
                             ///////////////////////////
/////////////////////// "H_ACK_o" and Write/read TX/RX FIFO /////////////////////
always @(*)
begin
 
H_ACK_o = 1'b0;                                              // set default value
H_RTY_o = 1'b0;
 
if( H_CYC_i && H_WE_i && H_STB_i )                        // if write                 
begin
  {H_wr_tx1buf, H_wr_tx2buf, H_wr_tx3buf} = 0;            // set default value
  H_ACK_o = 1;                                            // write to regs exclude FIFO is always permitted
     case(H_ADR_i)       // synthesis parallel_case
        ADDR_CH1T_FIFO : begin
                           if(tx1buf_full_i ==False)
                             H_wr_tx1buf = 1'b1;
                           if(tx1buf_full_i ==True)
                             begin
                             H_ACK_o = 1'b0;
                             H_RTY_o = 1'b1;
                             end
                         end
        ADDR_CH2T_FIFO : begin
                           if(tx32buf_full_i ==False)
                             H_wr_tx2buf = 1'b1;
                           if(tx2buf_full_i ==True)
                             begin
                             H_ACK_o = 1'b0;
                             H_RTY_o = 1'b1;
                             end
                         end
 
        ADDR_CH3T_FIFO : begin
                           if(tx3buf_full_i ==False)
                             H_wr_tx3buf = 1'b1;
                           if(tx3buf_full_i ==True)
                             begin
                             H_ACK_o = 1'b0;
                             H_RTY_o = 1'b1;
                             end
                         end
        default:         begin
                            {H_rd_rx1buf, H_rd_rx2buf, H_rd_rx3buf} = 3'bx;
                            H_ACK_o = 1'bx;
                         end
        endcase
end
else if( H_CYC_i && !H_WE_i && H_STB_i )                  // if read 
begin
  {H_rd_rx1buf, H_rd_rx2buf, H_rd_rx3buf} = 0;            // set default value
  H_ACK_o = 1;                                            // read to regs exclude FIFO is always permitted
  case(H_ADR_i)          // synthesis parallel_case
 
        ADDR_CH1R_FIFO : begin
                           if(rx1buf_empty_i ==False)
                             H_rd_rx1buf = 1'b1;
                           if( rx1buf_empty_i ==True
                              && rxbuf1_data_i[8] == 1'b1 )// if EOP/EEP, continue read but discard value read
                             begin
                             H_ACK_o = 1'b0;
                             H_RTY_o = 1'b1;
                             end
                         end
        ADDR_CH2R_FIFO : begin
                           if(rx2buf_empty_i ==False)
                             H_rd_rx2buf = 1'b1;
                           if(rx2buf_empty_i ==True)
                             && rxbuf2_data_i[8] == 1'b1 )// if EOP/EEP, continue read but discard value read
                             begin
                             H_ACK_o = 1'b0;
                             H_RTY_o = 1'b1;
                             end
                         end
        ADDR_CH3R_FIFO : begin
                           if(rx3buf_empty_i ==False)
                             H_rd_rx3buf = 1'b1;
                           if(rx3buf_empty_i ==True)
                             && rxbuf3_data_i[8] == 1'b1 )// if EOP/EEP, continue read but discard value read
                             begin
                             H_ACK_o = 1'b0;
                             H_RTY_o = 1'b1;
                             end
                         end
  defult :               begin
                           {H_rd_rx1buf, H_rd_rx2buf, H_rd_rx3buf} = 3'bx;
                            H_ACK_o = 1'bx;
                         end
  endcase
end
 
end   // end always @...
 
 
assign txbuf1_data_o = ADD_CH1_EOP  ?  EOP  :   SEL_TXDAT_SRC(COMI_DIS,
                                                           H_DAT_i,
                                                           H_SEL_i,
                                                           CM_DAT_i,
                                                           CM_SEL_o );
assign txbuf2_data_o = ADD_CH2_EOP  ?  EOP  :   SEL_TXDAT_SRC(COMI_DIS,
                                                           H_DAT_i,
                                                           H_SEL_i,
                                                           CM_DAT_i,
                                                           CM_SEL_o );
assign txbuf3_data_o = ADD_Ch3_EOP  ?  EOP  :   SEL_TXDAT_SRC(COMI_DIS,
                                                           H_DAT_i,
                                                           H_SEL_i,
                                                           CM_DAT_i,
                                                           CM_SEL_o );
 
function [7:0] SEL_TXDAT_SRC;                      // COMI or HOCI to TX FIFO
input COMI_DIS;
input [31:0] H_DAT_i;
input [3:0] H_SEL_i;
input [31:0] CM_DAT_i;
input [3:0] CM_SEL_o;
begin
  if (COMI_DIS ==True)
    SEL_TXDAT_SRC = SEL_H2TX_SRC(H_SEL_i, H_DAT_i);
  else if (COMI_DIS ==FALSE)
    SEL_TXDAT_SRC = SEL_CM2TX_SRC(CM_SEL_o, CM_DAT_i);
end
endfunction
 
 
///////// byte sel //////////
function [7:0]  SEL_H2TX_SRC;                       // Which byte from HOCI to TX FIFO;
input [3:0] H_SEL_i;
input [31:0] H_DAT_i;
 begin
    case (H_SEL_i)   // synthesis parallel_case
    4'b0001   :    SEL_TXDAT_SRC = H_DAT_i[ 7: 0];
    4'b0010   :    SEL_TXDAT_SRC = H_DAT_i[15: 8];
    4'b0100   :    SEL_TXDAT_SRC = H_DAT_i[23:16];
    4'b1000   :    SEL_TXDAT_SRC = H_DAT_i[31:24];
    default   :    SEL_TXDAT_SRC = 8'hxx;
    endcase
 end
endfunction
 
function [7:0] SEL_CM2TX_SRC;                      // Which byte from COMI to TX FIFO; COMI only access FIFOs. 
input [3:0] CM_SEL_o;
input [31:0] CM_DAT_i;
 begin
      case (CM_SEL_o) // synthesis parallel_case
      4'b0001 :    SEL_CM2TX_SRC = CM_DAT_i[ 7: 0];
      4'b0010 :    SEL_CM2TX_SRC = CM_DAT_i[15: 8];
      4'b0100 :    SEL_CM2TX_SRC = CM_DAT_i[23:16];
      4'b1000 :    SEL_CM2TX_SRC = CM_DAT_i[31:24];
      default :    SEL_CM2TX_SRC = 8'hxx;
      endcase
 end
////////end byte sel//////////
////////////////////////////// End Write/read FIFOs of RX/TX ///////////////////////////////
 
 
 
endmodule

Line No.	Rev	Author	Line
1	24	btltz	`//File name=Module name=WB_COMI_HOCI 2005-3-18 btltz@mail.china.com btltz from CASIC,China`
2			`//Description: SpaceWire WISHBONE interface for communication mem(COMI) and Host controller(HOCI)`
3			`//Spec : Use Little Endian internal`
4			`//Abbreviations: WB --- WISHBONE (SoC interconnection architecture)`
5			`// COMI --- COmmunication Memory Interface`
6			`// HOCI --- HOst Control Interface`
7			`//Origin: WISHBONE Specification Revision B.3; SpaceWire Std - Draft-1 of ESTEC,ESA`
8	2	btltz	`//-- TODO:`
9			`////////////////////////////////////////////////////////////////////////////////////`
10			`//`
11	24	btltz	`/synthesis translate_off/`
12			`include "timescale.v"
13			`/synthesis translate_on /`
14			`define reset 1 // WISHBONE Style reset
15	2	btltz
16	24	btltz	`module WB_COMI_HOCI #(parameter CM_AW=16,CM_DW=32,`
17			`H_DW=32,H_AW=5, // width==3 to select max 16 registers(include 2*3 transceiver FIFO)`
18			`IOBUF_DW=9)`
19			`(`
20			`// COMI interface(WISHBONE MASTER interface) to a "communication memory",a dpRAM`
21			`output [CM_AW-1:0] CM_ADR_o,`
22			`output [CM_DW-1:0] CM_DAT_o, //because some FPGA and ASIC devices do not support bi-directional signals so have not use "inout"`
23			`output [3:0] CM_SEL_o,`
24			`output CM_WE_o,`
25			`//output CM_STB0_o,`
26			`//output CM_STB1_o,`
27			`output CM_STB_o,`
28			`input [CM_DW-1:0] CM_DAT_i,`
29			`input CM_ACK_i,`
30			`// Pins to Support sharing a communication memory between 2 SpW interfaces.`
31			`output COC_o,`
32			`input COC_i,`
33			`// note that memory circuit does not have a reset input.`
34	2	btltz
35	24	btltz	`// HOCI interface(WISHBONE SLAVE interface) to host such as a uP`
36			`output [H_DW-1:0] H_DAT_o,`
37			`output [3:0] TGD_o, // data tag type output`
38			`output reg H_ACK_o,`
39			`output reg H_ERR_o,`
40			`output reg H_RTY_o,`
41			`input [H_AW-1:0] H_ADR_i,`
42			`input [H_DW-1:0] H_DAT_i,`
43			`input [3:0] H_TGD_i, // data tag type input`
44			`input [3:0] H_SEL_i,`
45			`input H_WE_i,`
46			`input H_CYC_i,`
47			`input H_STB_i,`
48	2	btltz
49	24	btltz	`output reg H_INT_o, // TAG. interrupt request line`
50
51	2	btltz	`// interface to 3 channels( CODEC + Glue Logic )`
52	24	btltz	`output wr_tx1buf_o,`
53			`output [IOBUF_DW-1:0] tx1buf_data_o,`
54			`input tx1buf_full_i,`
55			`output wr_tx2buf_o,`
56			`output [IOBUF_DW-1:0] tx2buf_data_o,`
57			`input tx2buf_full_i,`
58			`output wr_tx3buf_o,`
59			`output [IOBUF_DW-1:0] tx3buf_data_o,`
60			`input tx3buf_full_i,`
61	2	btltz
62	24	btltz	`output rd_rx1buf_o,`
63			`input [IOBUF_DW-1:0] rx1buf_data_i,`
64			`input rx1buf_empty_i,`
65			`input rx1buf_Afull_i,`
66			`output rd_rx2buf_o,`
67			`input [IOBUF_DW-1:0] rx2buf_data_i,`
68			`input rx2buf_empty_i,`
69			`input rx2buf_Afull_i,`
70			`output rd_rx3buf_o,`
71			`input [IOBUF_DW-1:0] rx3buf_data_i,`
72			`input rx3buf_empty_i,`
73			`input rx3buf_Afull_i,`
74	2	btltz	`// global input signals`
75			`input RST_i, CLK_i`
76			`);`
77	24	btltz
78			`parameter DFLT_LOC_LOC = 16'h10;`
79			`parameter DFLT_SPE = 40;`
80			`parameter DFLT_CTR_TX = ;`
81			`parameter DFLT_CTR_RX = ;`
82			`parameter DFLT_WB_CTR = ;`
83			`parameter DFLT_COMI_ACR = ;`
84			`parameter DFLT_PKT_SIZE = 8;`
85			`parameter DFLT_COMI_CH_SEL = 0;`
86	2	btltz
87	24	btltz	`parameter ADDR_LOC_LOC = 4'h00;`
88			`parameter ADDR_SPE1 = 4'h01;`
89			`parameter ADDR_CTR_STA1 = 4'h02;`
90			`parameter ADDR_SPE2 = 4'h03;`
91			`parameter ADDR_CTR_STA2 = 4'h04;`
92			`parameter ADDR_SPE3 = 4'h05;`
93			`parameter ADDR_CTR_STA3 = 4'h06;`
94			`parameter ADDR_WB_CTR = 4'h07;`
95			`parameter ADDR_CH1T_FIFO = 4'h0A;`
96			`parameter ADDR_CH1R_FIFO = 4'h0B;`
97			`parameter ADDR_CH2T_FIFO = 4'h0C;`
98			`parameter ADDR_CH2R_FIFO = 4'h0D;`
99			`parameter ADDR_CH3T_FIFO = 4'h0E;`
100			`parameter ADDR_CH3R_FIFO = 4'h0F;`
101			`paremeter ADDR_CH1TXSE = 4'h11;`
102			`parameter ADDR_CH1RXSE = 4'h12;`
103			`parameter ADDR_CH2TXSE = 4'h13;`
104			`parameter ADDR_CH2RXSE = 4'h14;`
105			`parameter ADDR_CH3TXSE = 4'h15;`
106			`parameter ADDR_CH3RXSE = 4'h16;`
107			`parameter EOP = 9'b1_0000_0000;`
108			`parameter EEP = 9'b1_0000_0001;`
109			`parameter True = 1;`
110			`parameter False = 0;`
111
112
113			`////////////////////`
114			`// registers`
115			`//`
116
117			`inculde "RegSpW.v"
118
119			`wire COMI_DIS = (COMI_ACR ==0); // disable COMI interface`
120
121	2	btltz	`///////////////////////////////////////////////////////////////////////////////////////////////////////////`
122	24	btltz	`// WISHBONE memory interface form "COMI"( COmmunication Memory Interface ).`
123			`// The mem may be a dpMEM which could be considered as "FASM":FPGA and ASIC Subset Model(asynchronous read).`
124	2	btltz	`//`
125	24	btltz	`reg [CM_AW-1:0] Agen_rx; // COMI receiver address generator`
126			`reg [CM_AW-1:0] Agen_tx; // COMI transmitter address generator`
127			`wire CM_wr_txbuf1, CM_wr_txbuf2, CM_wr_txbuf3;`
128			`wire CM_rd_rxbuf1, CM_rd_rxbuf2, CM_rd_rxbuf3;`
129	2	btltz
130	24	btltz	`/////// COMI autonomous accesses to the communication memory or read data to be transmitted //////////////`
131			`reg [1:0] gracnt_DI ; // granularity = 8 for WISHBONE 'DAT_I'`
132			`reg ov_gra_DI;`
133			`reg CM_STB_RD;`
134	2	btltz
135
136	24	btltz	`always @(posedge CLK_i)`
137			`if(CM_AB2TX_GO ==True)`
138			`gracnt <= 0;`
139			`else if(CM_STB_RD ==True)`
140			`begin`
141			`gracnt_DI <= gracnt_DI + 1;`
142			`if(gracnt_DI==3)`
143			`ov_gra_DI <= 1;`
144			`else`
145			`ov_gra_DI <= 0;`
146			`end`
147	2	btltz
148	24	btltz	`// read data to be transmitted`
149			`always @(posedge CLK_i)`
150			`if(reset)`
151			`CM_STB_RD <= 0;`
152			`else if( \|CM_AB2TX_GO == 1)`
153			`begin`
154			`CM_AB2TX_GO <= 0; // clear first`
155			`CM_RD_itl <= 1'b1;`
156			`end`
157			`else if( ( COMI_CH_SEL ==1 && Agen_tx ==CH1_TX_EAR`
158			`\|\| COMI_CH_SEL ==2 && Agen_tx ==CH2_TX_EAR`
159			`\|\| COMI_CH_SEL ==3 && Agen_tx ==Ch3_TX_EAR`
160			`) && CM_SEL_o[3] ==1'b1`
161			`)`
162			`CM_RD_itl <= 0;`
163			`always @(posedge CLK_i)`
164			`if(reset)`
165			`CM_STB_RD <= 0;`
166			`else if ( ( \|CM_AB2TX_GO ==1 \|\| CM_RD_itl ==1 ) &&`
167			`( COMI_CH_SEL ==1 && tx1buf_full_i ==False`
168			`\|\| COMI_CH_SEL ==2 && tx2buf_full_i ==False`
169			`\|\| COMI_CH_SEL ==3 && tx3buf_full_i ==False )`
170			`)`
171			`CM_STB_RD <= 1;`
172			`else`
173			`CM_STB_RD <= 0;`
174
175	2	btltz
176	24	btltz	`// Agen_tx`
177			`always @(posedge CLK_i)`
178			`if( \|CM_AB2TX_GO == 1) // load 'Agen_tx'`
179			`begin`
180			`case(COMI_CH_SEL) // synthesis parallel_case full_case`
181			`2'b01 : Agen_tx <= CH1_TX_SAR;`
182			`2'b10 : Agen_tx <= CH2_TX_SAR;`
183			`2'b11 : Agen_tx <= CH3_TX_SAR;`
184			`default : Agen_tx <= 'bx;`
185			`endcase`
186			`end`
187			`else if( CM_STB_RD ==True // 1 clk latency after 'CM_AB2TX_GO'`
188			`&& ov_gra_DI )`
189			`Agen_tx <= Agen_tx + 1;`
190	2	btltz
191	24	btltz	`assign CM_ADDR_o = Agen_tx; // address output`
192			`assign CM_SEL_o = ( CM_STB_o ==1'b1 ) ?`
193			`( gracnt_DI ==0 ? 4'b0001 :`
194			`( gracnt_DI ==1 ? 4'b0010 :`
195			`( gracnt_DI ==2 ? 4'b0100 :`
196			`( gracnt_DI ==3 ? 4'b1000 : 4'hx )))`
197			`)`
198			`: 4'b'b0; // note i assume that the synthesis tool support to translate it to be parallel. Most tools do this now.`
199
200			`assign CM_wr_txbuf1 = ( COMI_CH_SEL ==1 && CM_STB_RD ) ? 1'b1 : 1'b0;`
201			`assign CM_wr_txbuf2 = ( COMI_CH_SEL ==2 && CM_STB_RD ) ? 1'b1 : 1'b0;`
202			`assign CM_wr_txbuf3 = ( COMI_CH_SEL ==3 && CM_STB_RD ) ? 1'b1 : 1'b0;`
203
204
205			`// write to the communication memory from RX FIFO`
206			`reg [1:0] gracnt_DO; // granularity = 8 for WISHBONE 'DAT_O'`
207			`reg ov_gra_DO,`
208			`reg CM_STB_WR;`
209			`reg CM_WE_itl;`
210
211			`always @(posedge CLK_i)`
212			`if(CM_RX2AB_GO ==True)`
213			`gracnt_DO <= 0;`
214			`else if(CM_STB_WR ==True)`
215			`begin`
216			`gracnt_DO <= gracnt_DO + 1;`
217			`if(gracnt_DO==3)`
218			`ov_gra_DO <= 1;`
219			`else`
220			`ov_gra_DO <= 0;`
221			`end`
222
223			`always @(posedge CLK_i)`
224			`if(reset)`
225			`begin`
226			`CM_WE_itl <= 0;`
227			`CM_R <= 0;`
228			`end`
229			`else if( \|CM_AB2TX_GO == 1)`
230			`begin`
231			`CM_RX2AB_GO <= 0; // clear first`
232			`CM_STB_WR <= 1;`
233
234			`end`
235			`else if( ( COMI_CH_SEL ==1 && Agen_rx ==CH1_RX_EAR`
236			`\|\| COMI_CH_SEL ==2 && Agen_rx ==CH2_RX_EAR`
237			`\|\| COMI_CH_SEL ==3 && Agen_rx ==Ch3_RX_EAR`
238			`) && CM_SEL_o[3] ==1'b1`
239			`)`
240			`begin`
241			`CM_WE_itl <= 0;`
242			`CM_STB_WR <= 0;`
243
244
245			`always @(posedge CLK_i)`
246			`if( \|CM_RX2AB_GO == 1) // load 'Agen_tx'`
247			`begin`
248			`case(COMI_CH_SEL) // synthesis parallel_case full_case`
249			`2'b01 : Agen_rx <= CH1_RX_SAR;`
250			`2'b10 : Agen_rx <= CH2_RX_SAR;`
251			`2'b11 : Agen_rx <= CH3_RX_SAR;`
252			`default : Agen_rx <= 'bx;`
253			`endcase`
254			`end`
255			`else if( CM_STB_WR ==True // 1 clk latency after 'CM_AB2TX_GO'`
256			`&& ov_gra_DO )`
257			`Agen_rx <= Agen_rx + 1;`
258
259			`assign CM_ADDR_o = Agen_tx; // address output`
260			`assign CM_SEL_o = ( CM_STB_o ==1'b1 ) ?`
261			`( gracnt_DI ==0 ? 4'b0001 :`
262			`( gracnt_DI ==1 ? 4'b0010 :`
263			`( gracnt_DI ==2 ? 4'b0100 :`
264			`( gracnt_DI ==3 ? 4'b1000 : 4'hx )))`
265			`)`
266			`: 4'b'b0;`
267
268
269
270
271
272
273
274			`assign CM_WE_o = CM_WE_itl; // default 'CM_WE_o' is 'read'(low level)`
275			`assign CM_DAT_o = ();`
276			`assign CM_STB_o = CM_STB_RD \|\| CM_STB_WR;`
277
278			`function [31:0] SEL_RX2CM_SRC; // From Channel ? to COMI; COMI only access FIFOs.`
279			`input [1:0] COMI_CH_SEL;`
280			`input [8:0] rxbuf1_data_i;`
281			`input [8:0] rxbuf2_data_i;`
282			`input [8:0] rxbuf3_data_i;`
283			`begin`
284			`case(COMI_CH_SEL) // synthesis parallel_case`
285			`2'b01 : SEL_RX2CM_SRC[31:0] = { rxbuf1_data_i[7:0], rxbuf1_data_i[7:0], rxbuf1_data_i[7:0], rxbuf1_data_i[7:0] };`
286			`2'b10 : SEL_RX2CM_SRC[31:0] = { rxbuf2_data_i[7:0], rxbuf2_data_i[7:0], rxbuf2_data_i[7:0], rxbuf2_data_i[7:0] };`
287			`2'b11 : SEL_RX2CM_SRC[31:0] = { rxbuf3_data_i[7:0], rxbuf3_data_i[7:0], rxbuf3_data_i[7:0], rxbuf3_data_i[7:0] };`
288			`default : SEL_RX2CM_SRC[31:0] = 32'hxxxx;`
289			`end`
290			`endfunction`
291			`////////////end channel sel/////////`
292
293
294
295			`///////////////////////////////////////////////////////////////////////////////////////////////////////////`
296			`// WISHBONE Slave to form "HOCI"( HOst Control Interface ).`
297			`// The host may be a uP, FPGA, etc.`
298			`//`
299
300			`/*reg [31:0] H_SLV_LATCH;`
301
302			`// latch HOCI WISHBONE Slave DAT&TGD input`
303			`always @(posedge CLK_i)`
304			`if( H_CYC_i && H_WE_i && H_STB_i )`
305			`begin`
306			`case(H_SEL_i) // synthesis parallel_case`
307			`4'b0001 : H_SLV_LATCH[7:0] <= H_DAT_i[7:0];`
308			`4'b0010 : H_SLV_LATCH[15:8] <= H_DAT_i[15:8];`
309			`4'b0100 : H_SLV_LATCH[23:16] <= H_DAT_i[23:16];`
310			`4'b1000 : H_SLV_LATCH[31:24] <= H_DAT_i[31:24];`
311			`default : H_SLV_LATCH <= 'bx;`
312			`end`
313			`*/`
314
315			`reg H_wr_txbuf1, H_wr_txbuf2, H_wr_txbuf3;`
316			`reg H_rd_rxbuf1, H_rd_rxbuf2, H_rd_rxbuf3;`
317
318
319			`////////////////////// HOCI Write SpW registers /////////////////////////////////`
320			`always @(posedge CLK_i)`
321			`begin`
322			if(RST_i==`reset)
323			`begin`
324			`LOC_LOC <= DFLT_LOC_LOC;`
325			`SPE_CTL1 <= DFLT_SPE ;`
326			`SPE_CTL2 <= DFLT_SPE ;`
327			`SPE_CTL3 <= DFLT_SPE ;`
328			`CTL_TX1 <= DFLT_CTR_TX;`
329			`CTL_RX1 <= DFLT_CTR_RX;`
330			`CTL_TX2 <= DFLT_CTR_TX;`
331			`CTL_RX2 <= DFLT_CTR_RX;`
332			`CTL_TX3 <= DFLT_CTR_TX;`
333			`CTL_RX3 <= DFLT_CTR_RX;`
334			`WB_CTR <= DFLT_WB_CTR;`
335			`COMI_ACR <= DFLT_COMI_ACR;`
336			`COMI_CH_SEL <= DFLT_COMI_CH_SEL;`
337			`end`
338
339			`else if( H_CYC_i && H_WE_i && H_STB_i ) // Write`
340			`begin`
341			`case( {H_ADR_i, H_SEL_i} ) // synthesis full_case parallel_case // here full_case directive to substitute long default assignment`
342			`{ADDR_LOC_LOC, 4'b0001} : LOC_LOC <= H_DAT_i[ 7:0];`
343			`{ADDR_LOC_LOC, 4'b0010} : LOC_LOC <= H_DAT_i[15:8];`
344			`{ADDR_SPE1, 4'b0001} : SPE_CTL1[7:0] <= H_DAT_i[ 7:0];`
345			`{ADDR_SPE1, 4'b0010} : SPE_CTL1[15:8] <= H_DAT_i[15:8]; // write to status register results no effect`
346			`{ADDR_CTR_STA1,4'b0001} : CTL_RX1 <= H_DAT_i[ 7:0];`
347			`{ADDR_CTR_STA1,4'b0010} : CTL_TX1 <= H_DAT_i[15:8];`
348			`{ADDR_SPE2, 4'b0001} : SPE_CTL2[7:0] <= H_DAT_i[ 7:0];`
349			`{ADDR_SPE2, 4'b0010} : SPE_CTL2[15:8] <= H_DAT_i[15:8];`
350			`{ADDR_CTR_STA2,4'b0001} : CTL_RX2 <= H_DAT_i[ 7:0];`
351			`{ADDR_CTR_STA2,4'b0010} : CTL_TX2 <= H_DAT_i[15:8];`
352			`{ADDR_SPE3 ,4'b0001} : SPE_CTL3[7:0] <= H_DAT_i[ 7:0];`
353			`{ADDR_SPE3 ,4'b0010} : SPE_CTL3[15:8] <= H_DAT_i[15:8];`
354			`{ADDR_CTR_STA3,4'b0001} : CTL_RX3 <= H_DAT_i[ 7:0];`
355			`{ADDR_CTR_STA3,4'b0010} : CTL_TX3 <= H_DAT_i[15:8];`
356			`{ADDR_WB_CTR, 4'b0001} : begin`
357			`COMI_CH_SEL <= H_DAT_i[ 7:6];`
358			`CM_AB2TX_GO <= H_DAT_i[ 3:2];`
359			`CM_RX2AB_GO <= H_DAT_i[ 1:0];`
360			`end`
361			`{ADDR_WB_CTR, 4'b0010} : PKT_SIZE <= H_DAT_i[15:14];`
362			`{ADDR_WB_CTR, 4'b0100} : COMI_ACR <= H_DAT_i[23:20];`
363			`{ADDR_WB_CTR, 4'b1000} : WB_CTR <= H_DAT_i[31:30];`
364
365			`/writing FIFO is not performed here/`
366
367			`{ADDR_CH1TXSE, 4'b0001} : CH1_TX_SAR[ 7:0] <= H_DAT_i[7:0];`
368			`{ADDR_CH1TXSE, 4'b0010} : CH1_TX_SAR[15:8] <= H_DAT_i[15:8];`
369			`{ADDR_CH1TXSE, 4'b0100} : CH1_TX_SAR[23:16] <= H_DAT_i[23:16];`
370			`{ADDR_CH1TXSE, 4'b1000} : CH1_TX_SAR[31:24] <= H_DAT_i[31:24];`
371			`{ADDR_CH1RXSE, 4'b0001} : CH1_RX_SAR[ 7:0] <= H_DAT_i[7:0];`
372			`{ADDR_CH1RXSE, 4'b0010} : CH1_RX_SAR[15:8] <= H_DAT_i[15:8];`
373			`{ADDR_CH1RXSE, 4'b0100} : CH1_RX_SAR[23:16] <= H_DAT_i[23:16];`
374			`{ADDR_CH1RXSE, 4'b1000} : CH1_RX_SAR[31:24] <= H_DAT_i[31:24];`
375
376			`{ADDR_CH2TXSE, 4'b0001} : CH2_TX_SAR[ 7:0] <= H_DAT_i[7:0];`
377			`{ADDR_CH2TXSE, 4'b0010} : CH2_TX_SAR[15:8] <= H_DAT_i[15:8];`
378			`{ADDR_CH2TXSE, 4'b0100} : CH2_TX_SAR[23:16] <= H_DAT_i[23:16];`
379			`{ADDR_CH2TXSE, 4'b1000} : CH2_TX_SAR[31:24] <= H_DAT_i[31:24];`
380			`{ADDR_CH2RXSE, 4'b0001} : CH2_RX_SAR[ 7:0] <= H_DAT_i[7:0];`
381			`{ADDR_CH2RXSE, 4'b0010} : CH2_RX_SAR[15:8] <= H_DAT_i[15:8];`
382			`{ADDR_CH2RXSE, 4'b0100} : CH2_RX_SAR[23:16] <= H_DAT_i[23:16];`
383			`{ADDR_CH2RXSE, 4'b1000} : CH2_RX_SAR[31:24] <= H_DAT_i[31:24];`
384
385			`{ADDR_CH3TXSE, 4'b0001} : CH3_TX_SAR[ 7:0] <= H_DAT_i[7:0];`
386			`{ADDR_CH3TXSE, 4'b0010} : CH3_TX_SAR[15:8] <= H_DAT_i[15:8];`
387			`{ADDR_CH3TXSE, 4'b0100} : CH3_TX_SAR[23:16] <= H_DAT_i[23:16];`
388			`{ADDR_CH3TXSE, 4'b1000} : CH3_TX_SAR[31:24] <= H_DAT_i[31:24];`
389			`{ADDR_CH3RXSE, 4'b0001} : CH3_RX_SAR[ 7:0] <= H_DAT_i[7:0];`
390			`{ADDR_CH3RXSE, 4'b0010} : CH3_RX_SAR[15:8] <= H_DAT_i[15:8];`
391			`{ADDR_CH3RXSE, 4'b0100} : CH3_RX_SAR[23:16] <= H_DAT_i[23:16];`
392			`{ADDR_CH3RXSE, 4'b1000} : CH3_RX_SAR[31:24] <= H_DAT_i[31:24];`
393
394			`default: $display("Warning : missing write objective. h%, h%", H_ADR_i, H_SEL_i);`
395
396			`endcase`
397			`end`
398			`end // end always @...`
399
400			`/////////////////////////// HOCI read registers////////////////////////////////////`
401
402			`// Read SpW registers - include FIFOs of RX/TX`
403
404			`always @(*)`
405			`if( H_CYC_i && !H_WE_i && H_STB_i ) // Read`
406			`begin`
407			`case (H_ADR_i) // synthesis parallel_case`
408			`ADDR_SPE1 : H_DAT_o = SPE_CTL1;`
409			`ADDR_CTR_STA1 : H_DAT_o = { STA_TX1, STA_RX1, CTL_TX1, CTL_RX1 };`
410			`ADDR_SPE2 : H_DAT_o = SPE_CTL2;`
411			`ADDR_CTR_STA2 : H_DAT_o = { STA_TX2, STA_RX2, CTL_TX2, CTL_RX2 };`
412			`ADDR_SPE3 : H_DAT_o = SPE_CTL3;`
413			`ADDR_CTR_STA3 : H_DAT_o = { STA_TX3, STA_RX3, CTL_TX3, CTL_RX3 };`
414			`ADDR_WB_CTR : H_DAT_o = { WB_CTR, COMI_ACR, PKT_SIZE, COMI_CH_SEL };`
415			`ADDR_CH1R_FIFO : H_DAT_o = { rxbuf1_data_i[7:0], rxbuf1_data_i[7:0], rxbuf1_data_i[7:0], rxbuf1_data_i[7:0] };`
416			`ADDR_CH2R_FIFO : H_DAT_o = { rxbuf2_data_i[7:0], rxbuf2_data_i[7:0], rxbuf2_data_i[7:0], rxbuf2_data_i[7:0] };`
417			`ADDR_CH3R_FIFO : H_DAT_o = { rxbuf3_data_i[7:0], rxbuf3_data_i[7:0], rxbuF3_data_i[7:0], rxbuf3_data_i[7:0] };`
418			`ADDR_CH1TXSE : H_DAT_o = { CH1_TX_SAR, CH1_TX_EAR };`
419			`ADDR_CH1RXSE : H_DAT_o = { CH1_RX_SAR, CH1_RX_EAR };`
420			`ADDR_CH2TXSE : H_DAT_o = { CH2_TX_SAR, CH2_TX_EAR };`
421			`ADDR_CH2RXSE : H_DAT_o = { CH2_RX_SAR, CH2_RX_EAR };`
422			`ADDR_CH3TXSE : H_DAT_o = { CH3_TX_SAR, CH3_TX_EAR };`
423			`ADDR_CH3RXSE : H_DAT_o = { CH3_RX_SAR, CH3_RX_EAR };`
424			`default : H_DAT_o = 32'hxxxx;`
425			`endcase`
426			`end`
427
428
429
430
431			`///////////////////////////`
432			`// LET'S TALK ABOUT FIFO //`
433			`///////////////////////////`
434			`/////////////////////// "H_ACK_o" and Write/read TX/RX FIFO /////////////////////`
435			`always @(*)`
436			`begin`
437
438			`H_ACK_o = 1'b0; // set default value`
439			`H_RTY_o = 1'b0;`
440
441			`if( H_CYC_i && H_WE_i && H_STB_i ) // if write`
442			`begin`
443			`{H_wr_tx1buf, H_wr_tx2buf, H_wr_tx3buf} = 0; // set default value`
444			`H_ACK_o = 1; // write to regs exclude FIFO is always permitted`
445			`case(H_ADR_i) // synthesis parallel_case`
446			`ADDR_CH1T_FIFO : begin`
447			`if(tx1buf_full_i ==False)`
448			`H_wr_tx1buf = 1'b1;`
449			`if(tx1buf_full_i ==True)`
450			`begin`
451			`H_ACK_o = 1'b0;`
452			`H_RTY_o = 1'b1;`
453			`end`
454			`end`
455			`ADDR_CH2T_FIFO : begin`
456			`if(tx32buf_full_i ==False)`
457			`H_wr_tx2buf = 1'b1;`
458			`if(tx2buf_full_i ==True)`
459			`begin`
460			`H_ACK_o = 1'b0;`
461			`H_RTY_o = 1'b1;`
462			`end`
463			`end`
464
465			`ADDR_CH3T_FIFO : begin`
466			`if(tx3buf_full_i ==False)`
467			`H_wr_tx3buf = 1'b1;`
468			`if(tx3buf_full_i ==True)`
469			`begin`
470			`H_ACK_o = 1'b0;`
471			`H_RTY_o = 1'b1;`
472			`end`
473			`end`
474			`default: begin`
475			`{H_rd_rx1buf, H_rd_rx2buf, H_rd_rx3buf} = 3'bx;`
476			`H_ACK_o = 1'bx;`
477			`end`
478			`endcase`
479			`end`
480			`else if( H_CYC_i && !H_WE_i && H_STB_i ) // if read`
481			`begin`
482			`{H_rd_rx1buf, H_rd_rx2buf, H_rd_rx3buf} = 0; // set default value`
483			`H_ACK_o = 1; // read to regs exclude FIFO is always permitted`
484			`case(H_ADR_i) // synthesis parallel_case`
485
486			`ADDR_CH1R_FIFO : begin`
487			`if(rx1buf_empty_i ==False)`
488			`H_rd_rx1buf = 1'b1;`
489			`if( rx1buf_empty_i ==True`
490			`&& rxbuf1_data_i[8] == 1'b1 )// if EOP/EEP, continue read but discard value read`
491			`begin`
492			`H_ACK_o = 1'b0;`
493			`H_RTY_o = 1'b1;`
494			`end`
495			`end`
496			`ADDR_CH2R_FIFO : begin`
497			`if(rx2buf_empty_i ==False)`
498			`H_rd_rx2buf = 1'b1;`
499			`if(rx2buf_empty_i ==True)`
500			`&& rxbuf2_data_i[8] == 1'b1 )// if EOP/EEP, continue read but discard value read`

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[/] [spacewire/] [trunk/] [rtl/] [WB_COMI_HOCI.v] - Blame information for rev 27