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5 |
jorisvr |
/*
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* Test program for SpaceWire Light SPWAMBA core in LEON3 environment.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <asm-leon/irq.h>
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#include <asm-leon/amba.h>
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/*
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* The following defines are set in the Makefile:
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* TXCLKFREQ TX base clock frequency in MHz
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* DESCTABLESIZE Size of descriptor table as 2-log of nr of descriptors
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6 |
jorisvr |
* QUEUEFILL Number of bytes needed to ALMOST fill up TX and RX queues
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5 |
jorisvr |
* LOOPBACKSWITCH 1 if the spacewire loopback can be switched through UART RX enable
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*/
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#define DEVICE_SPACEWIRELIGHT 0x131
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/* APB registers */
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#define SPWAMBA_REG_CONTROL 0x00
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#define SPWAMBA_REG_STATUS 0x04
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#define SPWAMBA_REG_TXSCALER 0x08
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#define SPWAMBA_REG_TIMECODE 0x0c
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#define SPWAMBA_REG_RXDMA 0x10
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#define SPWAMBA_REG_TXDMA 0x14
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#define SPWAMBA_CONTROL_RESET 0x0001
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#define SPWAMBA_CONTROL_RESETDMA 0x0002
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#define SPWAMBA_CONTROL_START 0x0004
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#define SPWAMBA_CONTROL_DISABLE 0x0010
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#define SPWAMBA_CONTROL_EXTTICK 0x0020
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#define SPWAMBA_CONTROL_RXDMA 0x0040
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#define SPWAMBA_CONTROL_TXDMA 0x0080
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#define SPWAMBA_CONTROL_TXCANCEL 0x0100
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#define SPWAMBA_CONTROL_IESTATUS 0x0200
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#define SPWAMBA_CONTROL_IETICK 0x0400
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#define SPWAMBA_CONTROL_IERXDESC 0x0800
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#define SPWAMBA_CONTROL_IETXDESC 0x1000
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#define SPWAMBA_CONTROL_IERXPACKET 0x2000
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#define SPWAMBA_STATUS_RXDMA 0x0040
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#define SPWAMBA_STATUS_TXDMA 0x0080
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#define SPWAMBA_STATUS_RXDESC 0x0800
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#define SPWAMBA_STATUS_TXDESC 0x1000
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#define SPWAMBA_STATUS_RXPACKET 0x2000
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/* Value test macros. */
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#define CHECK_VALUE(label, v, expect) ( ((v) == (expect)) || (printf("CHECK FAILED: line %d, %s, got 0x%08x, expected 0x%08x\n", __LINE__, (label), (v), (expect)), fail(), 1) )
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#define CHECK_CONDITION(label, v, cond) ( (cond) || (printf("CHECK FAILED: line %d, %s, got 0x%08x\n", __LINE__, (label), (v)), fail(), 1) )
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/* Points to data register of first UART */
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extern int *console;
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struct descriptor_struct {
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volatile unsigned int f; /* descriptor flags */
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volatile unsigned char *d; /* data pointer */
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} __attribute__ ((packed));
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static unsigned long spwamba_start;
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static unsigned long spwamba_irq;
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static volatile int irq_expect;
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static volatile unsigned int irq_count;
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static struct descriptor_struct *rxdesctable;
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static struct descriptor_struct *txdesctable;
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static unsigned char *buf;
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/* Put LEON3 in powerdown mode to indicate success. */
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static void powerdown(void)
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{
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asm volatile (
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" rd %%psr, %%g1 \n"
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" andn %%g1, 0x20, %%g1 \n"
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" wr %%g1, %%psr \n"
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" nop ; nop ; nop \n"
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" wr %%g0, %%asr19 \n"
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" nop ; nop ; nop "
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: : : "g1" );
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}
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/* Put LEON3 in error mode to indicate failure. */
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static void fail(void) __attribute__ ((noreturn));
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static void fail(void)
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{
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asm volatile (
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" rd %%psr, %%g1 \n"
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" andn %%g1, 0x20, %%g1 \n"
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" wr %%g1, %%psr \n"
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" nop ; nop ; nop \n"
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" unimp 0 \n"
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" nop "
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: : : "g1" );
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exit(1);
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}
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/* Write to SPWAMBA register. */
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static inline void spwamba_write(unsigned int reg, unsigned int val)
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{
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(*(volatile unsigned int *)(spwamba_start + reg)) = val;
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}
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/* Read from SPWAMBA register. */
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static inline unsigned int spwamba_read(unsigned int reg)
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{
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return (*(volatile unsigned int *)(spwamba_start + reg));
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}
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/* SPWAMBA interrupt handler. */
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static int spwamba_interrupt(int irq, void *dev_id, struct leonbare_pt_regs *pt_regs)
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{
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if (!irq_expect) {
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printf("ERROR: spurious SPWAMBA interrupt\n");
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fail();
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}
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irq_count++;
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return 0;
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}
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/* Verify default values of APB registers. */
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static void check_default_regs(void)
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{
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unsigned int v;
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/* reg_control: expect all zeroes except for desctablesize=5 */
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v = spwamba_read(SPWAMBA_REG_CONTROL);
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CHECK_VALUE("reg_control", v, (DESCTABLESIZE << 24));
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_VALUE("reg_status", v, 0x4000);
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/* reg_txscaler: expect (TXCLKFREQ / 10 - 1) for 10 Mbit */
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v = spwamba_read(SPWAMBA_REG_TXSCALER);
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CHECK_VALUE("reg_txscaler", v, TXCLKFREQ / 10 - 1);
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v = spwamba_read(SPWAMBA_REG_TIMECODE);
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CHECK_VALUE("reg_timecode", v, 0);
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v = spwamba_read(SPWAMBA_REG_RXDMA);
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CHECK_VALUE("reg_rxdma", v, 0);
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v = spwamba_read(SPWAMBA_REG_TXDMA);
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CHECK_VALUE("reg_txdma", v, 0);
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}
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/* Test that the specified register bits are read/writeable. */
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static void test_reg_readwrite(unsigned int reg, unsigned int mask)
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{
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unsigned int i, v, t;
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v = 0;
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for (i = 0; i <= 32; i++) {
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if (v == 0 || (v & mask) != 0) {
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spwamba_write(reg, v);
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t = spwamba_read(reg);
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if ((t & mask) != v) {
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printf("ERROR: invalid value in register 0x%02x, wrote 0x%08x, got 0x%08x\n", reg, v, t);
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fail();
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}
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}
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v = (1 << i);
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}
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}
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/* Basic test of APB registers. */
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static void test_regs(void)
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{
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/* test default values */
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check_default_regs();
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printf("default APB register values [OK]\n");
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/* test read/write access */
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test_reg_readwrite(SPWAMBA_REG_CONTROL, 0x3e3c);
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test_reg_readwrite(SPWAMBA_REG_TXSCALER, 0xff);
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test_reg_readwrite(SPWAMBA_REG_TIMECODE, 0x3f00);
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test_reg_readwrite(SPWAMBA_REG_RXDMA, 0xfffffff8);
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test_reg_readwrite(SPWAMBA_REG_TXDMA, 0xfffffff8);
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printf("read/write access to APB registers [OK]\n");
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/* test effect of reset command on registers */
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spwamba_write(SPWAMBA_REG_CONTROL, 0x3e00);
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spwamba_write(SPWAMBA_REG_TXSCALER, 0xff);
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spwamba_write(SPWAMBA_REG_TIMECODE, 0x3f);
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spwamba_write(SPWAMBA_REG_RXDMA, 0xfffffff8);
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spwamba_write(SPWAMBA_REG_TXDMA, 0xfffffff8);
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spwamba_write(SPWAMBA_REG_CONTROL, 0x3e21);
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check_default_regs();
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printf("reset of APB registers [OK]\n");
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}
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/* Test SpaceWire link */
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void test_link(void)
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{
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unsigned int i, v;
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/* start link */
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spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_START);
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/* wait until link up */
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v = spwamba_read(SPWAMBA_REG_STATUS);
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for (i = 0; i < 250 && (v & 3) == 0; i++)
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v = spwamba_read(SPWAMBA_REG_STATUS);
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for (i = 0; i < 250 && (v & 3) == 1; i++)
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v = spwamba_read(SPWAMBA_REG_STATUS);
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for (i = 0; i < 250 && (v & 3) == 2; i++)
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_VALUE("reg_status", v, 0x4003);
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printf("SpaceWire link up [OK]\n");
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/* shut down link */
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spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_DISABLE);
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spwamba_write(SPWAMBA_REG_CONTROL, 0);
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/* check link down */
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_VALUE("reg_status", v, 0x4000);
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printf("SpaceWire link down [OK]\n");
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irq_count = 0;
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irq_expect = 1;
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spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_START | SPWAMBA_CONTROL_IESTATUS);
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/* wait until link up */
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v = spwamba_read(SPWAMBA_REG_STATUS);
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for (i = 0; i < 250 && (v & 3) != 3; i++)
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_VALUE("reg_status", v, 0x4003);
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CHECK_VALUE("irq_count", irq_count, 1);
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/* shut link down */
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spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_DISABLE | SPWAMBA_CONTROL_IESTATUS);
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spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_IESTATUS);
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/* check link down */
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_VALUE("reg_status", v, 0x4000);
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CHECK_VALUE("irq_count", irq_count, 2);
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printf("interrupt on status change [OK]\n");
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#if LOOPBACKSWITCH
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/* restart link */
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spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_START | SPWAMBA_CONTROL_IESTATUS);
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v = spwamba_read(SPWAMBA_REG_STATUS);
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for (i = 0; i < 250 && (v & 3) != 3; i++)
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_VALUE("reg_status", v, 0x4003);
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CHECK_VALUE("irq_count", irq_count, 3);
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/* unplug link, link should go down */
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console[2] &= ~LEON_REG_UART_CTRL_RE;
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v = spwamba_read(SPWAMBA_REG_STATUS);
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for (i = 0; i < 40 && (v & 3) == 3; i++)
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_CONDITION("reg_status", v, (v & 0x03) != 3 &&
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(v & 0x1c) != 0 &&
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(v & 0xffffffe0) == 0x4000);
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CHECK_VALUE("irq_count", irq_count, 4);
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/* clear sticky bits */
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spwamba_write(SPWAMBA_REG_STATUS, 0xffffffe3);
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i = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_CONDITION("reg_status", i, (v & 0xfffffffc) == (i & 0xfffffffc));
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spwamba_write(SPWAMBA_REG_STATUS, v);
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_CONDITION("reg_status", v, (v & 0xfffffffc) == 0x4000);
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printf("sticky error bits [OK]\n");
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/* replug link and check that link is restored*/
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console[2] |= LEON_REG_UART_CTRL_RE;
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| 276 |
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v = spwamba_read(SPWAMBA_REG_STATUS);
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for (i = 0; i < 250 && (v & 3) != 3; i++)
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_VALUE("reg_status", v, 0x4003);
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CHECK_VALUE("irq_count", irq_count, 5);
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| 282 |
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/* release link start line, link should stay up */
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| 283 |
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irq_expect = 0;
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spwamba_write(SPWAMBA_REG_CONTROL, 0);
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v = spwamba_read(SPWAMBA_REG_STATUS);
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for (i = 0; i < 40 && (v & 3) == 3; i++)
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_VALUE("reg_status", v, 0x4003);
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| 290 |
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/* pull plug, link should go down */
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console[2] &= ~LEON_REG_UART_CTRL_RE;
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v = spwamba_read(SPWAMBA_REG_STATUS);
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for (i = 0; i < 40 && (v & 3) == 3; i++)
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v = spwamba_read(SPWAMBA_REG_STATUS);
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CHECK_CONDITION("reg_status", v, (v & 0x1c) != 0 &&
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| 296 |
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(v & 0xffffffe3) == 0x4000);
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| 297 |
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spwamba_write(SPWAMBA_REG_STATUS, 0x3c);
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/* restore plug, link should stay down */
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console[2] |= LEON_REG_UART_CTRL_RE;
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| 301 |
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v = spwamba_read(SPWAMBA_REG_STATUS);
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| 302 |
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for (i = 0; i < 40 && (v & 3) == 0; i++)
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| 303 |
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v = spwamba_read(SPWAMBA_REG_STATUS);
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| 304 |
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CHECK_VALUE("reg_status", v, 0x4000);
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| 305 |
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| 306 |
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printf("handling physical disconnection [OK]\n");
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#endif
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| 308 |
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}
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| 309 |
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|
| 311 |
|
|
/* Test sending/receiving of time codes */
|
| 312 |
|
|
void test_timecode(void)
|
| 313 |
|
|
{
|
| 314 |
|
|
unsigned int i, v;
|
| 315 |
|
|
|
| 316 |
|
|
/* request time code transmission (link still down) */
|
| 317 |
|
|
spwamba_write(SPWAMBA_REG_TIMECODE, 0x131ff);
|
| 318 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 319 |
|
|
CHECK_VALUE("reg_status", v, 0x4000);
|
| 320 |
|
|
v = spwamba_read(SPWAMBA_REG_TIMECODE);
|
| 321 |
|
|
CHECK_VALUE("reg_timecode", v, 0x3200);
|
| 322 |
|
|
|
| 323 |
|
|
/* start link */
|
| 324 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_START);
|
| 325 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 326 |
|
|
for (i = 0; i < 250 && (v & 3) != 3; i++)
|
| 327 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 328 |
|
|
for (i = 0; i < 50 && (v & 0x400) == 0; i++)
|
| 329 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 330 |
|
|
CHECK_VALUE("reg_status", v, 0x4003);
|
| 331 |
|
|
v = spwamba_read(SPWAMBA_REG_TIMECODE);
|
| 332 |
|
|
CHECK_VALUE("reg_timecode", v, 0x3200);
|
| 333 |
|
|
|
| 334 |
|
|
/* request time code transmission and wait for timecode received */
|
| 335 |
|
|
spwamba_write(SPWAMBA_REG_TIMECODE, 0x13200);
|
| 336 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 337 |
|
|
for (i = 0; i < 50 && (v & 0x400) == 0; i++)
|
| 338 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 339 |
|
|
CHECK_VALUE("reg_status", v, 0x4403);
|
| 340 |
|
|
v = spwamba_read(SPWAMBA_REG_TIMECODE);
|
| 341 |
|
|
CHECK_VALUE("reg_timecode", v, 0x3332);
|
| 342 |
|
|
printf("send/receive timecode [OK]\n");
|
| 343 |
|
|
|
| 344 |
|
|
/* enable interrupt on time code */
|
| 345 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_IETICK);
|
| 346 |
|
|
|
| 347 |
|
|
/* manually send time code and expect interrupt */
|
| 348 |
|
|
irq_count = 0;
|
| 349 |
|
|
irq_expect = 1;
|
| 350 |
|
|
spwamba_write(SPWAMBA_REG_TIMECODE, 0x10f00);
|
| 351 |
|
|
for (i = 0; i < 50 && irq_count == 0; i++) ;
|
| 352 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 353 |
|
|
CHECK_VALUE("reg_status", v, 0x4403);
|
| 354 |
|
|
v = spwamba_read(SPWAMBA_REG_TIMECODE);
|
| 355 |
|
|
CHECK_VALUE("reg_timecode", v, 0x100f);
|
| 356 |
|
|
CHECK_VALUE("irq_count", irq_count, 1);
|
| 357 |
|
|
v = spwamba_read(SPWAMBA_REG_TIMECODE);
|
| 358 |
|
|
printf("interrupt on time code [OK]\n");
|
| 359 |
|
|
|
| 360 |
|
|
/* clear sticky status bit */
|
| 361 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 362 |
|
|
CHECK_VALUE("reg_status", v, 0x4403);
|
| 363 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, 0x400);
|
| 364 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 365 |
|
|
CHECK_VALUE("reg_status", v, 0x4003);
|
| 366 |
|
|
|
| 367 |
|
|
/* set up GPTIMER to generate external time tick after 4 us;
|
| 368 |
|
|
external tick signal should be ignored */
|
| 369 |
|
|
LEON3_GpTimer_Regs->e[1].rld = 4;
|
| 370 |
|
|
LEON3_GpTimer_Regs->e[1].ctrl = 0x05;
|
| 371 |
|
|
v = spwamba_read(SPWAMBA_REG_TIMECODE);
|
| 372 |
|
|
for (i = 0; i < 100 && v == 0x100f; i++)
|
| 373 |
|
|
v = spwamba_read(SPWAMBA_REG_TIMECODE);
|
| 374 |
|
|
CHECK_VALUE("reg_timecode", v, 0x100f);
|
| 375 |
|
|
|
| 376 |
|
|
/* enable external time tick and wait for timecode received */
|
| 377 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_IETICK | SPWAMBA_CONTROL_EXTTICK);
|
| 378 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 379 |
|
|
for (i = 0; i < 100 && (v & 0x400) == 0; i++)
|
| 380 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 381 |
|
|
CHECK_VALUE("reg_status", v, 0x4003);
|
| 382 |
|
|
LEON3_GpTimer_Regs->e[1].ctrl = 0x05;
|
| 383 |
|
|
for (i = 0; i < 100 && (v & 0x400) == 0; i++)
|
| 384 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 385 |
|
|
CHECK_VALUE("reg_status", v, 0x4403);
|
| 386 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 387 |
|
|
v = spwamba_read(SPWAMBA_REG_TIMECODE);
|
| 388 |
|
|
CHECK_VALUE("reg_timecode", v, 0x1110);
|
| 389 |
|
|
CHECK_VALUE("irq_count", irq_count, 2);
|
| 390 |
|
|
printf("external tick_in signal [OK]\n");
|
| 391 |
|
|
|
| 392 |
|
|
/* clear sticky status bits */
|
| 393 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 394 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 395 |
|
|
|
| 396 |
|
|
/* disable external time codes, disable timecode interrupts */
|
| 397 |
|
|
irq_expect = 0;
|
| 398 |
|
|
LEON3_GpTimer_Regs->e[1].ctrl = 0;
|
| 399 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, 0);
|
| 400 |
|
|
|
| 401 |
|
|
/* note: link still up */
|
| 402 |
|
|
}
|
| 403 |
|
|
|
| 404 |
|
|
|
| 405 |
|
|
/* Create 2048 bytes dummy data for transfer tests. */
|
| 406 |
|
|
static void create_test_data(void)
|
| 407 |
|
|
{
|
| 408 |
|
|
unsigned int i, j, k, t;
|
| 409 |
|
|
buf[0] = j = k = 1;
|
| 410 |
|
|
for (i = 1; i < 2048; i++) {
|
| 411 |
|
|
buf[i] = j;
|
| 412 |
|
|
t = j;
|
| 413 |
|
|
j += k;
|
| 414 |
|
|
k = t;
|
| 415 |
|
|
}
|
| 416 |
|
|
}
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
/* Check that dummy data has not accidentally been overwritten. */
|
| 420 |
|
|
static void check_test_data(void)
|
| 421 |
|
|
{
|
| 422 |
|
|
unsigned int i, j, k, t;
|
| 423 |
|
|
CHECK_VALUE("dummydata", buf[0], 1);
|
| 424 |
|
|
j = k = 1;
|
| 425 |
|
|
for (i = 1; i < 1024; i++) {
|
| 426 |
|
|
CHECK_VALUE("dummydata", buf[i], (unsigned char)j);
|
| 427 |
|
|
buf[i] = j;
|
| 428 |
|
|
t = j;
|
| 429 |
|
|
j += k;
|
| 430 |
|
|
k = t;
|
| 431 |
|
|
}
|
| 432 |
|
|
}
|
| 433 |
|
|
|
| 434 |
|
|
|
| 435 |
|
|
/* Test rxdesc/txdesc/rxpacket interrupts. */
|
| 436 |
|
|
static void test_data_interrupt(unsigned int iemask)
|
| 437 |
|
|
{
|
| 438 |
|
|
unsigned int i, v;
|
| 439 |
|
|
|
| 440 |
|
|
/* Reset DMA; reset sticky status bits */
|
| 441 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RESETDMA);
|
| 442 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 443 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 444 |
|
|
|
| 445 |
|
|
irq_count = 0;
|
| 446 |
|
|
irq_expect = 1;
|
| 447 |
|
|
|
| 448 |
|
|
/* Start TX dma */
|
| 449 |
|
|
txdesctable[0].f = 0x170003; /* EOP, EN, IE, WR, 3 bytes */
|
| 450 |
|
|
txdesctable[0].d = buf;
|
| 451 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)txdesctable);
|
| 452 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA | iemask);
|
| 453 |
|
|
|
| 454 |
|
|
/* Wait until packet transmitted */
|
| 455 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 456 |
|
|
for (i = 0; i < 200 && (v & 0x80) != 0; i++)
|
| 457 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 458 |
|
|
CHECK_CONDITION("reg_status", v, (v & 0x3fff) == 0x1003);
|
| 459 |
|
|
CHECK_VALUE("irq_count", irq_count, (iemask & SPWAMBA_CONTROL_IETXDESC) ? 1 : 0);
|
| 460 |
|
|
irq_count = 0;
|
| 461 |
|
|
|
| 462 |
|
|
/* Start RX dma */
|
| 463 |
|
|
rxdesctable[0].f = 0x10400; /* EN, 1024 bytes */
|
| 464 |
|
|
rxdesctable[0].d = buf + 8192;
|
| 465 |
|
|
rxdesctable[1].f = 0x70400; /* EN, IE, WR, 1024 bytes */
|
| 466 |
|
|
rxdesctable[1].d = buf + 8196;
|
| 467 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)rxdesctable);
|
| 468 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA | iemask);
|
| 469 |
|
|
|
| 470 |
|
|
/* Wait until packet received */
|
| 471 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 472 |
|
|
for (i = 0; i < 200 && (v & 0x2000) == 0; i++)
|
| 473 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 474 |
|
|
CHECK_VALUE("reg_status", v, 0x7043);
|
| 475 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 476 |
|
|
CHECK_VALUE("irq_count", irq_count, (iemask & SPWAMBA_CONTROL_IERXPACKET) ? 1 : 0);
|
| 477 |
|
|
irq_count = 0;
|
| 478 |
|
|
|
| 479 |
|
|
/* Start TX dma */
|
| 480 |
|
|
txdesctable[0].f = 0x130003; /* EOP, EN, WR, 3 bytes */
|
| 481 |
|
|
txdesctable[0].d = buf + 4;
|
| 482 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA | iemask);
|
| 483 |
|
|
|
| 484 |
|
|
/* Wait until packet received */
|
| 485 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 486 |
|
|
for (i = 0; i < 200 && (v & 0x2000) == 0; i++)
|
| 487 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 488 |
|
|
CHECK_VALUE("reg_status", v, 0x6843);
|
| 489 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 490 |
|
|
CHECK_VALUE("irq_count", irq_count, (iemask & (SPWAMBA_CONTROL_IERXPACKET | SPWAMBA_CONTROL_IERXDESC)) ? 1 : 0);
|
| 491 |
|
|
irq_count = 0;
|
| 492 |
|
|
|
| 493 |
|
|
/* Disable interrupts; reset DMA */
|
| 494 |
|
|
irq_expect = 0;
|
| 495 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RESETDMA);
|
| 496 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 497 |
|
|
CHECK_VALUE("reg_status", v, 0x4003);
|
| 498 |
|
|
}
|
| 499 |
|
|
|
| 500 |
|
|
|
| 501 |
|
|
/* Test DMA and data transfer. */
|
| 502 |
|
|
static void test_data(void)
|
| 503 |
|
|
{
|
| 504 |
|
|
unsigned int i, j, k, v;
|
| 505 |
|
|
|
| 506 |
|
|
/* note: link still up */
|
| 507 |
|
|
|
| 508 |
|
|
/* sentinels in RX buffer */
|
| 509 |
|
|
buf[8200] = 0xa0;
|
| 510 |
|
|
buf[9216] = 0xa1;
|
| 511 |
|
|
buf[9220] = 0xa2;
|
| 512 |
|
|
buf[10244] = 0xa3;
|
| 513 |
|
|
buf[11268] = 0xa4;
|
| 514 |
|
|
buf[11272] = 0xa5;
|
| 515 |
|
|
|
| 516 |
|
|
/* set up one TX descriptor */
|
| 517 |
|
|
txdesctable[0].f = 0x00110004; /* EOP, EN, 4 bytes */
|
| 518 |
|
|
txdesctable[0].d = buf;
|
| 519 |
|
|
txdesctable[1].f = 0xfffeffff; /* disabled */
|
| 520 |
|
|
txdesctable[1].d = NULL;
|
| 521 |
|
|
|
| 522 |
|
|
/* set up two RX descriptors */
|
| 523 |
|
|
rxdesctable[0].f = 0x10400; /* EN, 1024 bytes */
|
| 524 |
|
|
rxdesctable[0].d = buf + 8192;
|
| 525 |
|
|
rxdesctable[1].f = 0x50400; /* IE, EN, 1024 bytes */
|
| 526 |
|
|
rxdesctable[1].d = buf + 9216;
|
| 527 |
|
|
rxdesctable[2].f = 0; /* disabled */
|
| 528 |
|
|
rxdesctable[2].d = NULL;
|
| 529 |
|
|
|
| 530 |
|
|
/* start TX dma and wait until complete */
|
| 531 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)txdesctable);
|
| 532 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 533 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 534 |
|
|
for (i = 0; i < 200 && (v & 0x80) != 0; i++)
|
| 535 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 536 |
|
|
CHECK_CONDITION("reg_status", v, (v & 0x3fff) == 0x0003);
|
| 537 |
|
|
|
| 538 |
|
|
/* check TX descriptor status */
|
| 539 |
|
|
v = spwamba_read(SPWAMBA_REG_TXDMA);
|
| 540 |
|
|
CHECK_VALUE("reg_txdma", v, ((unsigned int)txdesctable) + 8);
|
| 541 |
|
|
CHECK_VALUE("txdesctable[0].f", txdesctable[0].f, 0x00180000);
|
| 542 |
|
|
CHECK_VALUE("txdesctable[0].d", (unsigned int)txdesctable[0].d, (unsigned int)buf);
|
| 543 |
|
|
CHECK_VALUE("txdesctable[1].f", txdesctable[1].f, 0xfffeffff);
|
| 544 |
|
|
|
| 545 |
|
|
/* start RX dma and wait until packet received */
|
| 546 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)rxdesctable);
|
| 547 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA);
|
| 548 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 549 |
|
|
for (i = 0; i < 200 && (v & 0x2000) == 0; i++)
|
| 550 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 551 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 552 |
|
|
|
| 553 |
|
|
/* check RX descriptor status */
|
| 554 |
|
|
v = spwamba_read(SPWAMBA_REG_RXDMA);
|
| 555 |
|
|
CHECK_VALUE("reg_rxdma", v, ((unsigned int)rxdesctable) + 8);
|
| 556 |
|
|
CHECK_VALUE("rxdesctable[0].f", rxdesctable[0].f, 0x00180004);
|
| 557 |
|
|
CHECK_VALUE("rxdesctable[0].d", (unsigned int)rxdesctable[0].d, ((unsigned int)buf) + 8192);
|
| 558 |
|
|
CHECK_VALUE("rxdesctable[1].f", rxdesctable[1].f, 0x00050400);
|
| 559 |
|
|
|
| 560 |
|
|
/* check received data */
|
| 561 |
|
|
for (i = 0; i < 4; i++)
|
| 562 |
|
|
CHECK_VALUE("rxdata", buf[8192+i], buf[i]);
|
| 563 |
|
|
for (i = 0; i < 4; i++)
|
| 564 |
|
|
CHECK_VALUE("rxeop", buf[8196+i], 0x00);
|
| 565 |
|
|
CHECK_VALUE("rx sentinel", buf[8200], 0xa0);
|
| 566 |
|
|
CHECK_VALUE("rx sentinel", buf[9216], 0xa1);
|
| 567 |
|
|
|
| 568 |
|
|
/* sticky rxpacket bit */
|
| 569 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 570 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 571 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 572 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 573 |
|
|
CHECK_VALUE("reg_status", v, 0x4043);
|
| 574 |
|
|
|
| 575 |
|
|
printf("transfer packet [OK]\n");
|
| 576 |
|
|
|
| 577 |
|
|
/* send another packet */
|
| 578 |
|
|
txdesctable[1].f = 0x00110003; /* EOP, EN, 3 bytes */
|
| 579 |
|
|
txdesctable[1].d = buf + 4;
|
| 580 |
|
|
txdesctable[2].f = 0;
|
| 581 |
|
|
|
| 582 |
|
|
/* start TX dma and wait until complete */
|
| 583 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 584 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 585 |
|
|
for (i = 0; i < 200 && (v & 0x80) != 0; i++)
|
| 586 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 587 |
|
|
CHECK_VALUE("txdesctable[1].f", txdesctable[1].f, 0x00180000);
|
| 588 |
|
|
|
| 589 |
|
|
/* wait until packet received and check status */
|
| 590 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 591 |
|
|
for (i = 0; i < 200 && (v & 0x2000) == 0; i++)
|
| 592 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 593 |
|
|
CHECK_VALUE("reg_status", v, 0x6843);
|
| 594 |
|
|
v = spwamba_read(SPWAMBA_REG_RXDMA);
|
| 595 |
|
|
CHECK_VALUE("reg_rxdma", v, ((unsigned int)rxdesctable) + 0x10);
|
| 596 |
|
|
CHECK_VALUE("rxdesctable[1].f", rxdesctable[1].f, 0x001c0003);
|
| 597 |
|
|
|
| 598 |
|
|
/* check received data */
|
| 599 |
|
|
for (i = 0; i < 3; i++)
|
| 600 |
|
|
CHECK_VALUE("rxdata", buf[9216+i], buf[4+i]);
|
| 601 |
|
|
CHECK_VALUE("rxeop", buf[9219], 0x00);
|
| 602 |
|
|
CHECK_VALUE("rx sentinel", buf[9220], 0xa2);
|
| 603 |
|
|
|
| 604 |
|
|
/* sticky rxpacket, rxframe bits */
|
| 605 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 606 |
|
|
CHECK_VALUE("reg_status", v, 0x6843);
|
| 607 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, 0x2000);
|
| 608 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 609 |
|
|
CHECK_VALUE("reg_status", v, 0x4843);
|
| 610 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, 0x0800);
|
| 611 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 612 |
|
|
CHECK_VALUE("reg_status", v, 0x4043);
|
| 613 |
|
|
|
| 614 |
|
|
printf("transfer packet (2) [OK]\n");
|
| 615 |
|
|
|
| 616 |
|
|
/* send another packet */
|
| 617 |
|
|
txdesctable[2].f = 0x00150002; /* EOP, IE, EN, 2 bytes */
|
| 618 |
|
|
txdesctable[2].d = buf + 8;
|
| 619 |
|
|
txdesctable[3].f = 0;
|
| 620 |
|
|
|
| 621 |
|
|
/* start TX dma and wait until complete */
|
| 622 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 623 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 624 |
|
|
for (i = 0; i < 200 && (v & 0x80) == 0x80; i++)
|
| 625 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 626 |
|
|
CHECK_VALUE("txdesctable[2].f", txdesctable[2].f, 0x001c0000);
|
| 627 |
|
|
|
| 628 |
|
|
/* wait until RX dma disabled */
|
| 629 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 630 |
|
|
for (i = 0; i < 200 && (v & 0x40) != 0; i++)
|
| 631 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 632 |
|
|
CHECK_VALUE("reg_status", v, 0x1003);
|
| 633 |
|
|
v = spwamba_read(SPWAMBA_REG_RXDMA);
|
| 634 |
|
|
CHECK_VALUE("reg_rxdma", v, ((unsigned int)rxdesctable) + 0x10);
|
| 635 |
|
|
CHECK_VALUE("rxdesctable[2].f", rxdesctable[2].f, 0);
|
| 636 |
|
|
|
| 637 |
|
|
/* sticky txframe bit */
|
| 638 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 639 |
|
|
CHECK_VALUE("reg_status", v, 0x1003);
|
| 640 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, 0x1000);
|
| 641 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 642 |
|
|
CHECK_VALUE("reg_status", v, 0x0003);
|
| 643 |
|
|
|
| 644 |
|
|
printf("stop RX dma at inactive descriptor [OK]\n");
|
| 645 |
|
|
|
| 646 |
|
|
/* resume RX DMA */
|
| 647 |
|
|
rxdesctable[2].f = 0x30400; /* EN, WR, 1024 bytes */
|
| 648 |
|
|
rxdesctable[2].d = buf + 10240;
|
| 649 |
|
|
rxdesctable[0].f = 0x10400; /* EN, 1024 bytes */
|
| 650 |
|
|
rxdesctable[0].d = buf + 11264;
|
| 651 |
|
|
rxdesctable[3].f = 0x10234; /* enabled but unused */
|
| 652 |
|
|
rxdesctable[3].d = NULL;
|
| 653 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA);
|
| 654 |
|
|
|
| 655 |
|
|
/* wait until pending packet received;
|
| 656 |
|
|
check RX descriptor wrapped */
|
| 657 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 658 |
|
|
for (i = 0; i < 200 && (v & 0x2000) == 0; i++)
|
| 659 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 660 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 661 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 662 |
|
|
v = spwamba_read(SPWAMBA_REG_RXDMA);
|
| 663 |
|
|
CHECK_VALUE("reg_rxdma", v, (unsigned int)rxdesctable);
|
| 664 |
|
|
CHECK_VALUE("rxdesctable[2].f", rxdesctable[2].f, 0x001a0002);
|
| 665 |
|
|
CHECK_VALUE("rxdesctable[3].f", rxdesctable[3].f, 0x00010234);
|
| 666 |
|
|
|
| 667 |
|
|
/* check received data */
|
| 668 |
|
|
CHECK_VALUE("rxdata", buf[10240], buf[8]);
|
| 669 |
|
|
CHECK_VALUE("rxdata", buf[10241], buf[9]);
|
| 670 |
|
|
CHECK_VALUE("rxeop", buf[10242], 0x00);
|
| 671 |
|
|
CHECK_VALUE("rxeop", buf[10243], 0x00);
|
| 672 |
|
|
CHECK_VALUE("rx sentinel", buf[10244], 0xa3);
|
| 673 |
|
|
|
| 674 |
|
|
printf("resume RX dma [OK]\n");
|
| 675 |
|
|
|
| 676 |
|
|
/* send another packet;
|
| 677 |
|
|
check TX descriptor wrapped */
|
| 678 |
|
|
txdesctable[3].f = 0x00130001; /* EOP, EN, WR, 1 byte */
|
| 679 |
|
|
txdesctable[3].d = buf + 12;
|
| 680 |
|
|
txdesctable[4].f = 0x00010123; /* enabled but unused */
|
| 681 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 682 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 683 |
|
|
for (i = 0; i < 200 && (v & 0x80) != 0; i++)
|
| 684 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 685 |
|
|
CHECK_VALUE("reg_status", v, 0x4043);
|
| 686 |
|
|
v = spwamba_read(SPWAMBA_REG_TXDMA);
|
| 687 |
|
|
CHECK_VALUE("reg_txdma", v, (unsigned int)txdesctable);
|
| 688 |
|
|
CHECK_VALUE("txdesctable[3].f", txdesctable[3].f, 0x001a0000);
|
| 689 |
|
|
CHECK_VALUE("txdesctable[4].f", txdesctable[4].f, 0x00010123);
|
| 690 |
|
|
|
| 691 |
|
|
/* wait until packet received */
|
| 692 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 693 |
|
|
for (i = 0; i < 200 && (v & 0x2000) == 0; i++)
|
| 694 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 695 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 696 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 697 |
|
|
v = spwamba_read(SPWAMBA_REG_RXDMA);
|
| 698 |
|
|
CHECK_VALUE("reg_rxdma", v, ((unsigned int)rxdesctable) + 8);
|
| 699 |
|
|
CHECK_VALUE("rxdesctable[0].f", rxdesctable[0].f, 0x00180001);
|
| 700 |
|
|
CHECK_VALUE("rxdesctable[3].f", rxdesctable[3].f, 0x00010234);
|
| 701 |
|
|
|
| 702 |
|
|
/* check received data */
|
| 703 |
|
|
CHECK_VALUE("rxdata", buf[11264], buf[12]);
|
| 704 |
|
|
CHECK_VALUE("rxeop", buf[11265], 0x00);
|
| 705 |
|
|
CHECK_VALUE("rxeop", buf[11266], 0x00);
|
| 706 |
|
|
CHECK_VALUE("rxeop", buf[11267], 0x00);
|
| 707 |
|
|
CHECK_VALUE("rx sentinel", buf[11268], 0xa4);
|
| 708 |
|
|
|
| 709 |
|
|
/* send packet and check descriptor auto-wrap */
|
| 710 |
|
|
k = (1 << DESCTABLESIZE) - 1;
|
| 711 |
|
|
txdesctable[k].f = 0x00110003; /* EOP, EN, 3 bytes */
|
| 712 |
|
|
txdesctable[k].d = buf + 16;
|
| 713 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)(&txdesctable[k]));
|
| 714 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 715 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 716 |
|
|
for (i = 0; i < 200 && (v & 0x80) != 0; i++)
|
| 717 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 718 |
|
|
v = spwamba_read(SPWAMBA_REG_TXDMA);
|
| 719 |
|
|
CHECK_VALUE("reg_txdma", v, (unsigned int)txdesctable);
|
| 720 |
|
|
CHECK_VALUE("txdesctable[k].f", txdesctable[k].f, 0x00180000);
|
| 721 |
|
|
|
| 722 |
|
|
/* wait until RX dma disabled */
|
| 723 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 724 |
|
|
for (i = 0; i < 200 && (v & 0x40) != 0; i++)
|
| 725 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 726 |
|
|
CHECK_VALUE("reg_status", v, 0x0003);
|
| 727 |
|
|
|
| 728 |
|
|
/* restart RX dma; receive packet; check descriptor auto-wrap */
|
| 729 |
|
|
rxdesctable[k].f = 0x10400; /* EN, 1024 bytes */
|
| 730 |
|
|
rxdesctable[k].d = buf + 11268;
|
| 731 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)(&rxdesctable[k]));
|
| 732 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA);
|
| 733 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 734 |
|
|
for (i = 0; i < 200 && (v & 0x2000) == 0; i++)
|
| 735 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 736 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 737 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 738 |
|
|
v = spwamba_read(SPWAMBA_REG_RXDMA);
|
| 739 |
|
|
CHECK_VALUE("reg_rxdma", v, (unsigned int)rxdesctable);
|
| 740 |
|
|
CHECK_VALUE("rxdesctable[k].f", rxdesctable[k].f, 0x00180003);
|
| 741 |
|
|
|
| 742 |
|
|
/* check received data */
|
| 743 |
|
|
for (i = 0; i < 3; i++)
|
| 744 |
|
|
CHECK_VALUE("rxdata", buf[11268+i], buf[16+i]);
|
| 745 |
|
|
CHECK_VALUE("rxeop", buf[11271], 0x00);
|
| 746 |
|
|
CHECK_VALUE("rx sentinel", buf[11272], 0xa5);
|
| 747 |
|
|
|
| 748 |
|
|
printf("descriptor wrap [OK]\n");
|
| 749 |
|
|
|
| 750 |
|
|
/* test interrupts */
|
| 751 |
|
|
test_data_interrupt(SPWAMBA_CONTROL_IERXDESC);
|
| 752 |
|
|
test_data_interrupt(SPWAMBA_CONTROL_IETXDESC);
|
| 753 |
|
|
test_data_interrupt(SPWAMBA_CONTROL_IERXPACKET);
|
| 754 |
|
|
test_data_interrupt(SPWAMBA_CONTROL_IERXDESC | SPWAMBA_CONTROL_IETXDESC | SPWAMBA_CONTROL_IERXPACKET);
|
| 755 |
|
|
|
| 756 |
|
|
printf("data interrupts [OK]\n");
|
| 757 |
|
|
|
| 758 |
|
|
/* start RX dma */
|
| 759 |
|
|
rxdesctable[0].f = 0x10400; /* EN, 1024 bytes */
|
| 760 |
|
|
rxdesctable[0].d = buf + 8192;
|
| 761 |
|
|
rxdesctable[1].f = 0;
|
| 762 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)rxdesctable);
|
| 763 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA);
|
| 764 |
|
|
|
| 765 |
|
|
/* transmit partial packets and check txdesc flag */
|
| 766 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)txdesctable);
|
| 767 |
|
|
for (i = 0; i < 8; i++) {
|
| 768 |
|
|
txdesctable[i].f = (0x10000 | (i < 4 ? 0x40000 : 0)) + i + 1;
|
| 769 |
|
|
txdesctable[i].d = buf + 4 * i;
|
| 770 |
|
|
txdesctable[i+1].f = 0;
|
| 771 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 772 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 773 |
|
|
for (j = 0; j < 200 && (v & 0x80) != 0; j++)
|
| 774 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 775 |
|
|
CHECK_CONDITION("reg_status", v, (v & 0x3fff) == (0x43 | (i < 4 ? 0x1000 : 0)));
|
| 776 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 777 |
|
|
CHECK_VALUE("txdesctable", txdesctable[i].f, 0x80000 | (i < 4 ? 0x40000 : 0));
|
| 778 |
|
|
}
|
| 779 |
|
|
|
| 780 |
|
|
/* transmit a series of partial packets at once */
|
| 781 |
|
|
for (i = 8; i < 16; i++) {
|
| 782 |
|
|
txdesctable[i].f = 0x10000 + i + 1;
|
| 783 |
|
|
txdesctable[i].d = buf + 4 * i;
|
| 784 |
|
|
}
|
| 785 |
|
|
txdesctable[16].f = 0;
|
| 786 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 787 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 788 |
|
|
for (i = 0; i < 1200 && (v & 0x80) != 0; i++)
|
| 789 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 790 |
|
|
CHECK_VALUE("reg_status", v, 0x0043);
|
| 791 |
|
|
for (i = 8; i < 16; i++)
|
| 792 |
|
|
CHECK_VALUE("txdesctable", txdesctable[i].f, 0x80000);
|
| 793 |
|
|
|
| 794 |
|
|
/* transmit just an EOP character */
|
| 795 |
|
|
txdesctable[16].f = 0x110000; /* EOP, EN, 0 bytes */
|
| 796 |
|
|
txdesctable[16].d = (unsigned char *)0xc0000000; /* invalid pointer */
|
| 797 |
|
|
txdesctable[17].f = 0;
|
| 798 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 799 |
|
|
|
| 800 |
|
|
/* wait until packet received */
|
| 801 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 802 |
|
|
for (i = 0; i < 1200 && (v & 0x2000) == 0; i++)
|
| 803 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 804 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 805 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 806 |
|
|
CHECK_VALUE("txdesctable[16].f", txdesctable[16].f, 0x180000);
|
| 807 |
|
|
CHECK_VALUE("rxdesctable[0].f", rxdesctable[0].f, 0x180088);
|
| 808 |
|
|
|
| 809 |
|
|
/* check received data */
|
| 810 |
|
|
k = 0;
|
| 811 |
|
|
for (i = 0; i < 16; i++) {
|
| 812 |
|
|
for (j = 0; j < i + 1; j++) {
|
| 813 |
|
|
CHECK_VALUE("rxdata", buf[8192+k], buf[4*i+j]);
|
| 814 |
|
|
k++;
|
| 815 |
|
|
}
|
| 816 |
|
|
}
|
| 817 |
|
|
|
| 818 |
|
|
printf("send partial packets [OK]\n");
|
| 819 |
|
|
|
| 820 |
|
|
/* set up descriptors for packets with different sizes */
|
| 821 |
|
|
for (i = 0; i < 8; i++) {
|
| 822 |
|
|
txdesctable[i].f = 0x110000 + i + 1;
|
| 823 |
|
|
txdesctable[i].d = buf + 4 * i;
|
| 824 |
|
|
}
|
| 825 |
|
|
/* tx packets of size 28 .. 35 */
|
| 826 |
|
|
for (i = 8; i < 16; i++) {
|
| 827 |
|
|
txdesctable[i].f = 0x110000 + i + 20;
|
| 828 |
|
|
txdesctable[i].d = buf + 4 * i;
|
| 829 |
|
|
}
|
| 830 |
|
|
txdesctable[16].f = 0;
|
| 831 |
|
|
/* initially set up just 12 rx frames */
|
| 832 |
|
|
for (i = 0; i < 12; i++) {
|
| 833 |
|
|
rxdesctable[i].f = 0x10020; /* max 32 bytes */
|
| 834 |
|
|
rxdesctable[i].d = buf + 8192 + 36 * i;
|
| 835 |
|
|
}
|
| 836 |
|
|
rxdesctable[12].f = 0;
|
| 837 |
|
|
|
| 838 |
|
|
/* start transfer and wait until rx complete */
|
| 839 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)rxdesctable);
|
| 840 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)txdesctable);
|
| 841 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA | SPWAMBA_CONTROL_TXDMA);
|
| 842 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 843 |
|
|
for (i = 0; i < 2400 && (v & 0x40) != 0; i++ )
|
| 844 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 845 |
|
|
CHECK_CONDITION("reg_status", v, (v & 0x3f7f) == 0x2003);
|
| 846 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 847 |
|
|
|
| 848 |
|
|
/* the next rx frame will have no EOP,
|
| 849 |
|
|
so it should trigger rxdesc but not rxpacket */
|
| 850 |
|
|
rxdesctable[12].f = 0x50020;
|
| 851 |
|
|
rxdesctable[12].d = buf + 8192 + 36 * 12;
|
| 852 |
|
|
rxdesctable[13].f = 0;
|
| 853 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA);
|
| 854 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 855 |
|
|
for (i = 0; i < 2400 && (v & 0x40) != 0; i++ )
|
| 856 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 857 |
|
|
CHECK_CONDITION("reg_status", v, (v & 0xff7f) == 0x0803);
|
| 858 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 859 |
|
|
|
| 860 |
|
|
/* do remaining RX frames; all packets are split over 2 rx frames */
|
| 861 |
|
|
for (i = 13; i < 20; i++) {
|
| 862 |
|
|
rxdesctable[i].f = 0x10020; /* max 32 bytes */
|
| 863 |
|
|
rxdesctable[i].d = buf + 8192 + 36 * i;
|
| 864 |
|
|
}
|
| 865 |
|
|
rxdesctable[19].f = 0x50020; /* IE on last descriptor */
|
| 866 |
|
|
rxdesctable[20].f = 0;
|
| 867 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA);
|
| 868 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 869 |
|
|
for (i = 0; i < 2400 && (v & 0x0800) == 0; i++ )
|
| 870 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 871 |
|
|
CHECK_VALUE("reg_status", v, 0x6843);
|
| 872 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 873 |
|
|
|
| 874 |
|
|
/* check completed descriptors */
|
| 875 |
|
|
for (i = 0; i < 16; i++)
|
| 876 |
|
|
CHECK_VALUE("txdesctable", txdesctable[i].f, 0x180000);
|
| 877 |
|
|
for (i = 0; i < 8; i++)
|
| 878 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[i].f, 0x180000 + i + 1);
|
| 879 |
|
|
for (i = 8; i < 12; i++)
|
| 880 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[i].f, 0x180000 + i + 20);
|
| 881 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[12].f, 0x0c0020);
|
| 882 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[13].f, 0x180000);
|
| 883 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[14].f, 0x080020);
|
| 884 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[15].f, 0x180001);
|
| 885 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[16].f, 0x080020);
|
| 886 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[17].f, 0x180002);
|
| 887 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[18].f, 0x080020);
|
| 888 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[19].f, 0x1c0003);
|
| 889 |
|
|
|
| 890 |
|
|
/* check received data */
|
| 891 |
|
|
for (i = 0; i < 8; i++)
|
| 892 |
|
|
for (j = 0; j < i + 1; j++)
|
| 893 |
|
|
CHECK_VALUE("rxdata", buf[8192+36*i+j], buf[4*i+j]);
|
| 894 |
|
|
k = 8;
|
| 895 |
|
|
for (i = 8; i < 16; i++) {
|
| 896 |
|
|
for (j = 0; j < i + 20; j++) {
|
| 897 |
|
|
CHECK_VALUE("rxdata", buf[8192+36*k+j%32], buf[4*i+j]);
|
| 898 |
|
|
if (j == 31) k++;
|
| 899 |
|
|
}
|
| 900 |
|
|
k++;
|
| 901 |
|
|
}
|
| 902 |
|
|
|
| 903 |
|
|
printf("several packet lengths [OK]\n");
|
| 904 |
|
|
|
| 905 |
|
|
/* set up 8 rx and tx descriptors for EEP packets */
|
| 906 |
|
|
for (i = 0; i < 8; i++) {
|
| 907 |
|
|
txdesctable[i].f = 0x210000 + i + 1;
|
| 908 |
|
|
txdesctable[i].d = buf + 12 * i;
|
| 909 |
|
|
rxdesctable[i].f = 0x010400 | (i == 7 ? 0x40000 : 0);
|
| 910 |
|
|
rxdesctable[i].d = buf + 8192 + 12 * i;
|
| 911 |
|
|
}
|
| 912 |
|
|
txdesctable[8].f = 0;
|
| 913 |
|
|
rxdesctable[8].f = 0;
|
| 914 |
|
|
|
| 915 |
|
|
/* start DMA, wait until last frame received */
|
| 916 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)rxdesctable);
|
| 917 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)txdesctable);
|
| 918 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA | SPWAMBA_CONTROL_TXDMA);
|
| 919 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 920 |
|
|
for (i = 0; i < 1200 && (v & 0x0800) == 0; i++)
|
| 921 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 922 |
|
|
CHECK_VALUE("reg_status", v, 0x6843);
|
| 923 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 924 |
|
|
|
| 925 |
|
|
/* check completed descriptors and received data*/
|
| 926 |
|
|
for (i = 0; i < 8; i++) {
|
| 927 |
|
|
CHECK_VALUE("txdesctable", txdesctable[i].f, 0x280000);
|
| 928 |
|
|
CHECK_VALUE("rxdesctable", rxdesctable[i].f, (0x280000 | (i == 7 ? 0x40000 : 0)) + i + 1);
|
| 929 |
|
|
for (j = 0; j < i + 1; j++)
|
| 930 |
|
|
CHECK_VALUE("rxdata", buf[8192+12*i+j], buf[12*i+j]);
|
| 931 |
|
|
for (j = i + 1; ; j++) {
|
| 932 |
|
|
CHECK_VALUE("rxeep", buf[8192+12*i+j], 0x01);
|
| 933 |
|
|
if ((j & 3) == 3)
|
| 934 |
|
|
break;
|
| 935 |
|
|
}
|
| 936 |
|
|
}
|
| 937 |
|
|
|
| 938 |
|
|
printf("transfer EEP packets [OK]\n");
|
| 939 |
|
|
|
| 940 |
|
|
/* send so much data that the RX and TX queues fill up */
|
| 941 |
|
|
txdesctable[0].f = 0x150000 + QUEUEFILL; /* EOP, EN, IE, QUEUEFILL bytes */
|
| 942 |
|
|
txdesctable[0].d = buf;
|
| 943 |
|
|
txdesctable[1].f = 0x150000 + QUEUEFILL; /* EOP, EN, IE, QUEUEFILL bytes */
|
| 944 |
|
|
txdesctable[1].d = buf + 40;
|
| 945 |
|
|
txdesctable[2].f = 0;
|
| 946 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)txdesctable);
|
| 947 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 948 |
|
|
|
| 949 |
|
|
/* wait until first packet transmitted */
|
| 950 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 951 |
|
|
for (i = 0; i < 12000 && (v & 0x1000) == 0; i++)
|
| 952 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 953 |
|
|
/* wait a little longer to make sure the flow is blocked */
|
| 954 |
|
|
for (i = 0; i < 1200; i++)
|
| 955 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 956 |
|
|
CHECK_VALUE("reg_status", v, 0x1083);
|
| 957 |
|
|
|
| 958 |
|
|
/* start RX dma */
|
| 959 |
|
|
rxdesctable[0].f = 0x010800; /* EN, 2048 bytes */
|
| 960 |
|
|
rxdesctable[0].d = buf + 8192;
|
| 961 |
|
|
rxdesctable[1].f = 0x050800; /* EN, IE, 2048 bytes */
|
| 962 |
|
|
rxdesctable[1].d = buf + 8192 + 2048;
|
| 963 |
|
|
rxdesctable[2].f = 0;
|
| 964 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)rxdesctable);
|
| 965 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA);
|
| 966 |
|
|
|
| 967 |
|
|
/* wait until second packet received */
|
| 968 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 969 |
|
|
for (i = 0; i < 12000 && (v & 0x800) == 0; i++)
|
| 970 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 971 |
|
|
CHECK_VALUE("reg_status", v, 0x7843);
|
| 972 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 973 |
|
|
|
| 974 |
|
|
/* check completed descriptors */
|
| 975 |
|
|
CHECK_VALUE("txdesctable[0].f", txdesctable[0].f, 0x1c0000);
|
| 976 |
|
|
CHECK_VALUE("txdesctable[1].f", txdesctable[1].f, 0x1c0000);
|
| 977 |
|
|
CHECK_VALUE("rxdesctable[0].f", rxdesctable[0].f, 0x180000 + QUEUEFILL);
|
| 978 |
|
|
CHECK_VALUE("rxdesctable[1].f", rxdesctable[1].f, 0x1c0000 + QUEUEFILL);
|
| 979 |
|
|
|
| 980 |
|
|
/* check received data */
|
| 981 |
|
|
for (i = 0; i < QUEUEFILL / 4; i++)
|
| 982 |
|
|
CHECK_VALUE("rxdata", ((unsigned int *)buf)[2048+i], ((unsigned int *)buf)[i]);
|
| 983 |
|
|
for (i = 0; i < QUEUEFILL / 4; i++)
|
| 984 |
|
|
CHECK_VALUE("rxdata", ((unsigned int *)buf)[2048+512+i], ((unsigned int *)buf)[10+i]);
|
| 985 |
|
|
CHECK_VALUE("rxeop", ((unsigned int *)buf)[2048+512+QUEUEFILL/4], 0);
|
| 986 |
|
|
|
| 987 |
|
|
printf("handle full TX queue [OK]\n");
|
| 988 |
|
|
|
| 989 |
|
|
/* start tx dma */
|
| 990 |
|
|
txdesctable[0].f = 0x050200; /* EN, IE, 512 bytes */
|
| 991 |
|
|
txdesctable[0].d = buf;
|
| 992 |
|
|
txdesctable[1].f = 0x150100; /* EOP, EN, IE, 256 bytes */
|
| 993 |
|
|
txdesctable[1].d = buf + 512;
|
| 994 |
|
|
txdesctable[2].f = 0;
|
| 995 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)txdesctable);
|
| 996 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 997 |
|
|
|
| 998 |
|
|
/* wait until first packet sent, then cancel tx dma */
|
| 999 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1000 |
|
|
for (i = 0; i < 1600 && (v & 0x1000) == 0; i++)
|
| 1001 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1002 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXCANCEL);
|
| 1003 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1004 |
|
|
CHECK_VALUE("reg_status", v, 0x1003);
|
| 1005 |
|
|
CHECK_VALUE("txdesctable[0].f", txdesctable[0].f, 0x0c0000);
|
| 1006 |
|
|
CHECK_VALUE("txdesctable[1].f", txdesctable[1].f, 0x150100);
|
| 1007 |
|
|
|
| 1008 |
|
|
/* send EEP to flush the partial packet */
|
| 1009 |
|
|
txdesctable[1].f = 0x250000;
|
| 1010 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 1011 |
|
|
|
| 1012 |
|
|
/* start rx dma */
|
| 1013 |
|
|
rxdesctable[0].f = 0x010400; /* EN, max 1024 bytes */
|
| 1014 |
|
|
rxdesctable[0].d = buf + 8192;
|
| 1015 |
|
|
rxdesctable[1].f = 0;
|
| 1016 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)rxdesctable);
|
| 1017 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RXDMA);
|
| 1018 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1019 |
|
|
for (i = 0; i < 1600 && (v & 0x2000) == 0; i++)
|
| 1020 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1021 |
|
|
CHECK_VALUE("reg_status", v, 0x7043);
|
| 1022 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1023 |
|
|
CHECK_VALUE("txdesctable[1].f", txdesctable[1].f, 0x2c0000);
|
| 1024 |
|
|
CHECK_CONDITION("rxdesctable[0].f", rxdesctable[0].f, (rxdesctable[0].f & 0xfffff000) == 0x280000);
|
| 1025 |
|
|
|
| 1026 |
|
|
printf("cancel TX dma [OK]\n");
|
| 1027 |
|
|
|
| 1028 |
|
|
/* start tx dma from invalid address */
|
| 1029 |
|
|
txdesctable[2].f = 0x110010; /* EOP, EN, 16 bytes */
|
| 1030 |
|
|
txdesctable[2].d = (unsigned char *)0xc0000000; /* invalid pointer */
|
| 1031 |
|
|
txdesctable[3].f = 0;
|
| 1032 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 1033 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1034 |
|
|
for (i = 0; i < 200 && (v & 0x80) != 0; i++)
|
| 1035 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1036 |
|
|
|
| 1037 |
|
|
/* check ahberror flag */
|
| 1038 |
|
|
CHECK_VALUE("reg_status", v, 0x4103);
|
| 1039 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1040 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1041 |
|
|
CHECK_VALUE("reg_status", v, 0x4103);
|
| 1042 |
|
|
|
| 1043 |
|
|
/* reset DMA */
|
| 1044 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RESETDMA);
|
| 1045 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1046 |
|
|
CHECK_VALUE("reg_status", v, 0x4003);
|
| 1047 |
|
|
|
| 1048 |
|
|
printf("AHB error and dma reset [OK]\n");
|
| 1049 |
|
|
|
| 1050 |
|
|
/* note: link still up */
|
| 1051 |
|
|
}
|
| 1052 |
|
|
|
| 1053 |
|
|
|
| 1054 |
|
|
/* Test handling of link loss during data transfer */
|
| 1055 |
|
|
static void test_linkloss(void)
|
| 1056 |
|
|
{
|
| 1057 |
|
|
unsigned int i, v;
|
| 1058 |
|
|
|
| 1059 |
|
|
/* note: link still up */
|
| 1060 |
|
|
|
| 1061 |
|
|
/* transfer one packet; wait until received */
|
| 1062 |
|
|
txdesctable[0].f = 0x00110014; /* EOP, EN, 20 bytes */
|
| 1063 |
|
|
txdesctable[0].d = buf + 4;
|
| 1064 |
|
|
txdesctable[1].f = 0;
|
| 1065 |
|
|
rxdesctable[0].f = 0x00010400; /* EN, 1024 bytes */
|
| 1066 |
|
|
rxdesctable[0].d = buf + 8192;
|
| 1067 |
|
|
rxdesctable[1].f = 0;
|
| 1068 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)rxdesctable);
|
| 1069 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)txdesctable);
|
| 1070 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA | SPWAMBA_CONTROL_RXDMA);
|
| 1071 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1072 |
|
|
for (i = 0; i < 400 && (v & 0x2000) == 0; i++)
|
| 1073 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1074 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 1075 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1076 |
|
|
CHECK_VALUE("txdesctable[0].f", txdesctable[0].f, 0x00180000);
|
| 1077 |
|
|
CHECK_VALUE("rxdesctable[0].f", rxdesctable[0].f, 0x00180014);
|
| 1078 |
|
|
|
| 1079 |
|
|
/* verify received data */
|
| 1080 |
|
|
for (i = 0; i < 20; i++)
|
| 1081 |
|
|
CHECK_VALUE("rxdata", buf[8192+i], buf[4+i]);
|
| 1082 |
|
|
|
| 1083 |
|
|
#if LOOPBACKSWITCH
|
| 1084 |
|
|
/* unplug link */
|
| 1085 |
|
|
console[2] &= ~LEON_REG_UART_CTRL_RE;
|
| 1086 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1087 |
|
|
for (i = 0; i < 40 && (v & 3) == 3; i++)
|
| 1088 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1089 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1090 |
|
|
|
| 1091 |
|
|
/* check receive buffer still empty */
|
| 1092 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1093 |
|
|
CHECK_VALUE("reg_status", v, 0x4040);
|
| 1094 |
|
|
|
| 1095 |
|
|
/* replug link */
|
| 1096 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_START);
|
| 1097 |
|
|
console[2] |= LEON_REG_UART_CTRL_RE;
|
| 1098 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1099 |
|
|
for (i = 0; i < 250 && (v & 3) != 3; i++)
|
| 1100 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1101 |
|
|
|
| 1102 |
|
|
/* check receive buffer still empty */
|
| 1103 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1104 |
|
|
CHECK_VALUE("reg_status", v, 0x4043);
|
| 1105 |
|
|
|
| 1106 |
|
|
/* transfer one packet; wait until received */
|
| 1107 |
|
|
txdesctable[1].f = 0x00110014; /* EOP, EN, 20 bytes */
|
| 1108 |
|
|
txdesctable[1].d = buf + 24;
|
| 1109 |
|
|
txdesctable[2].f = 0;
|
| 1110 |
|
|
rxdesctable[1].f = 0x00010400; /* EN, 1024 bytes */
|
| 1111 |
|
|
rxdesctable[1].d = buf + 8192 + 20;
|
| 1112 |
|
|
rxdesctable[2].f = 0;
|
| 1113 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 1114 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1115 |
|
|
for (i = 0; i < 200 && (v & 0x2000) == 0; i++)
|
| 1116 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1117 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 1118 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1119 |
|
|
CHECK_VALUE("txdesctable[1].f", txdesctable[1].f, 0x00180000);
|
| 1120 |
|
|
CHECK_VALUE("rxdesctable[1].f", rxdesctable[1].f, 0x00180014);
|
| 1121 |
|
|
|
| 1122 |
|
|
/* verify received data */
|
| 1123 |
|
|
for (i = 0; i < 20; i++)
|
| 1124 |
|
|
CHECK_VALUE("rxdata", buf[8192+20+i], buf[24+i]);
|
| 1125 |
|
|
|
| 1126 |
|
|
/* transfer partial packet */
|
| 1127 |
|
|
txdesctable[2].f = 0x00050014; /* EN, IE, 20 bytes */
|
| 1128 |
|
|
txdesctable[2].d = buf;
|
| 1129 |
|
|
txdesctable[3].f = 0;
|
| 1130 |
|
|
rxdesctable[2].f = 0x00010400; /* EN, 1024 bytes */
|
| 1131 |
|
|
rxdesctable[2].d = buf + 8192;
|
| 1132 |
|
|
rxdesctable[3].f = 0;
|
| 1133 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 1134 |
|
|
|
| 1135 |
|
|
/* wait until partial packet transferred */
|
| 1136 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1137 |
|
|
for (i = 0; i < 200; i++)
|
| 1138 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1139 |
|
|
CHECK_VALUE("reg_status", v, 0x1043);
|
| 1140 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1141 |
|
|
CHECK_VALUE("txdesctable[2].f", txdesctable[2].f, 0x000c0000);
|
| 1142 |
|
|
|
| 1143 |
|
|
/* unplug link */
|
| 1144 |
|
|
console[2] &= ~LEON_REG_UART_CTRL_RE;
|
| 1145 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1146 |
|
|
for (i = 0; i < 40 && (v & 3) == 3; i++)
|
| 1147 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1148 |
|
|
CHECK_CONDITION("reg_status", v, (v & 0x1fe3) == 0x0040);
|
| 1149 |
|
|
|
| 1150 |
|
|
/* wait until EEP received */
|
| 1151 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1152 |
|
|
for (i = 0; i < 100 && (v & 0x2000) == 0; i++)
|
| 1153 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1154 |
|
|
CHECK_CONDITION("reg_status", v, (v & 0xffffffe0) == 0x6040);
|
| 1155 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1156 |
|
|
CHECK_VALUE("rxdesctable[2].f", rxdesctable[2].f, 0x00280014);
|
| 1157 |
|
|
|
| 1158 |
|
|
/* verify received data */
|
| 1159 |
|
|
for (i = 0; i < 20; i++)
|
| 1160 |
|
|
CHECK_VALUE("rxdata", buf[8192+i], buf[i]);
|
| 1161 |
|
|
CHECK_VALUE("rxeep", buf[8192+20], 0x01);
|
| 1162 |
|
|
|
| 1163 |
|
|
/* send one packet; should be discarded */
|
| 1164 |
|
|
txdesctable[3].f = 0x0015000a; /* EOP, IE, EN, 10 bytes */
|
| 1165 |
|
|
txdesctable[3].d = buf;
|
| 1166 |
|
|
txdesctable[4].f = 0;
|
| 1167 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA | SPWAMBA_CONTROL_START);
|
| 1168 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1169 |
|
|
for (i = 0; i < 200 && (v & 0x0800) == 0; i++)
|
| 1170 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1171 |
|
|
CHECK_CONDITION("reg_status", v, (v & 0xfffffffc) == 0x5040);
|
| 1172 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1173 |
|
|
CHECK_VALUE("txdesctable[3].f", txdesctable[3].f, 0x001c0000);
|
| 1174 |
|
|
|
| 1175 |
|
|
/* replug link */
|
| 1176 |
|
|
console[2] |= LEON_REG_UART_CTRL_RE;
|
| 1177 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1178 |
|
|
for (i = 0; i < 250 && (v & 3) != 3; i++)
|
| 1179 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1180 |
|
|
|
| 1181 |
|
|
/* check receive buffer still empty */
|
| 1182 |
|
|
for (i = 0; i < 200; i++)
|
| 1183 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1184 |
|
|
CHECK_VALUE("reg_status", v, 0x4043);
|
| 1185 |
|
|
|
| 1186 |
|
|
/* transfer one packet; wait until received */
|
| 1187 |
|
|
txdesctable[4].f = 0x0011000a; /* EOP, EN, 10 bytes */
|
| 1188 |
|
|
txdesctable[4].d = buf + 28;
|
| 1189 |
|
|
txdesctable[5].f = 0;
|
| 1190 |
|
|
rxdesctable[3].f = 0x00010400; /* EN, 1024 bytes */
|
| 1191 |
|
|
rxdesctable[3].d = buf + 8192;
|
| 1192 |
|
|
rxdesctable[4].f = 0;
|
| 1193 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 1194 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1195 |
|
|
for (i = 0; i < 400 && (v & 0x2000) == 0; i++)
|
| 1196 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1197 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 1198 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1199 |
|
|
CHECK_VALUE("txdesctable[4].f", txdesctable[4].f, 0x00180000);
|
| 1200 |
|
|
CHECK_VALUE("rxdesctable[3].f", rxdesctable[3].f, 0x0018000a);
|
| 1201 |
|
|
|
| 1202 |
|
|
/* verify received data */
|
| 1203 |
|
|
for (i = 0; i < 10; i++)
|
| 1204 |
|
|
CHECK_VALUE("rxdata", buf[8192+i], buf[28+i]);
|
| 1205 |
|
|
CHECK_VALUE("rxeop", buf[8192+10], 0x00);
|
| 1206 |
|
|
|
| 1207 |
|
|
printf("got EEP and txdiscard after link lost [OK]\n");
|
| 1208 |
|
|
|
| 1209 |
|
|
#else
|
| 1210 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, ((unsigned int)rxdesctable) + 4 * 8);
|
| 1211 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, ((unsigned int)txdesctable) + 5 * 8);
|
| 1212 |
|
|
#endif
|
| 1213 |
|
|
|
| 1214 |
|
|
/* transfer partial packet */
|
| 1215 |
|
|
txdesctable[5].f = 0x0001000a; /* EN, 10 bytes */
|
| 1216 |
|
|
txdesctable[5].d = buf + 32;
|
| 1217 |
|
|
txdesctable[6].f = 0;
|
| 1218 |
|
|
rxdesctable[4].f = 0x00010400; /* EN, 1024 bytes */
|
| 1219 |
|
|
rxdesctable[4].d = buf + 8192;
|
| 1220 |
|
|
rxdesctable[5].f = 0;
|
| 1221 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 1222 |
|
|
|
| 1223 |
|
|
/* wait until partial packet transferred */
|
| 1224 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1225 |
|
|
for (i = 0; i < 200; i++)
|
| 1226 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1227 |
|
|
CHECK_VALUE("reg_status", v, 0x0043);
|
| 1228 |
|
|
CHECK_VALUE("txdesctable[5].f", txdesctable[5].f, 0x00080000);
|
| 1229 |
|
|
|
| 1230 |
|
|
/* disable link */
|
| 1231 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_DISABLE);
|
| 1232 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1233 |
|
|
CHECK_CONDITION("reg_status", v, (v & 0xffff9fff) == 0x0040);
|
| 1234 |
|
|
|
| 1235 |
|
|
/* wait until EEP received */
|
| 1236 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1237 |
|
|
for (i = 0; i < 100 && (v & 0x2000) == 0; i++)
|
| 1238 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1239 |
|
|
CHECK_VALUE("reg_status", v, 0x6040);
|
| 1240 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1241 |
|
|
CHECK_VALUE("rxdesctable[4].f", rxdesctable[4].f, 0x0028000a);
|
| 1242 |
|
|
|
| 1243 |
|
|
/* verify received data */
|
| 1244 |
|
|
for (i = 0; i < 10; i++)
|
| 1245 |
|
|
CHECK_VALUE("rxdata", buf[8192+i], buf[i+32]);
|
| 1246 |
|
|
CHECK_VALUE("rxeep", buf[8192+10], 0x01);
|
| 1247 |
|
|
|
| 1248 |
|
|
/* send one packet; wait until packet in TX buf */
|
| 1249 |
|
|
txdesctable[6].f = 0x0011000a; /* EOP, EN, 10 bytes */
|
| 1250 |
|
|
txdesctable[6].d = buf + 36;
|
| 1251 |
|
|
txdesctable[7].f = 0;
|
| 1252 |
|
|
rxdesctable[5].f = 0x00010400; /* EN, 1024 bytes */
|
| 1253 |
|
|
rxdesctable[5].d = buf + 8192;
|
| 1254 |
|
|
rxdesctable[6].f = 0;
|
| 1255 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA);
|
| 1256 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1257 |
|
|
for (i = 0; i < 400 && (v & 0x80) != 0; i++)
|
| 1258 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1259 |
|
|
CHECK_VALUE("reg_status", v, 0x4040);
|
| 1260 |
|
|
CHECK_VALUE("txdesctable[6].f", txdesctable[6].f, 0x00180000);
|
| 1261 |
|
|
|
| 1262 |
|
|
/* reenable link */
|
| 1263 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_START);
|
| 1264 |
|
|
|
| 1265 |
|
|
/* wait until packet received */
|
| 1266 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1267 |
|
|
for (i = 0; i < 400 && (v & 0x2000) == 0; i++)
|
| 1268 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1269 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 1270 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1271 |
|
|
CHECK_VALUE("rxdesctable[5].f", rxdesctable[5].f, 0x0018000a);
|
| 1272 |
|
|
|
| 1273 |
|
|
/* verify received data */
|
| 1274 |
|
|
for (i = 0; i < 10; i++)
|
| 1275 |
|
|
CHECK_VALUE("rxdata", buf[8192+i], buf[36+i]);
|
| 1276 |
|
|
CHECK_VALUE("rxeop", buf[8192+10], 0x00);
|
| 1277 |
|
|
|
| 1278 |
|
|
printf("got EEP after link disabled [OK]\n");
|
| 1279 |
|
|
|
| 1280 |
|
|
/* reset DMA */
|
| 1281 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RESETDMA);
|
| 1282 |
|
|
|
| 1283 |
|
|
/* note: link still up */
|
| 1284 |
|
|
}
|
| 1285 |
|
|
|
| 1286 |
|
|
|
| 1287 |
|
|
/* Change TX bit rate and measure throughput */
|
| 1288 |
|
|
static void test_txrate(void)
|
| 1289 |
|
|
{
|
| 1290 |
|
|
unsigned int i, k, v;
|
| 1291 |
|
|
|
| 1292 |
|
|
/* note: link still up */
|
| 1293 |
|
|
|
| 1294 |
|
|
/* set up 2nd GPTIMER channel to count down microseconds */
|
| 1295 |
|
|
LEON3_GpTimer_Regs->e[1].rld = 0xffffffff;
|
| 1296 |
|
|
LEON3_GpTimer_Regs->e[1].ctrl = 0x05;
|
| 1297 |
|
|
|
| 1298 |
|
|
for (k = 0; k < 3; k++) {
|
| 1299 |
|
|
unsigned int nbyte, txfreq, usec;
|
| 1300 |
|
|
|
| 1301 |
|
|
switch (k) {
|
| 1302 |
|
|
case 1:
|
| 1303 |
|
|
nbyte = 500;
|
| 1304 |
|
|
txfreq = 5;
|
| 1305 |
|
|
break;
|
| 1306 |
|
|
case 2:
|
| 1307 |
|
|
nbyte = 2048;
|
| 1308 |
|
|
txfreq = TXCLKFREQ / 2;
|
| 1309 |
|
|
break;
|
| 1310 |
|
|
default:
|
| 1311 |
|
|
nbyte = 1000;
|
| 1312 |
|
|
txfreq = 10;
|
| 1313 |
|
|
break;
|
| 1314 |
|
|
}
|
| 1315 |
|
|
|
| 1316 |
|
|
/* switch TX bit rate to txfreq Mbit/s */
|
| 1317 |
|
|
spwamba_write(SPWAMBA_REG_TXSCALER, (TXCLKFREQ / txfreq) - 1);
|
| 1318 |
|
|
|
| 1319 |
|
|
/* setup packet of nbyte bytes */
|
| 1320 |
|
|
txdesctable[0].f = 0x00110000 + nbyte;
|
| 1321 |
|
|
txdesctable[0].d = buf;
|
| 1322 |
|
|
txdesctable[1].f = 0;
|
| 1323 |
|
|
rxdesctable[0].f = 0x00011000; /* EN, 4096 bytes */
|
| 1324 |
|
|
rxdesctable[0].d = buf + 8192;
|
| 1325 |
|
|
rxdesctable[1].f = 0;
|
| 1326 |
|
|
|
| 1327 |
|
|
/* transfer packet and wait until received */
|
| 1328 |
|
|
usec = LEON3_GpTimer_Regs->e[1].val;
|
| 1329 |
|
|
spwamba_write(SPWAMBA_REG_RXDMA, (unsigned int)rxdesctable);
|
| 1330 |
|
|
spwamba_write(SPWAMBA_REG_TXDMA, (unsigned int)txdesctable);
|
| 1331 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_TXDMA | SPWAMBA_CONTROL_RXDMA);
|
| 1332 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1333 |
|
|
for (i = 0; i < 8000 && (v & 0x2080) != 0x2000; i++)
|
| 1334 |
|
|
v = spwamba_read(SPWAMBA_REG_STATUS);
|
| 1335 |
|
|
|
| 1336 |
|
|
usec = usec - LEON3_GpTimer_Regs->e[1].val + 1;
|
| 1337 |
|
|
|
| 1338 |
|
|
CHECK_VALUE("reg_status", v, 0x6043);
|
| 1339 |
|
|
spwamba_write(SPWAMBA_REG_STATUS, v);
|
| 1340 |
|
|
CHECK_VALUE("txdesctable[0].f", txdesctable[0].f, 0x00180000);
|
| 1341 |
|
|
CHECK_VALUE("rxdesctable[0].f", rxdesctable[0].f, 0x00180000 + nbyte);
|
| 1342 |
|
|
|
| 1343 |
|
|
/* verify last 32 bytes */
|
| 1344 |
|
|
for (i = nbyte - 32; i < nbyte; i++)
|
| 1345 |
|
|
CHECK_VALUE("rxdata", buf[8192+i], buf[i]);
|
| 1346 |
|
|
CHECK_VALUE("rxeop", buf[8192+nbyte], 0x00);
|
| 1347 |
|
|
|
| 1348 |
|
|
printf("transfered %d bytes at %d Mbit/s in %d usec = %d.%03d MByte/s [OK]\n",
|
| 1349 |
|
|
nbyte, txfreq, usec, nbyte/usec, ((nbyte%usec)*1000)/usec);
|
| 1350 |
|
|
}
|
| 1351 |
|
|
|
| 1352 |
|
|
/* reset SPWAMBA */
|
| 1353 |
|
|
spwamba_write(SPWAMBA_REG_CONTROL, SPWAMBA_CONTROL_RESET);
|
| 1354 |
|
|
|
| 1355 |
|
|
/* disable GPTIMER channel */
|
| 1356 |
|
|
LEON3_GpTimer_Regs->e[1].ctrl = 0;
|
| 1357 |
|
|
}
|
| 1358 |
|
|
|
| 1359 |
|
|
|
| 1360 |
|
|
int main(void)
|
| 1361 |
|
|
{
|
| 1362 |
|
|
printf("-------- spwamba_test --------\n");
|
| 1363 |
|
|
|
| 1364 |
|
|
/* Workaround to force amba_init(). */
|
| 1365 |
|
|
{
|
| 1366 |
|
|
unsigned int *tcount, *treload, *tctrl;
|
| 1367 |
|
|
Timer_getTimer1(&tcount, &treload, &tctrl);
|
| 1368 |
|
|
}
|
| 1369 |
|
|
|
| 1370 |
|
|
/* Find SPWAMBA core on APB bus. */
|
| 1371 |
|
|
spwamba_start = amba_find_apbslv_addr(0x8, 0x131, &spwamba_irq);
|
| 1372 |
|
|
if ((spwamba_start & 0xf0000000) != 0x80000000) {
|
| 1373 |
|
|
printf("ERROR: SPWAMBA core not found on APB bus.\n");
|
| 1374 |
|
|
fail();
|
| 1375 |
|
|
return 1;
|
| 1376 |
|
|
}
|
| 1377 |
|
|
printf("Found SPWAMBA core at 0x%08lx, irq=%lu.\n", spwamba_start, spwamba_irq);
|
| 1378 |
|
|
|
| 1379 |
|
|
/* Install interrupt handler. */
|
| 1380 |
|
|
irq_expect = 0;
|
| 1381 |
|
|
catch_interrupt((int)spwamba_interrupt, spwamba_irq);
|
| 1382 |
|
|
leonbare_enable_irq(spwamba_irq);
|
| 1383 |
|
|
|
| 1384 |
|
|
/* Allocate RX and TX descriptor tables, suitably aligned */
|
| 1385 |
|
|
rxdesctable = malloc(3 * (1 << DESCTABLESIZE) * 8);
|
| 1386 |
|
|
rxdesctable = (struct descriptor_struct *)(((((unsigned int)rxdesctable) >> (DESCTABLESIZE + 3)) + 1) << (DESCTABLESIZE + 3));
|
| 1387 |
|
|
txdesctable = rxdesctable + (1 << DESCTABLESIZE);
|
| 1388 |
|
|
|
| 1389 |
|
|
/* Allocate 16 kByte buffer */
|
| 1390 |
|
|
buf = malloc(16384);
|
| 1391 |
|
|
|
| 1392 |
|
|
/* Enable spacewire link, disable external time tick */
|
| 1393 |
|
|
#if LOOPBACKSWITCH
|
| 1394 |
|
|
console[2] |= LEON_REG_UART_CTRL_RE; /* uart RXEN bit enables spacewire loopback */
|
| 1395 |
|
|
#endif
|
| 1396 |
|
|
LEON3_GpTimer_Regs->e[1].ctrl = 0; /* Timer2 generates tick_in pulses */
|
| 1397 |
|
|
|
| 1398 |
|
|
test_regs();
|
| 1399 |
|
|
test_link();
|
| 1400 |
|
|
test_timecode();
|
| 1401 |
|
|
create_test_data();
|
| 1402 |
|
|
test_data();
|
| 1403 |
|
|
test_linkloss();
|
| 1404 |
|
|
test_txrate();
|
| 1405 |
|
|
|
| 1406 |
|
|
check_test_data();
|
| 1407 |
|
|
|
| 1408 |
|
|
printf("-------- done --------\n");
|
| 1409 |
|
|
powerdown();
|
| 1410 |
|
|
|
| 1411 |
|
|
return 0;
|
| 1412 |
|
|
}
|
| 1413 |
|
|
|
