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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [db/] [spw_fifo_ulight.map.qmsg] - Blame information for rev 34

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Line No. Rev Author Line
1 32 redbear 
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1503624762167 ""}
2 
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1503624762189 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 24 22:32:41 2017 " "Processing started: Thu Aug 24 22:32:41 2017" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1503624762189 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624762189 ""}
3 
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624762190 ""}
4 
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1503624770883 ""}
5 
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1503624770884 ""}
6 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" { { "Info" "ISGN_ENTITY_NAME" "1 detector_tokens " "Found entity 1: detector_tokens" {  } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 33 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786652 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786652 ""}
7 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce_db " "Found entity 1: debounce_db" {  } { { "../../rtl/DEBUG_VERILOG/debounce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" 33 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786653 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786653 ""}
8 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_reduce " "Found entity 1: clock_reduce" {  } { { "../../rtl/DEBUG_VERILOG/clock_reduce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" 34 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786654 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786654 ""}
9 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_spw_ultra_light " "Found entity 1: top_spw_ultra_light" {  } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 36 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786655 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786655 ""}
10 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" { { "Info" "ISGN_ENTITY_NAME" "1 spw_ulight_con_top_x " "Found entity 1: spw_ulight_con_top_x" {  } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786656 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786656 ""}
11 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 RX_SPW " "Found entity 1: RX_SPW" {  } { { "../../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 36 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786658 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786658 ""}
12 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSM_SPW " "Found entity 1: FSM_SPW" {  } { { "../../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" 36 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786659 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786659 ""}
13 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_tx " "Found entity 1: fifo_tx" {  } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 33 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786660 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786660 ""}
14 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_rx " "Found entity 1: fifo_rx" {  } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 33 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786661 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786661 ""}
15 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 TX_SPW " "Found entity 1: TX_SPW" {  } { { "../../rtl/RTL_VB/tx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" 36 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786663 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786663 ""}
16 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/ulight_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo " "Found entity 1: ulight_fifo" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786666 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786666 ""}
17 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" {  } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786667 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786667 ""}
18 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" {  } { { "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786668 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786668 ""}
19 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0 " "Found entity 1: ulight_fifo_mm_interconnect_0" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786692 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786692 ""}
20 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786693 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786693 ""}
21 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786693 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786693 ""}
22 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_mux" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786696 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786696 ""}
23 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786697 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786697 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786697 ""}
24 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_demux" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786698 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786698 ""}
25 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_mux" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786699 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786699 ""}
26 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_demux" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786700 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786700 ""}
27 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786701 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786701 ""}
28 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786702 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786702 ""}
29 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786705 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786705 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786705 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786705 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786705 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786705 ""}
30 
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503624786709 ""}
31 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786710 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786710 ""}
32 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" {  } { { "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786711 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786711 ""}
33 
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" {  } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503624786712 ""}
34 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" {  } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786713 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786713 ""}
35 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" {  } { { "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786714 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786714 ""}
36 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786715 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786715 ""}
37 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" {  } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786716 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786716 ""}
38 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" {  } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786717 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786717 ""}
39 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786721 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786721 ""}
40 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786722 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 185 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786722 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786722 ""}
41 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" {  } { { "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786724 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786724 ""}
42 
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503624786725 ""}
43 
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503624786725 ""}
44 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_002_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_002_default_decode" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786725 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router_002 " "Found entity 2: ulight_fifo_mm_interconnect_0_router_002" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786725 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786725 ""}
45 
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503624786726 ""}
46 
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503624786726 ""}
47 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_default_decode" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786727 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router " "Found entity 2: ulight_fifo_mm_interconnect_0_router" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786727 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786727 ""}
48 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786729 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786729 ""}
49 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786730 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786730 ""}
50 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_axi_master_ni " "Found entity 1: altera_merlin_axi_master_ni" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 27 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786732 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786732 ""}
51 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786734 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786734 ""}
52 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_write_data_fifo_tx " "Found entity 1: ulight_fifo_write_data_fifo_tx" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786735 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786735 ""}
53 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_tx_data " "Found entity 1: ulight_fifo_timecode_tx_data" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786736 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786736 ""}
54 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_rx " "Found entity 1: ulight_fifo_timecode_rx" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786737 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786737 ""}
55 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_pll_0 " "Found entity 1: ulight_fifo_pll_0" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786737 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786737 ""}
56 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_led_pio_test " "Found entity 1: ulight_fifo_led_pio_test" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786738 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786738 ""}
57 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0 " "Found entity 1: ulight_fifo_hps_0" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786739 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786739 ""}
58 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io " "Found entity 1: ulight_fifo_hps_0_hps_io" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786740 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786740 ""}
59 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram " "Found entity 1: hps_sdram" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786743 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786743 ""}
60 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_pll " "Found entity 1: hps_sdram_pll" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786745 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786745 ""}
61 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_clock_pair_generator " "Found entity 1: hps_sdram_p0_clock_pair_generator" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786930 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786930 ""}
62 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_addr_cmd_pads " "Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786931 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786931 ""}
63 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_memphy " "Found entity 1: hps_sdram_p0_acv_hard_memphy" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786933 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786933 ""}
64 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_ldc " "Found entity 1: hps_sdram_p0_acv_ldc" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786934 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786934 ""}
65 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_io_pads " "Found entity 1: hps_sdram_p0_acv_hard_io_pads" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786935 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786935 ""}
66 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_generic_ddio " "Found entity 1: hps_sdram_p0_generic_ddio" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786936 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786936 ""}
67 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset " "Found entity 1: hps_sdram_p0_reset" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786937 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786937 ""}
68 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset_sync " "Found entity 1: hps_sdram_p0_reset_sync" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786938 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786938 ""}
69 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_phy_csr " "Found entity 1: hps_sdram_p0_phy_csr" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" 31 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786939 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786939 ""}
70 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_iss_probe " "Found entity 1: hps_sdram_p0_iss_probe" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786940 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786940 ""}
71 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0 " "Found entity 1: hps_sdram_p0" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786941 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786941 ""}
72 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_altdqdqs " "Found entity 1: hps_sdram_p0_altdqdqs" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786942 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786942 ""}
73 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altdq_dqs2_acv_connect_to_hard_phy_cyclonev " "Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev" {  } { { "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786948 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786948 ""}
74 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hhp_qseq_synth_top " "Found entity 1: altera_mem_if_hhp_qseq_synth_top" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" 15 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786950 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786950 ""}
75 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hard_memory_controller_top_cyclonev " "Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786957 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786957 ""}
76 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_oct_cyclonev " "Found entity 1: altera_mem_if_oct_cyclonev" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" 23 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786958 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786958 ""}
77 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_dll_cyclonev " "Found entity 1: altera_mem_if_dll_cyclonev" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" 23 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786959 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786959 ""}
78 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io_border " "Found entity 1: ulight_fifo_hps_0_hps_io_border" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 14 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786960 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786960 ""}
79 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_fpga_interfaces " "Found entity 1: ulight_fifo_hps_0_fpga_interfaces" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" 14 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786961 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786961 ""}
80 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_fifo_empty_rx_status " "Found entity 1: ulight_fifo_fifo_empty_rx_status" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786962 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786962 ""}
81 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_info " "Found entity 1: ulight_fifo_data_info" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786963 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786963 ""}
82 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_flag_rx " "Found entity 1: ulight_fifo_data_flag_rx" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786964 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786964 ""}
83 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_counter_rx_fifo " "Found entity 1: ulight_fifo_counter_rx_fifo" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786965 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786965 ""}
84 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_clock_sel " "Found entity 1: ulight_fifo_clock_sel" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786966 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786966 ""}
85 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_auto_start " "Found entity 1: ulight_fifo_auto_start" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786967 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786967 ""}
86 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_rtl/spw_fifo_ulight.v 1 1 " "Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPW_ULIGHT_FIFO " "Found entity 1: SPW_ULIGHT_FIFO" {  } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624786968 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624786968 ""}
87 
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "top_tx_ready_tick spw_fifo_ulight.v(96) " "Verilog HDL Implicit Net warning at spw_fifo_ulight.v(96): created implicit net for \"top_tx_ready_tick\"" {  } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 96 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624786968 ""}
88 
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for \"pll_dr_clk\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624786968 ""}
89 
{ "Info" "ISGN_START_ELABORATION_TOP" "SPW_ULIGHT_FIFO " "Elaborating entity \"SPW_ULIGHT_FIFO\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1503624787358 ""}
90 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[6\] spw_fifo_ulight.v(17) " "Output port \"LED\[6\]\" at spw_fifo_ulight.v(17) has no driver" {  } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624787365 "|SPW_ULIGHT_FIFO"}
91 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo ulight_fifo:u0 " "Elaborating entity \"ulight_fifo\" for hierarchy \"ulight_fifo:u0\"" {  } { { "top_rtl/spw_fifo_ulight.v" "u0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787368 ""}
92 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_auto_start ulight_fifo:u0\|ulight_fifo_auto_start:auto_start " "Elaborating entity \"ulight_fifo_auto_start\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_auto_start:auto_start\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "auto_start" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 174 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787465 ""}
93 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_clock_sel ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel " "Elaborating entity \"ulight_fifo_clock_sel\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "clock_sel" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 185 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787473 ""}
94 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_counter_rx_fifo ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo " "Elaborating entity \"ulight_fifo_counter_rx_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "counter_rx_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 193 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787478 ""}
95 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_flag_rx ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx " "Elaborating entity \"ulight_fifo_data_flag_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_flag_rx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 209 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787486 ""}
96 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_info ulight_fifo:u0\|ulight_fifo_data_info:data_info " "Elaborating entity \"ulight_fifo_data_info\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_info:data_info\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_info" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 217 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787493 ""}
97 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_fifo_empty_rx_status ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status " "Elaborating entity \"ulight_fifo_fifo_empty_rx_status\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "fifo_empty_rx_status" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 236 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787500 ""}
98 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0 " "Elaborating entity \"ulight_fifo_hps_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "hps_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 328 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787520 ""}
99 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_fpga_interfaces ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces " "Elaborating entity \"ulight_fifo_hps_0_fpga_interfaces\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "fpga_interfaces" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787534 ""}
100 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io " "Elaborating entity \"ulight_fifo_hps_0_hps_io\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "hps_io" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 153 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787686 ""}
101 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io_border ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border " "Elaborating entity \"ulight_fifo_hps_0_hps_io_border\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "border" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 45 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787695 ""}
102 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst " "Elaborating entity \"hps_sdram\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "hps_sdram_inst" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 84 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787701 ""}
103 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_pll ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll " "Elaborating entity \"hps_sdram_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "pll" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 105 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787744 ""}
104 
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object \"pll_dr_clk\" assigned a value but never read" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503624787745 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}
105 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "pll_locked hps_sdram_pll.sv(91) " "Output port \"pll_locked\" at hps_sdram_pll.sv(91) has no driver" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 91 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624787746 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}
106 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0 " "Elaborating entity \"hps_sdram_p0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "p0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 230 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787775 ""}
107 
{ "Info" "IVRFX_VERI_DISPLAY_SYSTEM_CALL_INFO" "Using Regular core emif simulation models hps_sdram_p0.sv(405) " "Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 405 0 0 } }  } 0 10648 "Verilog HDL Display System Task info at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624787777 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0"}
108 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_memphy ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy " "Elaborating entity \"hps_sdram_p0_acv_hard_memphy\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "umemphy" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 573 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787819 ""}
109 
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "reset_n_seq_clk hps_sdram_p0_acv_hard_memphy.v(420) " "Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1503624787823 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
110 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 hps_sdram_p0_acv_hard_memphy.v(557) " "Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1)" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 557 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503624787824 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
111 
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "reset_n_seq_clk 0 hps_sdram_p0_acv_hard_memphy.v(420) " "Net \"reset_n_seq_clk\" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0'" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1503624787830 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
112 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ctl_reset_export_n hps_sdram_p0_acv_hard_memphy.v(222) " "Output port \"ctl_reset_export_n\" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 222 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624787830 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
113 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_ldc ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc " "Elaborating entity \"hps_sdram_p0_acv_ldc\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "memphy_ldc" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 554 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624787970 ""}
114 
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dq hps_sdram_p0_acv_ldc.v(45) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object \"phy_clk_dq\" assigned a value but never read" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 45 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503624787970 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"}
115 
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dqs_2x hps_sdram_p0_acv_ldc.v(47) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object \"phy_clk_dqs_2x\" assigned a value but never read" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 47 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503624787970 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"}
116 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_io_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_io_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "uio_pads" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 780 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788015 ""}
117 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ddio_phy_dqdin\[179..32\] hps_sdram_p0_acv_hard_io_pads.v(191) " "Output port \"ddio_phy_dqdin\[179..32\]\" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 191 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624788023 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads"}
118 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_addr_cmd_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_addr_cmd_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "uaddr_cmd_pads" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 244 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788035 ""}
119 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "uaddress_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 157 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788120 ""}
120 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ubank_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 166 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788186 ""}
121 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ucmd_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 189 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788196 ""}
122 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ureset_n_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 198 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788213 ""}
123 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborating entity \"altddio_out\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].umem_ck_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788579 ""}
124 
{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788581 ""}
125 
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "extend_oe_disable UNUSED " "Parameter \"extend_oe_disable\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624788581 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624788581 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "invert_output OFF " "Parameter \"invert_output\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624788581 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624788581 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altddio_out " "Parameter \"lpm_type\" = \"altddio_out\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624788581 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "oe_reg UNUSED " "Parameter \"oe_reg\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624788581 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_high OFF " "Parameter \"power_up_high\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624788581 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 1 " "Parameter \"width\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624788581 ""}  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1503624788581 ""}
126 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ddio_out_uqe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ddio_out_uqe " "Found entity 1: ddio_out_uqe" {  } { { "db/ddio_out_uqe.tdf" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/ddio_out_uqe.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624788641 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624788641 ""}
127 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddio_out_uqe ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated " "Elaborating entity \"ddio_out_uqe\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated\"" {  } { { "altddio_out.tdf" "auto_generated" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altddio_out.tdf" 101 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788642 ""}
128 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_clock_pair_generator ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator " "Elaborating entity \"hps_sdram_p0_clock_pair_generator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].uclk_generator" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 337 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788647 ""}
129 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_altdqdqs ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs " "Elaborating entity \"hps_sdram_p0_altdqdqs\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "dq_ddio\[0\].ubidir_dq_dqs" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 317 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788656 ""}
130 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdq_dqs2_acv_connect_to_hard_phy_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst " "Elaborating entity \"altdq_dqs2_acv_connect_to_hard_phy_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "altdq_dqs2_inst" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 146 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624788667 ""}
131 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hhp_qseq_synth_top ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq " "Elaborating entity \"altera_mem_if_hhp_qseq_synth_top\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "seq" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 238 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789106 ""}
132 
{ "Warning" "WSGN_EMPTY_SHELL" "altera_mem_if_hhp_qseq_synth_top " "Entity \"altera_mem_if_hhp_qseq_synth_top\" contains only dangling pins" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "seq" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 238 0 0 } }  } 0 12158 "Entity \"%1!s!\" contains only dangling pins" 0 0 "Analysis & Synthesis" 0 -1 1503624789107 ""}
133 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hard_memory_controller_top_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0 " "Elaborating entity \"altera_mem_if_hard_memory_controller_top_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "c0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 794 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789114 ""}
134 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1)" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1166 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503624789151 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
135 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1)" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1167 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503624789151 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
136 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1)" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1168 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503624789151 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
137 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1)" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1169 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503624789151 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
138 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1)" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1170 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503624789151 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
139 
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1)" {  } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1171 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503624789152 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
140 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_oct_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct " "Elaborating entity \"altera_mem_if_oct_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "oct" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 802 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789620 ""}
141 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_dll_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll " "Elaborating entity \"altera_mem_if_dll_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll\"" {  } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "dll" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 814 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789645 ""}
142 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_led_pio_test ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test " "Elaborating entity \"ulight_fifo_led_pio_test\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "led_pio_test" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 339 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789653 ""}
143 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_pll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0 " "Elaborating entity \"ulight_fifo_pll_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "pll_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789661 ""}
144 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborating entity \"altera_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "altera_pll_i" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789687 ""}
145 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvds_clk altera_pll.v(320) " "Output port \"lvds_clk\" at altera_pll.v(320) has no driver" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 320 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624789689 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"}
146 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_pll.v(321) " "Output port \"loaden\" at altera_pll.v(321) has no driver" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 321 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624789689 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"}
147 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk_out altera_pll.v(322) " "Output port \"extclk_out\" at altera_pll.v(322) has no driver" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 322 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624789689 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"}
148 
{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "wire_to_nowhere_64 " "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"wire_to_nowhere_64\" into its bus" {  } {  } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "Analysis & Synthesis" 0 -1 1503624789689 ""}
149 
{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789689 ""}
150 
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "fractional_vco_multiplier false " "Parameter \"fractional_vco_multiplier\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "reference_clock_frequency 100.0 MHz " "Parameter \"reference_clock_frequency\" = \"100.0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_cout 32 " "Parameter \"pll_fractional_cout\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_dsm_out_sel 1st_order " "Parameter \"pll_dsm_out_sel\" = \"1st_order\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode direct " "Parameter \"operation_mode\" = \"direct\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_clocks 1 " "Parameter \"number_of_clocks\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency0 400.000000 MHz " "Parameter \"output_clock_frequency0\" = \"400.000000 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift0 0 ps " "Parameter \"phase_shift0\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle0 50 " "Parameter \"duty_cycle0\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency1 0 MHz " "Parameter \"output_clock_frequency1\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift1 0 ps " "Parameter \"phase_shift1\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle1 50 " "Parameter \"duty_cycle1\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency2 0 MHz " "Parameter \"output_clock_frequency2\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift2 0 ps " "Parameter \"phase_shift2\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle2 50 " "Parameter \"duty_cycle2\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency3 0 MHz " "Parameter \"output_clock_frequency3\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift3 0 ps " "Parameter \"phase_shift3\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle3 50 " "Parameter \"duty_cycle3\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency4 0 MHz " "Parameter \"output_clock_frequency4\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift4 0 ps " "Parameter \"phase_shift4\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle4 50 " "Parameter \"duty_cycle4\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency5 0 MHz " "Parameter \"output_clock_frequency5\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift5 0 ps " "Parameter \"phase_shift5\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle5 50 " "Parameter \"duty_cycle5\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency6 0 MHz " "Parameter \"output_clock_frequency6\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift6 0 ps " "Parameter \"phase_shift6\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle6 50 " "Parameter \"duty_cycle6\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency7 0 MHz " "Parameter \"output_clock_frequency7\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift7 0 ps " "Parameter \"phase_shift7\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle7 50 " "Parameter \"duty_cycle7\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency8 0 MHz " "Parameter \"output_clock_frequency8\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift8 0 ps " "Parameter \"phase_shift8\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle8 50 " "Parameter \"duty_cycle8\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency9 0 MHz " "Parameter \"output_clock_frequency9\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift9 0 ps " "Parameter \"phase_shift9\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle9 50 " "Parameter \"duty_cycle9\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency10 0 MHz " "Parameter \"output_clock_frequency10\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift10 0 ps " "Parameter \"phase_shift10\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle10 50 " "Parameter \"duty_cycle10\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency11 0 MHz " "Parameter \"output_clock_frequency11\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift11 0 ps " "Parameter \"phase_shift11\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle11 50 " "Parameter \"duty_cycle11\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency12 0 MHz " "Parameter \"output_clock_frequency12\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift12 0 ps " "Parameter \"phase_shift12\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle12 50 " "Parameter \"duty_cycle12\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency13 0 MHz " "Parameter \"output_clock_frequency13\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift13 0 ps " "Parameter \"phase_shift13\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle13 50 " "Parameter \"duty_cycle13\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency14 0 MHz " "Parameter \"output_clock_frequency14\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift14 0 ps " "Parameter \"phase_shift14\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle14 50 " "Parameter \"duty_cycle14\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency15 0 MHz " "Parameter \"output_clock_frequency15\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift15 0 ps " "Parameter \"phase_shift15\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle15 50 " "Parameter \"duty_cycle15\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency16 0 MHz " "Parameter \"output_clock_frequency16\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift16 0 ps " "Parameter \"phase_shift16\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle16 50 " "Parameter \"duty_cycle16\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency17 0 MHz " "Parameter \"output_clock_frequency17\" = \"0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift17 0 ps " "Parameter \"phase_shift17\" = \"0 ps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle17 50 " "Parameter \"duty_cycle17\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type Cyclone V " "Parameter \"pll_type\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_subtype General " "Parameter \"pll_subtype\" = \"General\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_hi_div 2 " "Parameter \"m_cnt_hi_div\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_lo_div 2 " "Parameter \"m_cnt_lo_div\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_hi_div 256 " "Parameter \"n_cnt_hi_div\" = \"256\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_lo_div 256 " "Parameter \"n_cnt_lo_div\" = \"256\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_bypass_en false " "Parameter \"m_cnt_bypass_en\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_bypass_en true " "Parameter \"n_cnt_bypass_en\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_odd_div_duty_en false " "Parameter \"m_cnt_odd_div_duty_en\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_odd_div_duty_en false " "Parameter \"n_cnt_odd_div_duty_en\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div0 256 " "Parameter \"c_cnt_hi_div0\" = \"256\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div0 256 " "Parameter \"c_cnt_lo_div0\" = \"256\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst0 1 " "Parameter \"c_cnt_prst0\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst0 0 " "Parameter \"c_cnt_ph_mux_prst0\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src0 ph_mux_clk " "Parameter \"c_cnt_in_src0\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en0 true " "Parameter \"c_cnt_bypass_en0\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en0 false " "Parameter \"c_cnt_odd_div_duty_en0\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div1 1 " "Parameter \"c_cnt_hi_div1\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div1 1 " "Parameter \"c_cnt_lo_div1\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst1 1 " "Parameter \"c_cnt_prst1\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst1 0 " "Parameter \"c_cnt_ph_mux_prst1\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src1 ph_mux_clk " "Parameter \"c_cnt_in_src1\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en1 true " "Parameter \"c_cnt_bypass_en1\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en1 false " "Parameter \"c_cnt_odd_div_duty_en1\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div2 1 " "Parameter \"c_cnt_hi_div2\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div2 1 " "Parameter \"c_cnt_lo_div2\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst2 1 " "Parameter \"c_cnt_prst2\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst2 0 " "Parameter \"c_cnt_ph_mux_prst2\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src2 ph_mux_clk " "Parameter \"c_cnt_in_src2\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en2 true " "Parameter \"c_cnt_bypass_en2\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en2 false " "Parameter \"c_cnt_odd_div_duty_en2\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div3 1 " "Parameter \"c_cnt_hi_div3\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div3 1 " "Parameter \"c_cnt_lo_div3\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst3 1 " "Parameter \"c_cnt_prst3\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst3 0 " "Parameter \"c_cnt_ph_mux_prst3\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src3 ph_mux_clk " "Parameter \"c_cnt_in_src3\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en3 true " "Parameter \"c_cnt_bypass_en3\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en3 false " "Parameter \"c_cnt_odd_div_duty_en3\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div4 1 " "Parameter \"c_cnt_hi_div4\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div4 1 " "Parameter \"c_cnt_lo_div4\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst4 1 " "Parameter \"c_cnt_prst4\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst4 0 " "Parameter \"c_cnt_ph_mux_prst4\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src4 ph_mux_clk " "Parameter \"c_cnt_in_src4\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en4 true " "Parameter \"c_cnt_bypass_en4\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en4 false " "Parameter \"c_cnt_odd_div_duty_en4\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div5 1 " "Parameter \"c_cnt_hi_div5\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div5 1 " "Parameter \"c_cnt_lo_div5\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst5 1 " "Parameter \"c_cnt_prst5\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst5 0 " "Parameter \"c_cnt_ph_mux_prst5\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src5 ph_mux_clk " "Parameter \"c_cnt_in_src5\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en5 true " "Parameter \"c_cnt_bypass_en5\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en5 false " "Parameter \"c_cnt_odd_div_duty_en5\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div6 1 " "Parameter \"c_cnt_hi_div6\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div6 1 " "Parameter \"c_cnt_lo_div6\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst6 1 " "Parameter \"c_cnt_prst6\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst6 0 " "Parameter \"c_cnt_ph_mux_prst6\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src6 ph_mux_clk " "Parameter \"c_cnt_in_src6\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en6 true " "Parameter \"c_cnt_bypass_en6\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en6 false " "Parameter \"c_cnt_odd_div_duty_en6\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div7 1 " "Parameter \"c_cnt_hi_div7\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div7 1 " "Parameter \"c_cnt_lo_div7\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst7 1 " "Parameter \"c_cnt_prst7\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst7 0 " "Parameter \"c_cnt_ph_mux_prst7\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src7 ph_mux_clk " "Parameter \"c_cnt_in_src7\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en7 true " "Parameter \"c_cnt_bypass_en7\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en7 false " "Parameter \"c_cnt_odd_div_duty_en7\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div8 1 " "Parameter \"c_cnt_hi_div8\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div8 1 " "Parameter \"c_cnt_lo_div8\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst8 1 " "Parameter \"c_cnt_prst8\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst8 0 " "Parameter \"c_cnt_ph_mux_prst8\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src8 ph_mux_clk " "Parameter \"c_cnt_in_src8\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en8 true " "Parameter \"c_cnt_bypass_en8\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en8 false " "Parameter \"c_cnt_odd_div_duty_en8\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div9 1 " "Parameter \"c_cnt_hi_div9\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div9 1 " "Parameter \"c_cnt_lo_div9\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst9 1 " "Parameter \"c_cnt_prst9\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst9 0 " "Parameter \"c_cnt_ph_mux_prst9\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src9 ph_mux_clk " "Parameter \"c_cnt_in_src9\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en9 true " "Parameter \"c_cnt_bypass_en9\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en9 false " "Parameter \"c_cnt_odd_div_duty_en9\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div10 1 " "Parameter \"c_cnt_hi_div10\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div10 1 " "Parameter \"c_cnt_lo_div10\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst10 1 " "Parameter \"c_cnt_prst10\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst10 0 " "Parameter \"c_cnt_ph_mux_prst10\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src10 ph_mux_clk " "Parameter \"c_cnt_in_src10\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en10 true " "Parameter \"c_cnt_bypass_en10\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en10 false " "Parameter \"c_cnt_odd_div_duty_en10\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div11 1 " "Parameter \"c_cnt_hi_div11\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div11 1 " "Parameter \"c_cnt_lo_div11\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst11 1 " "Parameter \"c_cnt_prst11\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst11 0 " "Parameter \"c_cnt_ph_mux_prst11\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src11 ph_mux_clk " "Parameter \"c_cnt_in_src11\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en11 true " "Parameter \"c_cnt_bypass_en11\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en11 false " "Parameter \"c_cnt_odd_div_duty_en11\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div12 1 " "Parameter \"c_cnt_hi_div12\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div12 1 " "Parameter \"c_cnt_lo_div12\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst12 1 " "Parameter \"c_cnt_prst12\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst12 0 " "Parameter \"c_cnt_ph_mux_prst12\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src12 ph_mux_clk " "Parameter \"c_cnt_in_src12\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en12 true " "Parameter \"c_cnt_bypass_en12\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en12 false " "Parameter \"c_cnt_odd_div_duty_en12\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div13 1 " "Parameter \"c_cnt_hi_div13\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div13 1 " "Parameter \"c_cnt_lo_div13\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst13 1 " "Parameter \"c_cnt_prst13\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst13 0 " "Parameter \"c_cnt_ph_mux_prst13\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src13 ph_mux_clk " "Parameter \"c_cnt_in_src13\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en13 true " "Parameter \"c_cnt_bypass_en13\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en13 false " "Parameter \"c_cnt_odd_div_duty_en13\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div14 1 " "Parameter \"c_cnt_hi_div14\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div14 1 " "Parameter \"c_cnt_lo_div14\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst14 1 " "Parameter \"c_cnt_prst14\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst14 0 " "Parameter \"c_cnt_ph_mux_prst14\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src14 ph_mux_clk " "Parameter \"c_cnt_in_src14\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en14 true " "Parameter \"c_cnt_bypass_en14\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en14 false " "Parameter \"c_cnt_odd_div_duty_en14\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div15 1 " "Parameter \"c_cnt_hi_div15\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div15 1 " "Parameter \"c_cnt_lo_div15\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst15 1 " "Parameter \"c_cnt_prst15\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst15 0 " "Parameter \"c_cnt_ph_mux_prst15\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src15 ph_mux_clk " "Parameter \"c_cnt_in_src15\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en15 true " "Parameter \"c_cnt_bypass_en15\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en15 false " "Parameter \"c_cnt_odd_div_duty_en15\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div16 1 " "Parameter \"c_cnt_hi_div16\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div16 1 " "Parameter \"c_cnt_lo_div16\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst16 1 " "Parameter \"c_cnt_prst16\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst16 0 " "Parameter \"c_cnt_ph_mux_prst16\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src16 ph_mux_clk " "Parameter \"c_cnt_in_src16\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en16 true " "Parameter \"c_cnt_bypass_en16\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en16 false " "Parameter \"c_cnt_odd_div_duty_en16\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div17 1 " "Parameter \"c_cnt_hi_div17\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div17 1 " "Parameter \"c_cnt_lo_div17\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst17 1 " "Parameter \"c_cnt_prst17\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst17 0 " "Parameter \"c_cnt_ph_mux_prst17\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src17 ph_mux_clk " "Parameter \"c_cnt_in_src17\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en17 true " "Parameter \"c_cnt_bypass_en17\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en17 false " "Parameter \"c_cnt_odd_div_duty_en17\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_vco_div 2 " "Parameter \"pll_vco_div\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_cp_current 30 " "Parameter \"pll_cp_current\" = \"30\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_bwctrl 2000 " "Parameter \"pll_bwctrl\" = \"2000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_output_clk_frequency 400.0 MHz " "Parameter \"pll_output_clk_frequency\" = \"400.0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_division 1 " "Parameter \"pll_fractional_division\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "mimic_fbclk_type none " "Parameter \"mimic_fbclk_type\" = \"none\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_1 glb " "Parameter \"pll_fbclk_mux_1\" = \"glb\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_2 m_cnt " "Parameter \"pll_fbclk_mux_2\" = \"m_cnt\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_m_cnt_in_src ph_mux_clk " "Parameter \"pll_m_cnt_in_src\" = \"ph_mux_clk\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_slf_rst false " "Parameter \"pll_slf_rst\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "refclk1_frequency 100.0 MHz " "Parameter \"refclk1_frequency\" = \"100.0 MHz\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_loss_sw_en true " "Parameter \"pll_clk_loss_sw_en\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_manu_clk_sw_en false " "Parameter \"pll_manu_clk_sw_en\" = \"false\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_auto_clk_sw_en true " "Parameter \"pll_auto_clk_sw_en\" = \"true\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clkin_1_src clk_1 " "Parameter \"pll_clkin_1_src\" = \"clk_1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_sw_dly 0 " "Parameter \"pll_clk_sw_dly\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624789690 ""}  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1503624789690 ""}
151 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dps_extra_kick ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst " "Elaborating entity \"dps_extra_kick\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\"" {  } { { "altera_pll.v" "dps_extra_inst" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 769 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789695 ""}
152 
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 769 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789696 ""}
153 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dprio_init ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst " "Elaborating entity \"dprio_init\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\"" {  } { { "altera_pll.v" "dprio_init_inst" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 784 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789697 ""}
154 
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 784 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789698 ""}
155 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\"" {  } { { "altera_pll.v" "lcell_cntsel_int_0" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1961 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789703 ""}
156 
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1961 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789703 ""}
157 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\"" {  } { { "altera_pll.v" "lcell_cntsel_int_1" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1972 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789705 ""}
158 
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1972 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789706 ""}
159 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\"" {  } { { "altera_pll.v" "lcell_cntsel_int_2" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1983 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789707 ""}
160 
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1983 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789707 ""}
161 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\"" {  } { { "altera_pll.v" "lcell_cntsel_int_3" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1994 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789709 ""}
162 
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1994 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789709 ""}
163 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\"" {  } { { "altera_pll.v" "lcell_cntsel_int_4" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2005 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789711 ""}
164 
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2005 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789711 ""}
165 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll " "Elaborating entity \"altera_cyclonev_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\"" {  } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789724 ""}
166 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk altera_cyclonev_pll.v(632) " "Output port \"extclk\" at altera_cyclonev_pll.v(632) has no driver" {  } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 632 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624789728 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
167 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "clkout\[0\] altera_cyclonev_pll.v(637) " "Output port \"clkout\[0\]\" at altera_cyclonev_pll.v(637) has no driver" {  } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 637 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624789728 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
168 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_cyclonev_pll.v(641) " "Output port \"loaden\" at altera_cyclonev_pll.v(641) has no driver" {  } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 641 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624789728 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
169 
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvdsclk altera_cyclonev_pll.v(642) " "Output port \"lvdsclk\" at altera_cyclonev_pll.v(642) has no driver" {  } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 642 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503624789728 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
170 
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789728 ""}
171 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll_base ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 " "Elaborating entity \"altera_cyclonev_pll_base\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\"" {  } { { "altera_cyclonev_pll.v" "fpll_0" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1153 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789730 ""}
172 
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" {  } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1153 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789733 ""}
173 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_rx ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx " "Elaborating entity \"ulight_fifo_timecode_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_rx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 385 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789738 ""}
174 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_tx_data ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data " "Elaborating entity \"ulight_fifo_timecode_tx_data\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_tx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 396 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789745 ""}
175 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_write_data_fifo_tx ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx " "Elaborating entity \"ulight_fifo_write_data_fifo_tx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "write_data_fifo_tx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 426 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789754 ""}
176 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "mm_interconnect_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 553 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624789761 ""}
177 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_translator" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 1962 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791043 ""}
178 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_axi_master_ni ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent " "Elaborating entity \"altera_merlin_axi_master_ni\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_agent" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3434 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791090 ""}
179 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 485 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791119 ""}
180 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3518 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791161 ""}
181 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 608 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791182 ""}
182 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rsp_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3559 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791199 ""}
183 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rdata_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3600 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791239 ""}
184 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7102 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791403 ""}
185 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 205 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791460 ""}
186 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router_002" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791469 ""}
187 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 181 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791479 ""}
188 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_wr_limiter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7520 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791536 ""}
189 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7620 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791569 ""}
190 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_13_1 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter_13_1\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_13_1.burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 181 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791582 ""}
191 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 778 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791640 ""}
192 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_burstwrap_increment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment " "Elaborating entity \"altera_merlin_burst_adapter_burstwrap_increment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_burstwrap_increment" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 979 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791654 ""}
193 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_min ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min " "Elaborating entity \"altera_merlin_burst_adapter_min\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_min" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 1004 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791662 ""}
194 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_subtractor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub " "Elaborating entity \"altera_merlin_burst_adapter_subtractor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "ab_sub" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 157 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791672 ""}
195 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract " "Elaborating entity \"altera_merlin_burst_adapter_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "subtract" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 88 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624791676 ""}
196 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_demux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8813 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792296 ""}
197 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_mux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8979 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792352 ""}
198 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 287 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792373 ""}
199 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792379 ""}
200 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_demux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9485 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792476 ""}
201 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_mux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10111 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792509 ""}
202 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 630 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792669 ""}
203 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" {  } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792769 ""}
204 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "avalon_st_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10283 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792783 ""}
205 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0\"" {  } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "error_adapter_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792789 ""}
206 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller ulight_fifo:u0\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\"" {  } { { "ulight_fifo/synthesis/ulight_fifo.v" "rst_controller" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 616 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792850 ""}
207 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" {  } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 208 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792858 ""}
208 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1\"" {  } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_req_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 220 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792863 ""}
209 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spw_ulight_con_top_x spw_ulight_con_top_x:A_SPW_TOP " "Elaborating entity \"spw_ulight_con_top_x\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\"" {  } { { "top_rtl/spw_fifo_ulight.v" "A_SPW_TOP" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 143 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792872 ""}
210 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "top_spw_ultra_light spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW " "Elaborating entity \"top_spw_ultra_light\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\"" {  } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "SPW" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 101 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792877 ""}
211 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSM_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM " "Elaborating entity \"FSM_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\"" {  } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "FSM" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 113 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792882 ""}
212 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX " "Elaborating entity \"RX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\"" {  } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "RX" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 135 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792895 ""}
213 
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "rx_spw.v(508) " "Verilog HDL Case Statement information at rx_spw.v(508): all case item expressions in this case statement are onehot" {  } { { "../../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 508 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1503624792898 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX"}
214 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX " "Elaborating entity \"TX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\"" {  } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "TX" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 158 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792914 ""}
215 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_rx spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data " "Elaborating entity \"fifo_rx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\"" {  } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "rx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 116 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792954 ""}
216 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_tx spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data " "Elaborating entity \"fifo_tx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\"" {  } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "tx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 130 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792966 ""}
217 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debounce_db debounce_db:db_system_spwulight_b " "Elaborating entity \"debounce_db\" for hierarchy \"debounce_db:db_system_spwulight_b\"" {  } { { "top_rtl/spw_fifo_ulight.v" "db_system_spwulight_b" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 150 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792977 ""}
218 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_reduce clock_reduce:R_400_to_2_5_10_100_200_300MHZ " "Elaborating entity \"clock_reduce\" for hierarchy \"clock_reduce:R_400_to_2_5_10_100_200_300MHZ\"" {  } { { "top_rtl/spw_fifo_ulight.v" "R_400_to_2_5_10_100_200_300MHZ" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 158 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792982 ""}
219 
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "detector_tokens detector_tokens:m_x " "Elaborating entity \"detector_tokens\" for hierarchy \"detector_tokens:m_x\"" {  } { { "top_rtl/spw_fifo_ulight.v" "m_x" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 165 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624792994 ""}
220 
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "bit_c_ex detector_tokens.v(62) " "Verilog HDL or VHDL warning at detector_tokens.v(62): object \"bit_c_ex\" assigned a value but never read" {  } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 62 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503624792995 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
221 
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rx_data_take_0 detector_tokens.v(103) " "Verilog HDL or VHDL warning at detector_tokens.v(103): object \"rx_data_take_0\" assigned a value but never read" {  } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 103 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503624792995 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
222 
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "detector_tokens.v(271) " "Verilog HDL Case Statement information at detector_tokens.v(271): all case item expressions in this case statement are onehot" {  } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 271 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1503624792996 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
223 
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "extclk cyclonev_pll 1 2 " "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be left dangling without any fan-out logic." {  } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } }  } 0 12030 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  The extra bits will be left dangling without any fan-out logic." 0 0 "Analysis & Synthesis" 0 -1 1503624798481 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
224 
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[4\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[4\]\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1503624800711 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[4]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[3\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[3\]\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1503624800711 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[3]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[2\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[2\]\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1503624800711 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[2]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[1\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[1\]\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1503624800711 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[1]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[0\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[0\]\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1503624800711 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[0]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|gnd " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|gnd\"" {  } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 427 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1503624800711 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|gnd"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1503624800711 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1503624800711 ""}
225 
{ "Warning" "WINFER_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|mem_rtl_0 " "Inferred RAM node \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|mem_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "Analysis & Synthesis" 0 -1 1503624803108 ""}
226 
{ "Warning" "WINFER_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|mem_rtl_0 " "Inferred RAM node \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|mem_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "Analysis & Synthesis" 0 -1 1503624803110 ""}
227 
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|mem_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|mem_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 9 " "Parameter WIDTH_A set to 9" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 6 " "Parameter WIDTHAD_A set to 6" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 64 " "Parameter NUMWORDS_A set to 64" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 9 " "Parameter WIDTH_B set to 9" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 6 " "Parameter WIDTHAD_B set to 6" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 64 " "Parameter NUMWORDS_B set to 64" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""}  } {  } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|mem_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|mem_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 9 " "Parameter WIDTH_A set to 9" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 6 " "Parameter WIDTHAD_A set to 6" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 64 " "Parameter NUMWORDS_A set to 64" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 9 " "Parameter WIDTH_B set to 9" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 6 " "Parameter WIDTHAD_B set to 6" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 64 " "Parameter NUMWORDS_B set to 64" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1503624814170 ""}  } {  } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1503624814170 ""}  } {  } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1503624814170 ""}
228 
{ "Info" "ISGN_ELABORATION_HEADER" "spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|altsyncram:mem_rtl_0 " "Elaborated megafunction instantiation \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|altsyncram:mem_rtl_0\"" {  } {  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624814544 ""}
229 
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|altsyncram:mem_rtl_0 " "Instantiated megafunction \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|altsyncram:mem_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 9 " "Parameter \"WIDTH_A\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 6 " "Parameter \"WIDTHAD_A\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 64 " "Parameter \"NUMWORDS_A\" = \"64\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 9 " "Parameter \"WIDTH_B\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 6 " "Parameter \"WIDTHAD_B\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 64 " "Parameter \"NUMWORDS_B\" = \"64\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503624814544 ""}  } {  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1503624814544 ""}
230 
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_pfo1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_pfo1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_pfo1 " "Found entity 1: altsyncram_pfo1" {  } { { "db/altsyncram_pfo1.tdf" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/altsyncram_pfo1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503624814624 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624814624 ""}
231 
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "32 " "32 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1503624815265 ""}
232 
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" {  } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1503624826940 "|SPW_ULIGHT_FIFO|LED[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1503624826940 ""}
233 
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624827412 ""}
234 
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1372 " "1372 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1503624833892 ""}
235 
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "ulight_fifo_hps_0_hps_io_border:border " "Timing-Driven Synthesis is running on partition \"ulight_fifo_hps_0_hps_io_border:border\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503624834484 ""}
236 
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503624835350 ""}
237 
{ "Warning" "WAMERGE_PARTITION_MISSING_TOP" "1 " "Found 1 partition definition(s) having no effect on incremental compilation" { { "Warning" "WAMERGE_PARTITION_MISSING" "ulight_fifo_hps_0_hps_io_border:border " "Partition \"ulight_fifo_hps_0_hps_io_border:border\" has no effect on incremental compilation" {  } {  } 0 35015 "Partition \"%1!s!\" has no effect on incremental compilation" 0 0 "Design Software" 0 -1 1503625065202 ""}  } {  } 0 35014 "Found %1!d! partition definition(s) having no effect on incremental compilation" 0 0 "Analysis & Synthesis" 0 -1 1503625065202 ""}
238 
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "15 0 0 0 0 " "Adding 15 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1503625065386 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503625065386 ""}
239 
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" {  } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 3 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1503625067145 "|SPW_ULIGHT_FIFO|KEY[0]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1503625067145 ""}
240 
{ "Info" "ICUT_CUT_TM_SUMMARY" "6981 " "Implemented 6981 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1503625067172 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1503625067172 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6937 " "Implemented 6937 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1503625067172 ""} { "Info" "ICUT_CUT_TM_RAMS" "18 " "Implemented 18 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1503625067172 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1503625067172 ""}
241 
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 47 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 47 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1358 " "Peak virtual memory: 1358 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1503625067280 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 24 22:37:47 2017 " "Processing ended: Thu Aug 24 22:37:47 2017" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1503625067280 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:06 " "Elapsed time: 00:05:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1503625067280 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:05:38 " "Total CPU time (on all processors): 00:05:38" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1503625067280 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1503625067280 ""}

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