| 1 |
40 |
redbear |
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1517798813318 ""}
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| 2 |
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1517798813386 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 5 00:46:52 2018 " "Processing started: Mon Feb 5 00:46:52 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1517798813386 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798813386 ""}
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| 3 |
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798813387 ""}
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| 4 |
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{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "High Performance Effort timing performance increased compilation time " "High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time" { { "Info" "IQCU_OPT_MODE_OVERRIDE" "Fitter Effort Standard Fit " "Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517798823446 ""} { "Info" "IQCU_OPT_MODE_OVERRIDE" "Physical Synthesis Effort Level Normal " "Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517798823446 ""} } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798823446 ""}
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| 5 |
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1517798823763 ""}
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| 6 |
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1517798823763 ""}
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| 7 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_fsm_m " "Found entity 1: tx_fsm_m" { } { { "../../rtl/RTL_VB/tx_fsm_m.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841413 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841413 ""}
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| 8 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_fct_send " "Found entity 1: tx_fct_send" { } { { "../../rtl/RTL_VB/tx_fct_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841447 ""}
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| 9 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_fct_counter " "Found entity 1: tx_fct_counter" { } { { "../../rtl/RTL_VB/tx_fct_counter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841449 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841449 ""}
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| 10 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_data_send " "Found entity 1: tx_data_send" { } { { "../../rtl/RTL_VB/tx_data_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841459 ""}
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| 11 |
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{ "Warning" "WVRFX_L2_VERI_DUPLICATE_ATTRIBUTE" "dont_replicate rx_data_receive.v(64) " "Verilog HDL Attribute warning at rx_data_receive.v(64): overriding existing value for attribute \"dont_replicate\"" { } { { "../../rtl/RTL_VB/rx_data_receive.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v" 64 0 0 } } } 0 10890 "Verilog HDL Attribute warning at %2!s!: overriding existing value for attribute \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798841470 ""}
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| 12 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_data_receive " "Found entity 1: rx_data_receive" { } { { "../../rtl/RTL_VB/rx_data_receive.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841470 ""}
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| 13 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_data_control_p " "Found entity 1: rx_data_control_p" { } { { "../../rtl/RTL_VB/rx_data_control_p.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841474 ""}
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| 14 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_data_buffer_data_w " "Found entity 1: rx_data_buffer_data_w" { } { { "../../rtl/RTL_VB/rx_data_buffer_data_w.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841476 ""}
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| 15 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_control_data_rdy " "Found entity 1: rx_control_data_rdy" { } { { "../../rtl/RTL_VB/rx_control_data_rdy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841477 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841477 ""}
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| 16 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_buffer_fsm " "Found entity 1: rx_buffer_fsm" { } { { "../../rtl/RTL_VB/rx_buffer_fsm.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841480 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841480 ""}
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| 17 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 mem_data " "Found entity 1: mem_data" { } { { "../../rtl/RTL_VB/mem_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841491 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841491 ""}
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| 18 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_neg " "Found entity 1: counter_neg" { } { { "../../rtl/RTL_VB/counter_neg.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841493 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841493 ""}
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| 19 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bit_capture_control " "Found entity 1: bit_capture_control" { } { { "../../rtl/RTL_VB/bitc_capture_control.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841496 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841496 ""}
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| 20 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 bit_capture_data " "Found entity 1: bit_capture_data" { } { { "../../rtl/RTL_VB/bit_capture_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841498 ""}
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| 21 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 TX_SPW " "Found entity 1: TX_SPW" { } { { "../../rtl/RTL_VB/tx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841513 ""}
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| 22 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_spw_ultra_light " "Found entity 1: top_spw_ultra_light" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841515 ""}
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| 23 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" { { "Info" "ISGN_ENTITY_NAME" "1 spw_ulight_con_top_x " "Found entity 1: spw_ulight_con_top_x" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841526 ""}
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| 24 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 RX_SPW " "Found entity 1: RX_SPW" { } { { "../../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841537 ""}
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| 25 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSM_SPW " "Found entity 1: FSM_SPW" { } { { "../../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841540 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841540 ""}
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| 26 |
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{ "Warning" "WVRFX_L2_VERI_DUPLICATE_ATTRIBUTE" "syn_noprune fifo_tx.v(43) " "Verilog HDL Attribute warning at fifo_tx.v(43): overriding existing value for attribute \"syn_noprune\"" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 43 0 0 } } } 0 10890 "Verilog HDL Attribute warning at %2!s!: overriding existing value for attribute \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798841556 ""}
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| 27 |
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{ "Warning" "WVRFX_L2_VERI_DUPLICATE_ATTRIBUTE" "syn_noprune fifo_tx.v(44) " "Verilog HDL Attribute warning at fifo_tx.v(44): overriding existing value for attribute \"syn_noprune\"" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 44 0 0 } } } 0 10890 "Verilog HDL Attribute warning at %2!s!: overriding existing value for attribute \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798841556 ""}
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| 28 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_tx " "Found entity 1: fifo_tx" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841557 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841557 ""}
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| 29 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_rx " "Found entity 1: fifo_rx" { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841565 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841565 ""}
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| 30 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce_db " "Found entity 1: debounce_db" { } { { "../../rtl/DEBUG_VERILOG/debounce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841587 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841587 ""}
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| 31 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" { { "Info" "ISGN_ENTITY_NAME" "1 detector_tokens " "Found entity 1: detector_tokens" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841619 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841619 ""}
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| 32 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_reduce " "Found entity 1: clock_reduce" { } { { "../../rtl/DEBUG_VERILOG/clock_reduce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841635 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841635 ""}
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| 33 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/ulight_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo " "Found entity 1: ulight_fifo" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841654 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841654 ""}
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| 34 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841669 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841669 ""}
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| 35 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841685 ""}
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| 36 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0 " "Found entity 1: ulight_fifo_mm_interconnect_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841728 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841728 ""}
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| 37 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841730 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841730 ""}
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| 38 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841757 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841757 ""}
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| 39 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841760 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841760 ""}
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| 40 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841761 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841761 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841761 ""}
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| 41 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841806 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841806 ""}
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| 42 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841849 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841849 ""}
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| 43 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841860 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841860 ""}
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| 44 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841909 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841909 ""}
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| 45 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841922 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841922 ""}
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| 46 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841929 ""}
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| 47 |
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798841949 ""}
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| 48 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841950 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841950 ""}
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| 49 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841952 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841952 ""}
|
| 50 |
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798841954 ""}
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| 51 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841955 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841955 ""}
|
| 52 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841956 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841956 ""}
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| 53 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841959 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841959 ""}
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| 54 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841960 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841960 ""}
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| 55 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841997 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841997 ""}
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| 56 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842043 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842043 ""}
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| 57 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842045 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 185 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842045 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842045 ""}
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| 58 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842087 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842087 ""}
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| 59 |
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842139 ""}
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| 60 |
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842139 ""}
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| 61 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_002_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_002_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842140 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router_002 " "Found entity 2: ulight_fifo_mm_interconnect_0_router_002" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842140 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842140 ""}
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| 62 |
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842182 ""}
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| 63 |
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842182 ""}
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| 64 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842184 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router " "Found entity 2: ulight_fifo_mm_interconnect_0_router" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842184 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842184 ""}
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| 65 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842230 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842230 ""}
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| 66 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842266 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842266 ""}
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| 67 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_axi_master_ni " "Found entity 1: altera_merlin_axi_master_ni" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842284 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842284 ""}
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| 68 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842287 ""}
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| 69 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_write_data_fifo_tx " "Found entity 1: ulight_fifo_write_data_fifo_tx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842330 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842330 ""}
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| 70 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_tx_data " "Found entity 1: ulight_fifo_timecode_tx_data" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842341 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842341 ""}
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| 71 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_rx " "Found entity 1: ulight_fifo_timecode_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842342 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842342 ""}
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| 72 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_pll_0 " "Found entity 1: ulight_fifo_pll_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842343 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842343 ""}
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| 73 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_led_pio_test " "Found entity 1: ulight_fifo_led_pio_test" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842388 ""}
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| 74 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0 " "Found entity 1: ulight_fifo_hps_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842446 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842446 ""}
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| 75 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io " "Found entity 1: ulight_fifo_hps_0_hps_io" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842447 ""}
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| 76 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram " "Found entity 1: hps_sdram" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842457 ""}
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| 77 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_pll " "Found entity 1: hps_sdram_pll" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842467 ""}
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| 78 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_clock_pair_generator " "Found entity 1: hps_sdram_p0_clock_pair_generator" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842650 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842650 ""}
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| 79 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_addr_cmd_pads " "Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842667 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842667 ""}
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| 80 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_memphy " "Found entity 1: hps_sdram_p0_acv_hard_memphy" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842676 ""}
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| 81 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_ldc " "Found entity 1: hps_sdram_p0_acv_ldc" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842685 ""}
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| 82 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_io_pads " "Found entity 1: hps_sdram_p0_acv_hard_io_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842686 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842686 ""}
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| 83 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_generic_ddio " "Found entity 1: hps_sdram_p0_generic_ddio" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842687 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842687 ""}
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| 84 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset " "Found entity 1: hps_sdram_p0_reset" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842699 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842699 ""}
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| 85 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset_sync " "Found entity 1: hps_sdram_p0_reset_sync" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842714 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842714 ""}
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| 86 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_phy_csr " "Found entity 1: hps_sdram_p0_phy_csr" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842715 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842715 ""}
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| 87 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_iss_probe " "Found entity 1: hps_sdram_p0_iss_probe" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842717 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842717 ""}
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| 88 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0 " "Found entity 1: hps_sdram_p0" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842719 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842719 ""}
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| 89 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_altdqdqs " "Found entity 1: hps_sdram_p0_altdqdqs" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842721 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842721 ""}
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| 90 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altdq_dqs2_acv_connect_to_hard_phy_cyclonev " "Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842740 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842740 ""}
|
| 91 |
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|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hhp_qseq_synth_top " "Found entity 1: altera_mem_if_hhp_qseq_synth_top" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842752 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842752 ""}
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| 92 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hard_memory_controller_top_cyclonev " "Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842809 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842809 ""}
|
| 93 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_oct_cyclonev " "Found entity 1: altera_mem_if_oct_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842822 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842822 ""}
|
| 94 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_dll_cyclonev " "Found entity 1: altera_mem_if_dll_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842828 ""}
|
| 95 |
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|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io_border " "Found entity 1: ulight_fifo_hps_0_hps_io_border" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842830 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842830 ""}
|
| 96 |
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|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_fpga_interfaces " "Found entity 1: ulight_fifo_hps_0_fpga_interfaces" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842834 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842834 ""}
|
| 97 |
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_fifo_empty_rx_status " "Found entity 1: ulight_fifo_fifo_empty_rx_status" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842842 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842842 ""}
|
| 98 |
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_info " "Found entity 1: ulight_fifo_data_info" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842843 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842843 ""}
|
| 99 |
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_flag_rx " "Found entity 1: ulight_fifo_data_flag_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842845 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842845 ""}
|
| 100 |
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_counter_rx_fifo " "Found entity 1: ulight_fifo_counter_rx_fifo" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842846 ""}
|
| 101 |
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_clock_sel " "Found entity 1: ulight_fifo_clock_sel" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842847 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842847 ""}
|
| 102 |
|
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_auto_start " "Found entity 1: ulight_fifo_auto_start" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842850 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842850 ""}
|
| 103 |
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_rtl/spw_fifo_ulight.v 1 1 " "Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPW_ULIGHT_FIFO " "Found entity 1: SPW_ULIGHT_FIFO" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842852 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842852 ""}
|
| 104 |
|
|
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "top_tx_ready_tick spw_fifo_ulight.v(99) " "Verilog HDL Implicit Net warning at spw_fifo_ulight.v(99): created implicit net for \"top_tx_ready_tick\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 99 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798842852 ""}
|
| 105 |
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{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for \"pll_dr_clk\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798842852 ""}
|
| 106 |
|
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{ "Info" "ISGN_START_ELABORATION_TOP" "SPW_ULIGHT_FIFO " "Elaborating entity \"SPW_ULIGHT_FIFO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1517798843221 ""}
|
| 107 |
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[6\] spw_fifo_ulight.v(17) " "Output port \"LED\[6\]\" at spw_fifo_ulight.v(17) has no driver" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843242 "|SPW_ULIGHT_FIFO"}
|
| 108 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo ulight_fifo:u0 " "Elaborating entity \"ulight_fifo\" for hierarchy \"ulight_fifo:u0\"" { } { { "top_rtl/spw_fifo_ulight.v" "u0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843245 ""}
|
| 109 |
|
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_auto_start ulight_fifo:u0\|ulight_fifo_auto_start:auto_start " "Elaborating entity \"ulight_fifo_auto_start\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_auto_start:auto_start\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "auto_start" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843262 ""}
|
| 110 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_clock_sel ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel " "Elaborating entity \"ulight_fifo_clock_sel\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "clock_sel" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 185 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843287 ""}
|
| 111 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_counter_rx_fifo ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo " "Elaborating entity \"ulight_fifo_counter_rx_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "counter_rx_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843332 ""}
|
| 112 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_flag_rx ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx " "Elaborating entity \"ulight_fifo_data_flag_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_flag_rx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 209 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843346 ""}
|
| 113 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_info ulight_fifo:u0\|ulight_fifo_data_info:data_info " "Elaborating entity \"ulight_fifo_data_info\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_info:data_info\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_info" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 217 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843368 ""}
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| 114 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_fifo_empty_rx_status ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status " "Elaborating entity \"ulight_fifo_fifo_empty_rx_status\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "fifo_empty_rx_status" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 236 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843383 ""}
|
| 115 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0 " "Elaborating entity \"ulight_fifo_hps_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "hps_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843418 ""}
|
| 116 |
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|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_fpga_interfaces ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces " "Elaborating entity \"ulight_fifo_hps_0_fpga_interfaces\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "fpga_interfaces" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843456 ""}
|
| 117 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io " "Elaborating entity \"ulight_fifo_hps_0_hps_io\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "hps_io" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843552 ""}
|
| 118 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io_border ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border " "Elaborating entity \"ulight_fifo_hps_0_hps_io_border\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "border" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 45 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843603 ""}
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| 119 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst " "Elaborating entity \"hps_sdram\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "hps_sdram_inst" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 84 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843672 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_pll ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll " "Elaborating entity \"hps_sdram_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "pll" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843696 ""}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object \"pll_dr_clk\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798843707 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "pll_locked hps_sdram_pll.sv(91) " "Output port \"pll_locked\" at hps_sdram_pll.sv(91) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 91 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843707 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0 " "Elaborating entity \"hps_sdram_p0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "p0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 230 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843710 ""}
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{ "Info" "IVRFX_VERI_DISPLAY_SYSTEM_CALL_INFO" "Using Regular core emif simulation models hps_sdram_p0.sv(405) " "Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 405 0 0 } } } 0 10648 "Verilog HDL Display System Task info at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798843726 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_memphy ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy " "Elaborating entity \"hps_sdram_p0_acv_hard_memphy\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "umemphy" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 573 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843729 ""}
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{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "reset_n_seq_clk hps_sdram_p0_acv_hard_memphy.v(420) " "Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1517798843769 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 hps_sdram_p0_acv_hard_memphy.v(557) " "Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 557 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798843769 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "reset_n_seq_clk 0 hps_sdram_p0_acv_hard_memphy.v(420) " "Net \"reset_n_seq_clk\" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0'" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1517798843769 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ctl_reset_export_n hps_sdram_p0_acv_hard_memphy.v(222) " "Output port \"ctl_reset_export_n\" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 222 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843769 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_ldc ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc " "Elaborating entity \"hps_sdram_p0_acv_ldc\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "memphy_ldc" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 554 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843772 ""}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dq hps_sdram_p0_acv_ldc.v(45) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object \"phy_clk_dq\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 45 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798843781 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dqs_2x hps_sdram_p0_acv_ldc.v(47) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object \"phy_clk_dqs_2x\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798843781 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_io_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_io_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "uio_pads" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 780 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843784 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ddio_phy_dqdin\[179..32\] hps_sdram_p0_acv_hard_io_pads.v(191) " "Output port \"ddio_phy_dqdin\[179..32\]\" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 191 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843798 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_addr_cmd_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_addr_cmd_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "uaddr_cmd_pads" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843801 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "uaddress_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843890 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ubank_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 166 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843937 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ucmd_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843957 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ureset_n_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 198 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843993 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborating entity \"altddio_out\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].umem_ck_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844604 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844640 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "extend_oe_disable UNUSED " "Parameter \"extend_oe_disable\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "invert_output OFF " "Parameter \"invert_output\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altddio_out " "Parameter \"lpm_type\" = \"altddio_out\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "oe_reg UNUSED " "Parameter \"oe_reg\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_high OFF " "Parameter \"power_up_high\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 1 " "Parameter \"width\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1517798844641 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ddio_out_uqe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ddio_out_uqe " "Found entity 1: ddio_out_uqe" { } { { "db/ddio_out_uqe.tdf" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/ddio_out_uqe.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798844747 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798844747 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddio_out_uqe ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated " "Elaborating entity \"ddio_out_uqe\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated\"" { } { { "altddio_out.tdf" "auto_generated" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altddio_out.tdf" 100 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844749 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_clock_pair_generator ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator " "Elaborating entity \"hps_sdram_p0_clock_pair_generator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].uclk_generator" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 337 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844809 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_altdqdqs ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs " "Elaborating entity \"hps_sdram_p0_altdqdqs\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "dq_ddio\[0\].ubidir_dq_dqs" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844868 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdq_dqs2_acv_connect_to_hard_phy_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst " "Elaborating entity \"altdq_dqs2_acv_connect_to_hard_phy_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "altdq_dqs2_inst" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 146 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844920 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hhp_qseq_synth_top ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq " "Elaborating entity \"altera_mem_if_hhp_qseq_synth_top\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "seq" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 238 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845026 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hard_memory_controller_top_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0 " "Elaborating entity \"altera_mem_if_hard_memory_controller_top_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "c0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845070 ""}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1166 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_oct_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct " "Elaborating entity \"altera_mem_if_oct_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "oct" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845101 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_dll_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll " "Elaborating entity \"altera_mem_if_dll_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "dll" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 814 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845115 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_led_pio_test ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test " "Elaborating entity \"ulight_fifo_led_pio_test\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "led_pio_test" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 339 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845124 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_pll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0 " "Elaborating entity \"ulight_fifo_pll_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "pll_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845134 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborating entity \"altera_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "altera_pll_i" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845181 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvds_clk altera_pll.v(319) " "Output port \"lvds_clk\" at altera_pll.v(319) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 319 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845241 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_pll.v(320) " "Output port \"loaden\" at altera_pll.v(320) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 320 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845241 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk_out altera_pll.v(321) " "Output port \"extclk_out\" at altera_pll.v(321) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 321 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845241 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"}
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{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "wire_to_nowhere_64 " "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"wire_to_nowhere_64\" into its bus" { } { } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "Analysis & Synthesis" 0 -1 1517798845242 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845242 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "fractional_vco_multiplier false " "Parameter \"fractional_vco_multiplier\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "reference_clock_frequency 50.0 MHz " "Parameter \"reference_clock_frequency\" = \"50.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_cout 32 " "Parameter \"pll_fractional_cout\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_dsm_out_sel 1st_order " "Parameter \"pll_dsm_out_sel\" = \"1st_order\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode normal " "Parameter \"operation_mode\" = \"normal\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_clocks 1 " "Parameter \"number_of_clocks\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency0 400.000000 MHz " "Parameter \"output_clock_frequency0\" = \"400.000000 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift0 0 ps " "Parameter \"phase_shift0\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle0 50 " "Parameter \"duty_cycle0\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency1 0 MHz " "Parameter \"output_clock_frequency1\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift1 0 ps " "Parameter \"phase_shift1\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle1 50 " "Parameter \"duty_cycle1\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency2 0 MHz " "Parameter \"output_clock_frequency2\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift2 0 ps " "Parameter \"phase_shift2\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle2 50 " "Parameter \"duty_cycle2\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency3 0 MHz " "Parameter \"output_clock_frequency3\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift3 0 ps " "Parameter \"phase_shift3\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle3 50 " "Parameter \"duty_cycle3\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency4 0 MHz " "Parameter \"output_clock_frequency4\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift4 0 ps " "Parameter \"phase_shift4\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle4 50 " "Parameter \"duty_cycle4\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency5 0 MHz " "Parameter \"output_clock_frequency5\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift5 0 ps " "Parameter \"phase_shift5\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle5 50 " "Parameter \"duty_cycle5\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency6 0 MHz " "Parameter \"output_clock_frequency6\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift6 0 ps " "Parameter \"phase_shift6\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle6 50 " "Parameter \"duty_cycle6\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency7 0 MHz " "Parameter \"output_clock_frequency7\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift7 0 ps " "Parameter \"phase_shift7\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle7 50 " "Parameter \"duty_cycle7\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency8 0 MHz " "Parameter \"output_clock_frequency8\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift8 0 ps " "Parameter \"phase_shift8\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle8 50 " "Parameter \"duty_cycle8\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency9 0 MHz " "Parameter \"output_clock_frequency9\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift9 0 ps " "Parameter \"phase_shift9\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle9 50 " "Parameter \"duty_cycle9\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency10 0 MHz " "Parameter \"output_clock_frequency10\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift10 0 ps " "Parameter \"phase_shift10\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle10 50 " "Parameter \"duty_cycle10\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency11 0 MHz " "Parameter \"output_clock_frequency11\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift11 0 ps " "Parameter \"phase_shift11\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle11 50 " "Parameter \"duty_cycle11\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency12 0 MHz " "Parameter \"output_clock_frequency12\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift12 0 ps " "Parameter \"phase_shift12\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle12 50 " "Parameter \"duty_cycle12\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency13 0 MHz " "Parameter \"output_clock_frequency13\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift13 0 ps " "Parameter \"phase_shift13\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle13 50 " "Parameter \"duty_cycle13\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency14 0 MHz " "Parameter \"output_clock_frequency14\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift14 0 ps " "Parameter \"phase_shift14\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle14 50 " "Parameter \"duty_cycle14\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency15 0 MHz " "Parameter \"output_clock_frequency15\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift15 0 ps " "Parameter \"phase_shift15\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle15 50 " "Parameter \"duty_cycle15\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency16 0 MHz " "Parameter \"output_clock_frequency16\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift16 0 ps " "Parameter \"phase_shift16\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle16 50 " "Parameter \"duty_cycle16\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency17 0 MHz " "Parameter \"output_clock_frequency17\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift17 0 ps " "Parameter \"phase_shift17\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle17 50 " "Parameter \"duty_cycle17\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type Cyclone V " "Parameter \"pll_type\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_subtype General " "Parameter \"pll_subtype\" = \"General\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_hi_div 4 " "Parameter \"m_cnt_hi_div\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_lo_div 4 " "Parameter \"m_cnt_lo_div\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_hi_div 256 " "Parameter \"n_cnt_hi_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_lo_div 256 " "Parameter \"n_cnt_lo_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_bypass_en false " "Parameter \"m_cnt_bypass_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_bypass_en true " "Parameter \"n_cnt_bypass_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_odd_div_duty_en false " "Parameter \"m_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_odd_div_duty_en false " "Parameter \"n_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div0 256 " "Parameter \"c_cnt_hi_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div0 256 " "Parameter \"c_cnt_lo_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst0 1 " "Parameter \"c_cnt_prst0\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst0 0 " "Parameter \"c_cnt_ph_mux_prst0\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src0 ph_mux_clk " "Parameter \"c_cnt_in_src0\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en0 true " "Parameter \"c_cnt_bypass_en0\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en0 false " "Parameter \"c_cnt_odd_div_duty_en0\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div1 1 " "Parameter \"c_cnt_hi_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div1 1 " "Parameter \"c_cnt_lo_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst1 1 " "Parameter \"c_cnt_prst1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst1 0 " "Parameter \"c_cnt_ph_mux_prst1\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src1 ph_mux_clk " "Parameter \"c_cnt_in_src1\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en1 true " "Parameter \"c_cnt_bypass_en1\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en1 false " "Parameter \"c_cnt_odd_div_duty_en1\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div2 1 " "Parameter \"c_cnt_hi_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div2 1 " "Parameter \"c_cnt_lo_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst2 1 " "Parameter \"c_cnt_prst2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst2 0 " "Parameter \"c_cnt_ph_mux_prst2\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src2 ph_mux_clk " "Parameter \"c_cnt_in_src2\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en2 true " "Parameter \"c_cnt_bypass_en2\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en2 false " "Parameter \"c_cnt_odd_div_duty_en2\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div3 1 " "Parameter \"c_cnt_hi_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div3 1 " "Parameter \"c_cnt_lo_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst3 1 " "Parameter \"c_cnt_prst3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst3 0 " "Parameter \"c_cnt_ph_mux_prst3\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src3 ph_mux_clk " "Parameter \"c_cnt_in_src3\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en3 true " "Parameter \"c_cnt_bypass_en3\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en3 false " "Parameter \"c_cnt_odd_div_duty_en3\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div4 1 " "Parameter \"c_cnt_hi_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div4 1 " "Parameter \"c_cnt_lo_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst4 1 " "Parameter \"c_cnt_prst4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst4 0 " "Parameter \"c_cnt_ph_mux_prst4\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src4 ph_mux_clk " "Parameter \"c_cnt_in_src4\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en4 true " "Parameter \"c_cnt_bypass_en4\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en4 false " "Parameter \"c_cnt_odd_div_duty_en4\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div5 1 " "Parameter \"c_cnt_hi_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div5 1 " "Parameter \"c_cnt_lo_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst5 1 " "Parameter \"c_cnt_prst5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst5 0 " "Parameter \"c_cnt_ph_mux_prst5\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src5 ph_mux_clk " "Parameter \"c_cnt_in_src5\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en5 true " "Parameter \"c_cnt_bypass_en5\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en5 false " "Parameter \"c_cnt_odd_div_duty_en5\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div6 1 " "Parameter \"c_cnt_hi_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div6 1 " "Parameter \"c_cnt_lo_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst6 1 " "Parameter \"c_cnt_prst6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst6 0 " "Parameter \"c_cnt_ph_mux_prst6\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src6 ph_mux_clk " "Parameter \"c_cnt_in_src6\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en6 true " "Parameter \"c_cnt_bypass_en6\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en6 false " "Parameter \"c_cnt_odd_div_duty_en6\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div7 1 " "Parameter \"c_cnt_hi_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div7 1 " "Parameter \"c_cnt_lo_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst7 1 " "Parameter \"c_cnt_prst7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst7 0 " "Parameter \"c_cnt_ph_mux_prst7\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src7 ph_mux_clk " "Parameter \"c_cnt_in_src7\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en7 true " "Parameter \"c_cnt_bypass_en7\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en7 false " "Parameter \"c_cnt_odd_div_duty_en7\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div8 1 " "Parameter \"c_cnt_hi_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div8 1 " "Parameter \"c_cnt_lo_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst8 1 " "Parameter \"c_cnt_prst8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst8 0 " "Parameter \"c_cnt_ph_mux_prst8\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src8 ph_mux_clk " "Parameter \"c_cnt_in_src8\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en8 true " "Parameter \"c_cnt_bypass_en8\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en8 false " "Parameter \"c_cnt_odd_div_duty_en8\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div9 1 " "Parameter \"c_cnt_hi_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div9 1 " "Parameter \"c_cnt_lo_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst9 1 " "Parameter \"c_cnt_prst9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst9 0 " "Parameter \"c_cnt_ph_mux_prst9\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src9 ph_mux_clk " "Parameter \"c_cnt_in_src9\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en9 true " "Parameter \"c_cnt_bypass_en9\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en9 false " "Parameter \"c_cnt_odd_div_duty_en9\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div10 1 " "Parameter \"c_cnt_hi_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div10 1 " "Parameter \"c_cnt_lo_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst10 1 " "Parameter \"c_cnt_prst10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst10 0 " "Parameter \"c_cnt_ph_mux_prst10\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src10 ph_mux_clk " "Parameter \"c_cnt_in_src10\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en10 true " "Parameter \"c_cnt_bypass_en10\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en10 false " "Parameter \"c_cnt_odd_div_duty_en10\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div11 1 " "Parameter \"c_cnt_hi_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div11 1 " "Parameter \"c_cnt_lo_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst11 1 " "Parameter \"c_cnt_prst11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst11 0 " "Parameter \"c_cnt_ph_mux_prst11\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src11 ph_mux_clk " "Parameter \"c_cnt_in_src11\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en11 true " "Parameter \"c_cnt_bypass_en11\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en11 false " "Parameter \"c_cnt_odd_div_duty_en11\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div12 1 " "Parameter \"c_cnt_hi_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div12 1 " "Parameter \"c_cnt_lo_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst12 1 " "Parameter \"c_cnt_prst12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst12 0 " "Parameter \"c_cnt_ph_mux_prst12\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src12 ph_mux_clk " "Parameter \"c_cnt_in_src12\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en12 true " "Parameter \"c_cnt_bypass_en12\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en12 false " "Parameter \"c_cnt_odd_div_duty_en12\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div13 1 " "Parameter \"c_cnt_hi_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div13 1 " "Parameter \"c_cnt_lo_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst13 1 " "Parameter \"c_cnt_prst13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst13 0 " "Parameter \"c_cnt_ph_mux_prst13\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src13 ph_mux_clk " "Parameter \"c_cnt_in_src13\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en13 true " "Parameter \"c_cnt_bypass_en13\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en13 false " "Parameter \"c_cnt_odd_div_duty_en13\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div14 1 " "Parameter \"c_cnt_hi_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div14 1 " "Parameter \"c_cnt_lo_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst14 1 " "Parameter \"c_cnt_prst14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst14 0 " "Parameter \"c_cnt_ph_mux_prst14\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src14 ph_mux_clk " "Parameter \"c_cnt_in_src14\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en14 true " "Parameter \"c_cnt_bypass_en14\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en14 false " "Parameter \"c_cnt_odd_div_duty_en14\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div15 1 " "Parameter \"c_cnt_hi_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div15 1 " "Parameter \"c_cnt_lo_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst15 1 " "Parameter \"c_cnt_prst15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst15 0 " "Parameter \"c_cnt_ph_mux_prst15\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src15 ph_mux_clk " "Parameter \"c_cnt_in_src15\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en15 true " "Parameter \"c_cnt_bypass_en15\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en15 false " "Parameter \"c_cnt_odd_div_duty_en15\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div16 1 " "Parameter \"c_cnt_hi_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div16 1 " "Parameter \"c_cnt_lo_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst16 1 " "Parameter \"c_cnt_prst16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst16 0 " "Parameter \"c_cnt_ph_mux_prst16\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src16 ph_mux_clk " "Parameter \"c_cnt_in_src16\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en16 true " "Parameter \"c_cnt_bypass_en16\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en16 false " "Parameter \"c_cnt_odd_div_duty_en16\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div17 1 " "Parameter \"c_cnt_hi_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div17 1 " "Parameter \"c_cnt_lo_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst17 1 " "Parameter \"c_cnt_prst17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst17 0 " "Parameter \"c_cnt_ph_mux_prst17\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src17 ph_mux_clk " "Parameter \"c_cnt_in_src17\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en17 true " "Parameter \"c_cnt_bypass_en17\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en17 false " "Parameter \"c_cnt_odd_div_duty_en17\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_vco_div 2 " "Parameter \"pll_vco_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_cp_current 20 " "Parameter \"pll_cp_current\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_bwctrl 4000 " "Parameter \"pll_bwctrl\" = \"4000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_output_clk_frequency 400.0 MHz " "Parameter \"pll_output_clk_frequency\" = \"400.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_division 1 " "Parameter \"pll_fractional_division\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "mimic_fbclk_type gclk " "Parameter \"mimic_fbclk_type\" = \"gclk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_1 glb " "Parameter \"pll_fbclk_mux_1\" = \"glb\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_2 fb_1 " "Parameter \"pll_fbclk_mux_2\" = \"fb_1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_m_cnt_in_src ph_mux_clk " "Parameter \"pll_m_cnt_in_src\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_slf_rst false " "Parameter \"pll_slf_rst\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "refclk1_frequency 100.0 MHz " "Parameter \"refclk1_frequency\" = \"100.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_loss_sw_en true " "Parameter \"pll_clk_loss_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_manu_clk_sw_en false " "Parameter \"pll_manu_clk_sw_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_auto_clk_sw_en true " "Parameter \"pll_auto_clk_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clkin_1_src clk_1 " "Parameter \"pll_clkin_1_src\" = \"clk_1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_sw_dly 0 " "Parameter \"pll_clk_sw_dly\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1517798845243 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dps_extra_kick ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst " "Elaborating entity \"dps_extra_kick\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\"" { } { { "altera_pll.v" "dps_extra_inst" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 768 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845249 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 768 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845310 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dprio_init ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst " "Elaborating entity \"dprio_init\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\"" { } { { "altera_pll.v" "dprio_init_inst" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 783 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845313 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 783 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845316 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\"" { } { { "altera_pll.v" "lcell_cntsel_int_0" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1960 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845325 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1960 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845367 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\"" { } { { "altera_pll.v" "lcell_cntsel_int_1" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1971 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845369 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1971 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845406 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\"" { } { { "altera_pll.v" "lcell_cntsel_int_2" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1982 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845408 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1982 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845438 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\"" { } { { "altera_pll.v" "lcell_cntsel_int_3" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1993 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845441 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1993 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845453 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\"" { } { { "altera_pll.v" "lcell_cntsel_int_4" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2004 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845457 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2004 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845480 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll " "Elaborating entity \"altera_cyclonev_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\"" { } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845497 ""}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk altera_cyclonev_pll.v(631) " "Output port \"extclk\" at altera_cyclonev_pll.v(631) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 631 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845533 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "clkout\[0\] altera_cyclonev_pll.v(636) " "Output port \"clkout\[0\]\" at altera_cyclonev_pll.v(636) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 636 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845534 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_cyclonev_pll.v(640) " "Output port \"loaden\" at altera_cyclonev_pll.v(640) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 640 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845534 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
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{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvdsclk altera_cyclonev_pll.v(641) " "Output port \"lvdsclk\" at altera_cyclonev_pll.v(641) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 641 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845534 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2223 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845534 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll_base ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 " "Elaborating entity \"altera_cyclonev_pll_base\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\"" { } { { "altera_cyclonev_pll.v" "fpll_0" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1152 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845536 ""}
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{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1152 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845573 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_rx ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx " "Elaborating entity \"ulight_fifo_timecode_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_rx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 385 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845580 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_tx_data ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data " "Elaborating entity \"ulight_fifo_timecode_tx_data\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_tx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 396 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845584 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_write_data_fifo_tx ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx " "Elaborating entity \"ulight_fifo_write_data_fifo_tx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "write_data_fifo_tx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845592 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "mm_interconnect_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845630 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_translator" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 1962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845879 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_axi_master_ni ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent " "Elaborating entity \"altera_merlin_axi_master_ni\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_agent" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3434 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845953 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845980 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3518 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846007 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 608 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846033 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rsp_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3559 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846048 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rdata_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3600 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846060 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846300 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846335 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router_002" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846352 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846404 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_wr_limiter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7520 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846478 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7620 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846513 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_13_1 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter_13_1\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_13_1.burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846546 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 778 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846577 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_burstwrap_increment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment " "Elaborating entity \"altera_merlin_burst_adapter_burstwrap_increment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_burstwrap_increment" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846581 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_min ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min " "Elaborating entity \"altera_merlin_burst_adapter_min\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_min" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 1004 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846584 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_subtractor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub " "Elaborating entity \"altera_merlin_burst_adapter_subtractor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "ab_sub" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846611 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract " "Elaborating entity \"altera_merlin_burst_adapter_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "subtract" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 88 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846625 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_demux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8813 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847450 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_mux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847487 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 287 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847537 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847593 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_demux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847740 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_mux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10111 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847808 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 630 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847862 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847897 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "avalon_st_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10283 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847916 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "error_adapter_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 200 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847920 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller ulight_fifo:u0\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "rst_controller" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 616 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848007 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848031 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_req_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 220 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848035 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spw_ulight_con_top_x spw_ulight_con_top_x:A_SPW_TOP " "Elaborating entity \"spw_ulight_con_top_x\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\"" { } { { "top_rtl/spw_fifo_ulight.v" "A_SPW_TOP" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 148 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848043 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "top_spw_ultra_light spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW " "Elaborating entity \"top_spw_ultra_light\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\"" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "SPW" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 136 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848096 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSM_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM " "Elaborating entity \"FSM_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\"" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "FSM" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 112 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848109 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX " "Elaborating entity \"RX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\"" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "RX" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848125 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_buffer_fsm spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_buffer_fsm:buffer_fsm " "Elaborating entity \"rx_buffer_fsm\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_buffer_fsm:buffer_fsm\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "buffer_fsm" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 176 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848143 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_data_buffer_data_w spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_buffer_data_w:buffer_data_flag " "Elaborating entity \"rx_data_buffer_data_w\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_buffer_data_w:buffer_data_flag\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "buffer_data_flag" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 191 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848173 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_control_data_rdy spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_control_data_rdy:control_data_rdy " "Elaborating entity \"rx_control_data_rdy\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_control_data_rdy:control_data_rdy\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "control_data_rdy" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848203 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_data_control_p spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_control_p:data_control " "Elaborating entity \"rx_data_control_p\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_control_p:data_control\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "data_control" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 250 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848211 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bit_capture_data spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|bit_capture_data:capture_d " "Elaborating entity \"bit_capture_data\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|bit_capture_data:capture_d\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "capture_d" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848214 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bit_capture_control spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|bit_capture_control:capture_c " "Elaborating entity \"bit_capture_control\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|bit_capture_control:capture_c\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "capture_c" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 283 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848219 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_neg spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|counter_neg:cnt_neg " "Elaborating entity \"counter_neg\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|counter_neg:cnt_neg\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "cnt_neg" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 291 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848228 ""}
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{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "counter_neg.v(58) " "Verilog HDL Case Statement information at counter_neg.v(58): all case item expressions in this case statement are onehot" { } { { "../../rtl/RTL_VB/counter_neg.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v" 58 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1517798848229 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_data_receive spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_receive:rx_dtarcv " "Elaborating entity \"rx_data_receive\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_receive:rx_dtarcv\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "rx_dtarcv" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 325 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848231 ""}
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| 238 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX " "Elaborating entity \"TX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\"" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "TX" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848234 ""}
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| 239 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_fsm_m spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm " "Elaborating entity \"tx_fsm_m\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\"" { } { { "../../rtl/RTL_VB/tx_spw.v" "tx_fsm" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" 117 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848250 ""}
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| 240 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_fct_counter spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt " "Elaborating entity \"tx_fct_counter\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\"" { } { { "../../rtl/RTL_VB/tx_fsm_m.v" "tx_fct_cnt" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" 789 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848269 ""}
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| 241 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_fct_send spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd " "Elaborating entity \"tx_fct_send\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\"" { } { { "../../rtl/RTL_VB/tx_fsm_m.v" "tx_fct_snd" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" 797 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848276 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_data_send spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_data_send:tx_data_snd " "Elaborating entity \"tx_data_send\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_data_send:tx_data_snd\"" { } { { "../../rtl/RTL_VB/tx_spw.v" "tx_data_snd" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" 142 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848296 ""}
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| 243 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_rx spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data " "Elaborating entity \"fifo_rx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\"" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "rx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848352 ""}
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| 244 |
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mem_data spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|mem_data:mem_dta_fifo_tx " "Elaborating entity \"mem_data\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|mem_data:mem_dta_fifo_tx\"" { } { { "../../rtl/RTL_VB/fifo_rx.v" "mem_dta_fifo_tx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 415 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848378 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_tx spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data " "Elaborating entity \"fifo_tx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\"" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "tx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848406 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debounce_db debounce_db:db_system_spwulight_b " "Elaborating entity \"debounce_db\" for hierarchy \"debounce_db:db_system_spwulight_b\"" { } { { "top_rtl/spw_fifo_ulight.v" "db_system_spwulight_b" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 155 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848420 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_reduce clock_reduce:R_400_to_2_5_10_100_200_300MHZ " "Elaborating entity \"clock_reduce\" for hierarchy \"clock_reduce:R_400_to_2_5_10_100_200_300MHZ\"" { } { { "top_rtl/spw_fifo_ulight.v" "R_400_to_2_5_10_100_200_300MHZ" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 163 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848422 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "detector_tokens detector_tokens:m_x " "Elaborating entity \"detector_tokens\" for hierarchy \"detector_tokens:m_x\"" { } { { "top_rtl/spw_fifo_ulight.v" "m_x" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848437 ""}
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| 249 |
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "control_r detector_tokens.v(87) " "Verilog HDL or VHDL warning at detector_tokens.v(87): object \"control_r\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 87 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798848442 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
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{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "control_p_r detector_tokens.v(88) " "Verilog HDL warning at detector_tokens.v(88): object control_p_r used but never assigned" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 88 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
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| 251 |
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "dta_timec detector_tokens.v(92) " "Verilog HDL or VHDL warning at detector_tokens.v(92): object \"dta_timec\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 92 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
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| 252 |
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{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "dta_timec_p detector_tokens.v(93) " "Verilog HDL warning at detector_tokens.v(93): object dta_timec_p used but never assigned" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 93 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
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| 253 |
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ready_control detector_tokens.v(104) " "Verilog HDL or VHDL warning at detector_tokens.v(104): object \"ready_control\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 104 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ready_data detector_tokens.v(105) " "Verilog HDL or VHDL warning at detector_tokens.v(105): object \"ready_data\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 105 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
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| 255 |
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "control_p_r 0 detector_tokens.v(88) " "Net \"control_p_r\" at detector_tokens.v(88) has no driver or initial value, using a default initial value '0'" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 88 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
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| 256 |
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "dta_timec_p\[7..0\] 0 detector_tokens.v(93) " "Net \"dta_timec_p\[7..0\]\" at detector_tokens.v(93) has no driver or initial value, using a default initial value '0'" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 93 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"}
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| 257 |
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{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "extclk cyclonev_pll 1 2 " "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2223 0 0 } } } 0 12030 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be left dangling without any fan-out logic." 0 0 "Analysis & Synthesis" 0 -1 1517798855164 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"}
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| 258 |
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{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[4\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[4\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[4]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[3\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[3\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[3]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[2\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[2\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[2]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[1\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[1\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[1]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[0\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[0\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[0]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|gnd " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|gnd\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 426 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|gnd"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1517798857940 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1517798857940 ""}
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{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "2 " "Ignored 2 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "2 " "Ignored 2 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Design Software" 0 -1 1517798860164 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Analysis & Synthesis" 0 -1 1517798860164 ""}
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{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "32 " "32 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1517798873413 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873498 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873499 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873501 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873503 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_info_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_info_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873505 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873506 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873508 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873510 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873511 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873513 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873515 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873517 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:link_disable_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:link_disable_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873520 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:auto_start_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:auto_start_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873522 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:link_start_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:link_start_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873524 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873525 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873526 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873528 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873529 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873531 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873532 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873534 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|detector_tokens:m_x\|state_data_process " "State machine \"\|SPW_ULIGHT_FIFO\|detector_tokens:m_x\|state_data_process\" will be implemented as a safe state machine." { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 51 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873535 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_open_slot " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_open_slot\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 60 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873535 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_data_write " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_data_write\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 54 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873536 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_data_read " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_data_read\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 57 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873536 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\|dps_current_state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\|dps_current_state\" will be implemented as a safe state machine." { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2672 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873537 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|state_data_read " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|state_data_read\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 52 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873537 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|state_tx " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|state_tx\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fsm_m.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" 92 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873539 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\|state_fct_send " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\|state_fct_send\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fct_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" 45 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873540 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\|state_fct_send_p " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\|state_fct_send_p\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fct_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" 48 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873540 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\|state_fct_p " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\|state_fct_p\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fct_counter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" 47 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873541 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|state_data_write " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|state_data_write\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 49 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873541 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\|state_fct_receive " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\|state_fct_receive\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fct_counter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" 44 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873542 ""}
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{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\|state_fsm " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\|state_fsm\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" 71 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873543 ""}
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{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1517798887177 "|SPW_ULIGHT_FIFO|LED[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1517798887177 ""}
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| 297 |
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798887909 ""}
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| 298 |
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{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1382 " "1382 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1517798893747 ""}
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| 299 |
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "ulight_fifo_hps_0_hps_io_border:border " "Timing-Driven Synthesis is running on partition \"ulight_fifo_hps_0_hps_io_border:border\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798894460 ""}
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| 300 |
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798895861 ""}
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| 301 |
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{ "Warning" "WAMERGE_PARTITION_MISSING_TOP" "1 " "Found 1 partition definition(s) having no effect on incremental compilation" { { "Warning" "WAMERGE_PARTITION_MISSING" "ulight_fifo_hps_0_hps_io_border:border " "Partition \"ulight_fifo_hps_0_hps_io_border:border\" has no effect on incremental compilation" { } { } 0 35015 "Partition \"%1!s!\" has no effect on incremental compilation" 0 0 "Design Software" 0 -1 1517799127876 ""} } { } 0 35014 "Found %1!d! partition definition(s) having no effect on incremental compilation" 0 0 "Analysis & Synthesis" 0 -1 1517799127876 ""}
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| 302 |
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "15 0 0 0 0 " "Adding 15 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1517799128148 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517799128148 ""}
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| 303 |
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{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1517799130174 "|SPW_ULIGHT_FIFO|KEY[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1517799130174 ""}
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| 304 |
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{ "Info" "ICUT_CUT_TM_SUMMARY" "8595 " "Implemented 8595 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1517799130206 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1517799130206 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8569 " "Implemented 8569 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1517799130206 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1517799130206 ""}
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| 305 |
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 53 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 53 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1310 " "Peak virtual memory: 1310 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1517799130374 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 5 00:52:10 2018 " "Processing ended: Mon Feb 5 00:52:10 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1517799130374 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:18 " "Elapsed time: 00:05:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1517799130374 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:05:46 " "Total CPU time (on all processors): 00:05:46" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1517799130374 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1517799130374 ""}
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