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Assembler report for spw_fifo_ulight
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Mon Feb 5 00:57:44 2018
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Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Assembler Summary
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3. Assembler Settings
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4. Assembler Generated Files
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5. Assembler Device Options: spw_fifo_ulight.sof
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6. Assembler Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+---------------------------------------------------------------+
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; Assembler Summary ;
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+-----------------------+---------------------------------------+
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; Assembler Status ; Successful - Mon Feb 5 00:57:44 2018 ;
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; Revision Name ; spw_fifo_ulight ;
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; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
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; Family ; Cyclone V ;
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; Device ; 5CSEMA4U23C6 ;
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+-----------------------+---------------------------------------+
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+----------------------------------+
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; Assembler Settings ;
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+--------+---------+---------------+
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; Option ; Setting ; Default Value ;
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+--------+---------+---------------+
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+---------------------------------------------------------------------------------------------------------------------------------------+
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; Assembler Generated Files ;
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+---------------------------------------------------------------------------------------------------------------------------------------+
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; File Name ;
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+---------------------------------------------------------------------------------------------------------------------------------------+
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.sof ;
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+---------------------------------------------------------------------------------------------------------------------------------------+
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+-----------------------------------------------+
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; Assembler Device Options: spw_fifo_ulight.sof ;
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+----------------+------------------------------+
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; Option ; Setting ;
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+----------------+------------------------------+
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; JTAG usercode ; 0x00C20F9D ;
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; Checksum ; 0x00C20F9D ;
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+----------------+------------------------------+
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+--------------------+
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; Assembler Messages ;
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+--------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Assembler
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Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
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Info: Processing started: Mon Feb 5 00:57:25 2018
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (115030): Assembler is generating device programming files
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Info (11878): Hard Processor Subsystem configuration has not changed and a Preloader software update is not required
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Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 1044 megabytes
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Info: Processing ended: Mon Feb 5 00:57:44 2018
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Info: Elapsed time: 00:00:19
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Info: Total CPU time (on all processors): 00:00:11
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