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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.map.summary] - Blame information for rev 35

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Line No. Rev Author Line
1 35 redbear
Analysis & Synthesis Status : Successful - Fri Sep 15 08:13:05 2017
2 32 redbear
Quartus Prime Version : 17.0.1 Build 598 06/07/2017 SJ Lite Edition
3
Revision Name : spw_fifo_ulight
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Top-level Entity Name : SPW_ULIGHT_FIFO
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Family : Cyclone V
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Logic utilization (in ALMs) : N/A
7 35 redbear
Total registers : 4692
8 32 redbear
Total pins : 15
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Total virtual pins : 0
10 35 redbear
Total block memory bits : 0
11 32 redbear
Total DSP Blocks : 0
12
Total HSSI RX PCSs : 0
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Total HSSI PMA RX Deserializers : 0
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Total HSSI TX PCSs : 0
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Total HSSI PMA TX Serializers : 0
16
Total PLLs : 1
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Total DLLs : 0

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