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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.sta.rpt] - Blame information for rev 35

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Line No.	Rev	Author	Line
1	32	redbear	`TimeQuest Timing Analyzer report for spw_fifo_ulight`
2	35	redbear	`Fri Sep 15 08:19:10 2017`
3	32	redbear	`Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition`
4
5
6			`---------------------`
7			`; Table of Contents ;`
8			`---------------------`
9			`1. Legal Notice`
10			`2. TimeQuest Timing Analyzer Summary`
11			`3. Parallel Compilation`
12			`4. SDC File List`
13			`5. Clocks`
14			`6. Slow 1100mV 85C Model Fmax Summary`
15			`7. Timing Closure Recommendations`
16			`8. Slow 1100mV 85C Model Setup Summary`
17			`9. Slow 1100mV 85C Model Hold Summary`
18			`10. Slow 1100mV 85C Model Recovery Summary`
19			`11. Slow 1100mV 85C Model Removal Summary`
20			`12. Slow 1100mV 85C Model Minimum Pulse Width Summary`
21			`13. Slow 1100mV 85C Model Metastability Summary`
22			`14. Slow 1100mV 0C Model Fmax Summary`
23			`15. Slow 1100mV 0C Model Setup Summary`
24			`16. Slow 1100mV 0C Model Hold Summary`
25			`17. Slow 1100mV 0C Model Recovery Summary`
26			`18. Slow 1100mV 0C Model Removal Summary`
27			`19. Slow 1100mV 0C Model Minimum Pulse Width Summary`
28			`20. Slow 1100mV 0C Model Metastability Summary`
29			`21. Fast 1100mV 85C Model Setup Summary`
30			`22. Fast 1100mV 85C Model Hold Summary`
31			`23. Fast 1100mV 85C Model Recovery Summary`
32			`24. Fast 1100mV 85C Model Removal Summary`
33			`25. Fast 1100mV 85C Model Minimum Pulse Width Summary`
34			`26. Fast 1100mV 85C Model Metastability Summary`
35			`27. Fast 1100mV 0C Model Setup Summary`
36			`28. Fast 1100mV 0C Model Hold Summary`
37			`29. Fast 1100mV 0C Model Recovery Summary`
38			`30. Fast 1100mV 0C Model Removal Summary`
39			`31. Fast 1100mV 0C Model Minimum Pulse Width Summary`
40			`32. Fast 1100mV 0C Model Metastability Summary`
41			`33. Multicorner Timing Analysis Summary`
42			`34. Board Trace Model Assignments`
43			`35. Input Transition Times`
44			`36. Signal Integrity Metrics (Slow 1100mv 0c Model)`
45			`37. Signal Integrity Metrics (Slow 1100mv 85c Model)`
46			`38. Signal Integrity Metrics (Fast 1100mv 0c Model)`
47			`39. Signal Integrity Metrics (Fast 1100mv 85c Model)`
48			`40. Setup Transfers`
49			`41. Hold Transfers`
50			`42. Recovery Transfers`
51			`43. Removal Transfers`
52			`44. Report TCCS`
53			`45. Report RSKM`
54			`46. Unconstrained Paths Summary`
55			`47. Clock Status Summary`
56			`48. Unconstrained Input Ports`
57			`49. Unconstrained Output Ports`
58			`50. Unconstrained Input Ports`
59			`51. Unconstrained Output Ports`
60			`52. TimeQuest Timing Analyzer Messages`
61
62
63
64			`----------------`
65			`; Legal Notice ;`
66			`----------------`
67			`Copyright (C) 2017 Intel Corporation. All rights reserved.`
68			`Your use of Intel Corporation's design tools, logic functions`
69			`and other software and tools, and its AMPP partner logic`
70			`functions, and any output files from any of the foregoing`
71			`(including device programming or simulation files), and any`
72			`associated documentation or information are expressly subject`
73			`to the terms and conditions of the Intel Program License`
74			`Subscription Agreement, the Intel Quartus Prime License Agreement,`
75			`the Intel MegaCore Function License Agreement, or other`
76			`applicable license agreement, including, without limitation,`
77			`that your use is for the sole purpose of programming logic`
78			`devices manufactured by Intel and sold by Intel or its`
79			`authorized distributors. Please refer to the applicable`
80			`agreement for further details.`
81
82
83
84			`+-----------------------------------------------------------------------------+`
85			`; TimeQuest Timing Analyzer Summary ;`
86			`+-----------------------+-----------------------------------------------------+`
87			`; Quartus Prime Version ; Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;`
88			`; Timing Analyzer ; TimeQuest ;`
89			`; Revision Name ; spw_fifo_ulight ;`
90			`; Device Family ; Cyclone V ;`
91			`; Device Name ; 5CSEMA4U23C6 ;`
92			`; Timing Models ; Final ;`
93			`; Delay Model ; Combined ;`
94			`; Rise/Fall Delays ; Enabled ;`
95			`+-----------------------+-----------------------------------------------------+`
96
97
98			`+------------------------------------------+`
99			`; Parallel Compilation ;`
100			`+----------------------------+-------------+`
101			`; Processors ; Number ;`
102			`+----------------------------+-------------+`
103			`; Number detected on machine ; 4 ;`
104			`; Maximum allowed ; 2 ;`
105			`; ; ;`
106	35	redbear	`; Average used ; 1.48 ;`
107	32	redbear	`; Maximum used ; 2 ;`
108			`; ; ;`
109			`; Usage by Processor ; % Time Used ;`
110			`; Processor 1 ; 100.0% ;`
111	35	redbear	`; Processor 2 ; 47.8% ;`
112	32	redbear	`+----------------------------+-------------+`
113
114
115			`+--------------------------------------------------------------------------------------------------+`
116			`; SDC File List ;`
117			`+--------------------------------------------------------------+--------+--------------------------+`
118			`; SDC File Path ; Status ; Read at ;`
119			`+--------------------------------------------------------------+--------+--------------------------+`
120	35	redbear	`; sdc/spw_fifo_ulight.out.sdc ; OK ; Fri Sep 15 08:18:31 2017 ;`
121			`; ulight_fifo/synthesis/submodules/altera_reset_controller.sdc ; OK ; Fri Sep 15 08:18:31 2017 ;`
122	32	redbear	`+--------------------------------------------------------------+--------+--------------------------+`
123
124
125			`+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
126			`; Clocks ;`
127			`+----------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------+`
128			`; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;`
129			`+----------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------+`
130			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; Base ; 4.000 ; 250.0 MHz ; 0.000 ; 2.000 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i } ;`
131			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; Base ; 3.000 ; 333.33 MHz ; 0.000 ; 1.500 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i } ;`
132			`; din_a ; Base ; 3.000 ; 333.33 MHz ; 0.000 ; 1.500 ; ; ; ; ; ; ; ; ; ; ; { din_a } ;`
133			`; FPGA_CLK1_50 ; Base ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; ; ; ; ; ; ; ; ; ; ; { FPGA_CLK1_50 } ;`
134			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; Base ; 3.000 ; 333.33 MHz ; 0.000 ; 1.500 ; ; ; ; ; ; ; ; ; ; ; { spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e } ;`
135			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 1 ; 1 ; ; ; ; ; false ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|vco0ph[0] ; { u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk } ;`
136			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 2 ; 8 ; ; ; ; ; false ; FPGA_CLK1_50 ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|refclkin ; { u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] } ;`
137			`+----------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------+`
138
139
140			`+----------------------------------------------------+`
141			`; Slow 1100mV 85C Model Fmax Summary ;`
142			`+------------+-----------------+--------------+------+`
143			`; Fmax ; Restricted Fmax ; Clock Name ; Note ;`
144			`+------------+-----------------+--------------+------+`
145	35	redbear	`; 113.58 MHz ; 113.58 MHz ; FPGA_CLK1_50 ; ;`
146	32	redbear	`+------------+-----------------+--------------+------+`
147			This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
148
149
150			`----------------------------------`
151			`; Timing Closure Recommendations ;`
152			`----------------------------------`
153			`HTML report is unavailable in plain text report export.`
154
155
156			`+--------------------------------------+`
157			`; Slow 1100mV 85C Model Setup Summary ;`
158			`+--------------+-------+---------------+`
159			`; Clock ; Slack ; End Point TNS ;`
160			`+--------------+-------+---------------+`
161	35	redbear	`; FPGA_CLK1_50 ; 1.196 ; 0.000 ;`
162	32	redbear	`+--------------+-------+---------------+`
163
164
165			`+--------------------------------------+`
166			`; Slow 1100mV 85C Model Hold Summary ;`
167			`+--------------+-------+---------------+`
168			`; Clock ; Slack ; End Point TNS ;`
169			`+--------------+-------+---------------+`
170	35	redbear	`; FPGA_CLK1_50 ; 0.271 ; 0.000 ;`
171	32	redbear	`+--------------+-------+---------------+`
172
173
174			`+----------------------------------------+`
175			`; Slow 1100mV 85C Model Recovery Summary ;`
176			`+--------------+-------+-----------------+`
177			`; Clock ; Slack ; End Point TNS ;`
178			`+--------------+-------+-----------------+`
179	35	redbear	`; FPGA_CLK1_50 ; 4.785 ; 0.000 ;`
180	32	redbear	`+--------------+-------+-----------------+`
181
182
183			`+---------------------------------------+`
184			`; Slow 1100mV 85C Model Removal Summary ;`
185			`+--------------+-------+----------------+`
186			`; Clock ; Slack ; End Point TNS ;`
187			`+--------------+-------+----------------+`
188	35	redbear	`; FPGA_CLK1_50 ; 0.979 ; 0.000 ;`
189	32	redbear	`+--------------+-------+----------------+`
190
191
192			`+----------------------------------------------------------------------------------------------------+`
193			`; Slow 1100mV 85C Model Minimum Pulse Width Summary ;`
194			`+----------------------------------------------------------------------------+-------+---------------+`
195			`; Clock ; Slack ; End Point TNS ;`
196			`+----------------------------------------------------------------------------+-------+---------------+`
197	35	redbear	`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.538 ; 0.000 ;`
198			`; din_a ; 0.597 ; 0.000 ;`
199			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.657 ; 0.000 ;`
200			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; 0.679 ; 0.000 ;`
201			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 1.084 ; 0.000 ;`
202	32	redbear	`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; 1.250 ; 0.000 ;`
203			`; FPGA_CLK1_50 ; 4.202 ; 0.000 ;`
204			`+----------------------------------------------------------------------------+-------+---------------+`
205
206
207			`-----------------------------------------------`
208			`; Slow 1100mV 85C Model Metastability Summary ;`
209			`-----------------------------------------------`
210			`The design MTBF is not calculated because there are no specified synchronizers in the design.`
211			`Number of Synchronizer Chains Found: 59`
212			`Shortest Synchronizer Chain: 2 Registers`
213			`Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
214	35	redbear	`Worst Case Available Settling Time: 12.106 ns`
215	32	redbear
216
217
218
219			`+----------------------------------------------------+`
220			`; Slow 1100mV 0C Model Fmax Summary ;`
221			`+------------+-----------------+--------------+------+`
222			`; Fmax ; Restricted Fmax ; Clock Name ; Note ;`
223			`+------------+-----------------+--------------+------+`
224	35	redbear	`; 113.69 MHz ; 113.69 MHz ; FPGA_CLK1_50 ; ;`
225	32	redbear	`+------------+-----------------+--------------+------+`
226			This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
227
228
229			`+--------------------------------------+`
230			`; Slow 1100mV 0C Model Setup Summary ;`
231			`+--------------+-------+---------------+`
232			`; Clock ; Slack ; End Point TNS ;`
233			`+--------------+-------+---------------+`
234	35	redbear	`; FPGA_CLK1_50 ; 1.204 ; 0.000 ;`
235	32	redbear	`+--------------+-------+---------------+`
236
237
238			`+--------------------------------------+`
239			`; Slow 1100mV 0C Model Hold Summary ;`
240			`+--------------+-------+---------------+`
241			`; Clock ; Slack ; End Point TNS ;`
242			`+--------------+-------+---------------+`
243	35	redbear	`; FPGA_CLK1_50 ; 0.253 ; 0.000 ;`
244	32	redbear	`+--------------+-------+---------------+`
245
246
247			`+---------------------------------------+`
248			`; Slow 1100mV 0C Model Recovery Summary ;`
249			`+--------------+-------+----------------+`
250			`; Clock ; Slack ; End Point TNS ;`
251			`+--------------+-------+----------------+`
252	35	redbear	`; FPGA_CLK1_50 ; 4.852 ; 0.000 ;`
253	32	redbear	`+--------------+-------+----------------+`
254
255
256			`+--------------------------------------+`
257			`; Slow 1100mV 0C Model Removal Summary ;`
258			`+--------------+-------+---------------+`
259			`; Clock ; Slack ; End Point TNS ;`
260			`+--------------+-------+---------------+`
261	35	redbear	`; FPGA_CLK1_50 ; 0.920 ; 0.000 ;`
262	32	redbear	`+--------------+-------+---------------+`
263
264
265			`+----------------------------------------------------------------------------------------------------+`
266			`; Slow 1100mV 0C Model Minimum Pulse Width Summary ;`
267			`+----------------------------------------------------------------------------+-------+---------------+`
268			`; Clock ; Slack ; End Point TNS ;`
269			`+----------------------------------------------------------------------------+-------+---------------+`
270	35	redbear	`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.465 ; 0.000 ;`
271			`; din_a ; 0.633 ; 0.000 ;`
272			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.663 ; 0.000 ;`
273			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; 0.716 ; 0.000 ;`
274			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 1.117 ; 0.000 ;`
275	32	redbear	`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; 1.250 ; 0.000 ;`
276			`; FPGA_CLK1_50 ; 4.284 ; 0.000 ;`
277			`+----------------------------------------------------------------------------+-------+---------------+`
278
279
280			`----------------------------------------------`
281			`; Slow 1100mV 0C Model Metastability Summary ;`
282			`----------------------------------------------`
283			`The design MTBF is not calculated because there are no specified synchronizers in the design.`
284			`Number of Synchronizer Chains Found: 59`
285			`Shortest Synchronizer Chain: 2 Registers`
286			`Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
287	35	redbear	`Worst Case Available Settling Time: 12.241 ns`
288	32	redbear
289
290
291
292			`+--------------------------------------+`
293			`; Fast 1100mV 85C Model Setup Summary ;`
294			`+--------------+-------+---------------+`
295			`; Clock ; Slack ; End Point TNS ;`
296			`+--------------+-------+---------------+`
297	35	redbear	`; FPGA_CLK1_50 ; 4.542 ; 0.000 ;`
298	32	redbear	`+--------------+-------+---------------+`
299
300
301			`+--------------------------------------+`
302			`; Fast 1100mV 85C Model Hold Summary ;`
303			`+--------------+-------+---------------+`
304			`; Clock ; Slack ; End Point TNS ;`
305			`+--------------+-------+---------------+`
306	35	redbear	`; FPGA_CLK1_50 ; 0.162 ; 0.000 ;`
307	32	redbear	`+--------------+-------+---------------+`
308
309
310			`+----------------------------------------+`
311			`; Fast 1100mV 85C Model Recovery Summary ;`
312			`+--------------+-------+-----------------+`
313			`; Clock ; Slack ; End Point TNS ;`
314			`+--------------+-------+-----------------+`
315	35	redbear	`; FPGA_CLK1_50 ; 6.857 ; 0.000 ;`
316	32	redbear	`+--------------+-------+-----------------+`
317
318
319			`+---------------------------------------+`
320			`; Fast 1100mV 85C Model Removal Summary ;`
321			`+--------------+-------+----------------+`
322			`; Clock ; Slack ; End Point TNS ;`
323			`+--------------+-------+----------------+`
324	35	redbear	`; FPGA_CLK1_50 ; 0.574 ; 0.000 ;`
325	32	redbear	`+--------------+-------+----------------+`
326
327
328			`+----------------------------------------------------------------------------------------------------+`
329			`; Fast 1100mV 85C Model Minimum Pulse Width Summary ;`
330			`+----------------------------------------------------------------------------+-------+---------------+`
331			`; Clock ; Slack ; End Point TNS ;`
332			`+----------------------------------------------------------------------------+-------+---------------+`
333			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.799 ; 0.000 ;`
334	35	redbear	`; din_a ; 0.812 ; 0.000 ;`
335			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; 0.897 ; 0.000 ;`
336			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.920 ; 0.000 ;`
337	32	redbear	`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; 1.250 ; 0.000 ;`
338	35	redbear	`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 1.333 ; 0.000 ;`
339	32	redbear	`; FPGA_CLK1_50 ; 4.076 ; 0.000 ;`
340			`+----------------------------------------------------------------------------+-------+---------------+`
341
342
343			`-----------------------------------------------`
344			`; Fast 1100mV 85C Model Metastability Summary ;`
345			`-----------------------------------------------`
346			`The design MTBF is not calculated because there are no specified synchronizers in the design.`
347			`Number of Synchronizer Chains Found: 59`
348			`Shortest Synchronizer Chain: 2 Registers`
349			`Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
350	35	redbear	`Worst Case Available Settling Time: 15.202 ns`
351	32	redbear
352
353
354
355			`+--------------------------------------+`
356			`; Fast 1100mV 0C Model Setup Summary ;`
357			`+--------------+-------+---------------+`
358			`; Clock ; Slack ; End Point TNS ;`
359			`+--------------+-------+---------------+`
360	35	redbear	`; FPGA_CLK1_50 ; 5.038 ; 0.000 ;`
361	32	redbear	`+--------------+-------+---------------+`
362
363
364			`+--------------------------------------+`
365			`; Fast 1100mV 0C Model Hold Summary ;`
366			`+--------------+-------+---------------+`
367			`; Clock ; Slack ; End Point TNS ;`
368			`+--------------+-------+---------------+`
369	35	redbear	`; FPGA_CLK1_50 ; 0.146 ; 0.000 ;`
370	32	redbear	`+--------------+-------+---------------+`
371
372
373			`+---------------------------------------+`
374			`; Fast 1100mV 0C Model Recovery Summary ;`
375			`+--------------+-------+----------------+`
376			`; Clock ; Slack ; End Point TNS ;`
377			`+--------------+-------+----------------+`
378			`; FPGA_CLK1_50 ; 7.031 ; 0.000 ;`
379			`+--------------+-------+----------------+`
380
381
382			`+--------------------------------------+`
383			`; Fast 1100mV 0C Model Removal Summary ;`
384			`+--------------+-------+---------------+`
385			`; Clock ; Slack ; End Point TNS ;`
386			`+--------------+-------+---------------+`
387	35	redbear	`; FPGA_CLK1_50 ; 0.524 ; 0.000 ;`
388	32	redbear	`+--------------+-------+---------------+`
389
390
391			`+----------------------------------------------------------------------------------------------------+`
392			`; Fast 1100mV 0C Model Minimum Pulse Width Summary ;`
393			`+----------------------------------------------------------------------------+-------+---------------+`
394			`; Clock ; Slack ; End Point TNS ;`
395			`+----------------------------------------------------------------------------+-------+---------------+`
396	35	redbear	`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; 0.793 ; 0.000 ;`
397			`; din_a ; 0.828 ; 0.000 ;`
398			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; 0.961 ; 0.000 ;`
399			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0.969 ; 0.000 ;`
400	32	redbear	`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; 1.250 ; 0.000 ;`
401	35	redbear	`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; 1.399 ; 0.000 ;`
402	32	redbear	`; FPGA_CLK1_50 ; 4.039 ; 0.000 ;`
403			`+----------------------------------------------------------------------------+-------+---------------+`
404
405
406			`----------------------------------------------`
407			`; Fast 1100mV 0C Model Metastability Summary ;`
408			`----------------------------------------------`
409			`The design MTBF is not calculated because there are no specified synchronizers in the design.`
410			`Number of Synchronizer Chains Found: 59`
411			`Shortest Synchronizer Chain: 2 Registers`
412			`Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
413	35	redbear	`Worst Case Available Settling Time: 15.621 ns`
414	32	redbear
415
416
417
418			`+----------------------------------------------------------------------------------------------------------------------------------------+`
419			`; Multicorner Timing Analysis Summary ;`
420			`+-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+`
421			`; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;`
422			`+-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+`
423	35	redbear	`; Worst-case Slack ; 1.196 ; 0.146 ; 4.785 ; 0.524 ; 0.465 ;`
424			`; FPGA_CLK1_50 ; 1.196 ; 0.146 ; 4.785 ; 0.524 ; 4.039 ;`
425			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; N/A ; N/A ; N/A ; N/A ; 1.084 ;`
426			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; N/A ; N/A ; N/A ; N/A ; 0.657 ;`
427			`; din_a ; N/A ; N/A ; N/A ; N/A ; 0.597 ;`
428			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; N/A ; N/A ; N/A ; N/A ; 0.679 ;`
429			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; N/A ; N/A ; N/A ; N/A ; 0.465 ;`
430	32	redbear	`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.250 ;`
431			`; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;`
432			`; FPGA_CLK1_50 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ;`
433			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; N/A ; N/A ; N/A ; N/A ; 0.000 ;`
434			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; N/A ; N/A ; N/A ; N/A ; 0.000 ;`
435			`; din_a ; N/A ; N/A ; N/A ; N/A ; 0.000 ;`
436			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; N/A ; N/A ; N/A ; N/A ; 0.000 ;`
437			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; N/A ; N/A ; N/A ; N/A ; 0.000 ;`
438			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ;`
439			`+-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+`
440
441
442			`+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
443			`; Board Trace Model Assignments ;`
444			`+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+`
445			`; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;`
446			`+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+`
447	35	redbear	`; dout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;`
448			`; sout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;`
449	32	redbear	`; LED[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
450			`; LED[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
451			`; LED[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
452			`; LED[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
453			`; LED[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
454			`; LED[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
455			`; LED[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
456			`; LED[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;`
457			`; dout_a(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;`
458			`; sout_a(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;`
459			`+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+`
460
461
462			`+-----------------------------------------------------------------+`
463			`; Input Transition Times ;`
464			`+--------------+--------------+-----------------+-----------------+`
465			`; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;`
466			`+--------------+--------------+-----------------+-----------------+`
467			`; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;`
468			`; FPGA_CLK1_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;`
469			`; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;`
470			`; din_a ; LVDS ; 2000 ps ; 2000 ps ;`
471			`; sin_a ; LVDS ; 2000 ps ; 2000 ps ;`
472			`; din_a(n) ; LVDS ; 2000 ps ; 2000 ps ;`
473			`; sin_a(n) ; LVDS ; 2000 ps ; 2000 ps ;`
474			`+--------------+--------------+-----------------+-----------------+`
475
476
477			+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
478			; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
479			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
480			; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
481			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
482	35	redbear	; dout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;
483			; sout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;
484	32	redbear	; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
485			; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
486			; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
487			; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
488			; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
489			; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
490			; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;
491			; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
492			; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;
493			; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;
494			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
495
496
497			+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
498			; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
499			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
500			; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
501			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
502	35	redbear	; dout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;
503			; sout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;
504	32	redbear	; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
505			; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;
506			; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
507			; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
508			; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
509			; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
510			; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;
511			; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
512			; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;
513			; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;
514			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
515
516
517			+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
518			; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
519			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
520			; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
521			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
522	35	redbear	; dout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;
523			; sout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;
524	32	redbear	; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
525			; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
526			; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
527			; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
528			; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
529			; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
530			; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;
531			; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
532			; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;
533			; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;
534			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
535
536
537			+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
538			; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
539			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
540			; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
541			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
542	35	redbear	; dout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;
543			; sout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;
544	32	redbear	; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
545			; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
546			; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
547			; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
548			; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
549			; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
550			; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;
551			; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
552			; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;
553			; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;
554			+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
555
556
557			`+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
558			`; Setup Transfers ;`
559			`+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+`
560			`; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;`
561			`+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+`
562			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
563			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
564			`; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; false path ; 0 ; 0 ;`
565			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
566			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;`
567			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;`
568			`; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0 ; false path ; 0 ; 0 ;`
569			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; false path ; 0 ;`
570			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; false path ; 0 ; 0 ;`
571			`; din_a ; din_a ; false path ; false path ; false path ; false path ;`
572			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;`
573			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;`
574			`; din_a ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;`
575	35	redbear	`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 198264 ; 0 ; 0 ; 0 ;`
576	32	redbear	`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;`
577			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; false path ; 0 ; false path ; 0 ;`
578			`; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; false path ; 0 ; false path ; 0 ;`
579			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; false path ; false path ; false path ; false path ;`
580			`; FPGA_CLK1_50 ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; false path ; 0 ; 0 ; 0 ;`
581			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; false path ; 0 ; 0 ; 0 ;`
582			`+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+`
583			`Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.`
584
585
586			`+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
587			`; Hold Transfers ;`
588			`+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+`
589			`; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;`
590			`+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+`
591			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
592			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
593			`; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; false path ; 0 ; 0 ;`
594			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
595			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;`
596			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;`
597			`; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; 0 ; false path ; 0 ; 0 ;`
598			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; false path ; 0 ;`
599			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; false path ; 0 ; 0 ;`
600			`; din_a ; din_a ; false path ; false path ; false path ; false path ;`
601			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;`
602			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;`
603			`; din_a ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;`
604	35	redbear	`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 198264 ; 0 ; 0 ; 0 ;`
605	32	redbear	`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;`
606			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; false path ; 0 ; false path ; 0 ;`
607			`; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; false path ; 0 ; false path ; 0 ;`
608			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; false path ; false path ; false path ; false path ;`
609			`; FPGA_CLK1_50 ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; false path ; 0 ; 0 ; 0 ;`
610			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; false path ; 0 ; 0 ; 0 ;`
611			`+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+`
612			`Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.`
613
614
615			`+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
616			`; Recovery Transfers ;`
617			`+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+`
618			`; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;`
619			`+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+`
620			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
621			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
622			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;`
623			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; din_a ; 100 ; 0 ; 69 ; 0 ;`
624			`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3102 ; 0 ; 0 ; 0 ;`
625			`; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; false path ; 0 ; false path ; 0 ;`
626			`+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+`
627			`Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.`
628
629
630			`+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
631			`; Removal Transfers ;`
632			`+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+`
633			`; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;`
634			`+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+`
635			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
636			`; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;`
637			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;`
638			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; din_a ; 100 ; 0 ; 69 ; 0 ;`
639			`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3102 ; 0 ; 0 ; 0 ;`
640			`; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; false path ; 0 ; false path ; 0 ;`
641			`+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+`
642			`Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.`
643
644
645			`---------------`
646			`; Report TCCS ;`
647			`---------------`
648			`No dedicated SERDES Transmitter circuitry present in device or used in design`
649
650
651			`---------------`
652			`; Report RSKM ;`
653			`---------------`
654			`No non-DPA dedicated SERDES Receiver circuitry present in device or used in design`
655
656
657			`+------------------------------------------------+`
658			`; Unconstrained Paths Summary ;`
659			`+---------------------------------+-------+------+`
660			`; Property ; Setup ; Hold ;`
661			`+---------------------------------+-------+------+`
662			`; Illegal Clocks ; 0 ; 0 ;`
663			`; Unconstrained Clocks ; 0 ; 0 ;`
664			`; Unconstrained Input Ports ; 2 ; 2 ;`
665			`; Unconstrained Input Port Paths ; 36 ; 36 ;`
666			`; Unconstrained Output Ports ; 10 ; 10 ;`
667			`; Unconstrained Output Port Paths ; 10 ; 10 ;`
668			`+---------------------------------+-------+------+`
669
670
671			`+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+`
672			`; Clock Status Summary ;`
673			`+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------+-------------+`
674			`; Target ; Clock ; Type ; Status ;`
675			`+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------+-------------+`
676			`; FPGA_CLK1_50 ; FPGA_CLK1_50 ; Base ; Constrained ;`
677			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i ; Base ; Constrained ;`
678			`; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i ; Base ; Constrained ;`
679			`; din_a ; din_a ; Base ; Constrained ;`
680			`; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e ; Base ; Constrained ;`
681			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk ; Generated ; Constrained ;`
682			`; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0] ; Generated ; Constrained ;`
683			`+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------+-------------+`
684
685
686			`+---------------------------------------------------------------------------------------------------+`
687			`; Unconstrained Input Ports ;`
688			`+------------+--------------------------------------------------------------------------------------+`
689			`; Input Port ; Comment ;`
690			`+------------+--------------------------------------------------------------------------------------+`
691			`; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;`
692			`; sin_a ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;`
693			`+------------+--------------------------------------------------------------------------------------+`
694
695
696			`+-----------------------------------------------------------------------------------------------------+`
697			`; Unconstrained Output Ports ;`
698			`+-------------+---------------------------------------------------------------------------------------+`
699			`; Output Port ; Comment ;`
700			`+-------------+---------------------------------------------------------------------------------------+`
701			`; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
702			`; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
703			`; LED[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
704			`; LED[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
705			`; LED[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
706			`; LED[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
707			`; dout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
708			`; dout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
709			`; sout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
710			`; sout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
711			`+-------------+---------------------------------------------------------------------------------------+`
712
713
714			`+---------------------------------------------------------------------------------------------------+`
715			`; Unconstrained Input Ports ;`
716			`+------------+--------------------------------------------------------------------------------------+`
717			`; Input Port ; Comment ;`
718			`+------------+--------------------------------------------------------------------------------------+`
719			`; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;`
720			`; sin_a ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;`
721			`+------------+--------------------------------------------------------------------------------------+`
722
723
724			`+-----------------------------------------------------------------------------------------------------+`
725			`; Unconstrained Output Ports ;`
726			`+-------------+---------------------------------------------------------------------------------------+`
727			`; Output Port ; Comment ;`
728			`+-------------+---------------------------------------------------------------------------------------+`
729			`; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
730			`; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
731			`; LED[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
732			`; LED[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
733			`; LED[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
734			`; LED[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
735			`; dout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
736			`; dout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
737			`; sout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
738			`; sout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;`
739			`+-------------+---------------------------------------------------------------------------------------+`
740
741
742			`+------------------------------------+`
743			`; TimeQuest Timing Analyzer Messages ;`
744			`+------------------------------------+`
745			`Info: *******************************************************************`
746			`Info: Running Quartus Prime TimeQuest Timing Analyzer`
747			`Info: Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition`
748	35	redbear	`Info: Processing started: Fri Sep 15 08:18:16 2017`
749	32	redbear	`Info: Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulight`
750			`Info: qsta_default_script.tcl version: #1`
751			`Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.`
752			`Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected`
753			`Info (21077): Low junction temperature is 0 degrees C`
754			`Info (21077): High junction temperature is 85 degrees C`
755			`Info (334003): Started post-fitting delay annotation`
756			`Info (334004): Delay annotation completed successfully`
757			`Info (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'`
758			`Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'`
759			`Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.`
760			`Info (332098): Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout`
761			`Info (332098): Cell: m_x\|always3~0 from: dataf to: combout`
762			`Info (332098): From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457`
763			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter from: vco0ph[0] to: divclk`
764			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin[0] to: clkout`
765			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk`
766			`Info (332152): The following assignments are ignored by the derive_clock_uncertainty command`
767			`Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON`
768			`Info: Analyzing Slow 1100mV 85C Model`
769	35	redbear	`Info (332146): Worst-case setup slack is 1.196`
770	32	redbear	`Info (332119): Slack End Point TNS Clock`
771			`Info (332119): ========= =================== =====================`
772	35	redbear	`Info (332119): 1.196 0.000 FPGA_CLK1_50`
773			`Info (332146): Worst-case hold slack is 0.271`
774	32	redbear	`Info (332119): Slack End Point TNS Clock`
775			`Info (332119): ========= =================== =====================`
776	35	redbear	`Info (332119): 0.271 0.000 FPGA_CLK1_50`
777			`Info (332146): Worst-case recovery slack is 4.785`
778	32	redbear	`Info (332119): Slack End Point TNS Clock`
779			`Info (332119): ========= =================== =====================`
780	35	redbear	`Info (332119): 4.785 0.000 FPGA_CLK1_50`
781			`Info (332146): Worst-case removal slack is 0.979`
782	32	redbear	`Info (332119): Slack End Point TNS Clock`
783			`Info (332119): ========= =================== =====================`
784	35	redbear	`Info (332119): 0.979 0.000 FPGA_CLK1_50`
785			`Info (332146): Worst-case minimum pulse width slack is 0.538`
786	32	redbear	`Info (332119): Slack End Point TNS Clock`
787			`Info (332119): ========= =================== =====================`
788	35	redbear	`Info (332119): 0.538 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
789			`Info (332119): 0.597 0.000 din_a`
790			`Info (332119): 0.657 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
791			`Info (332119): 0.679 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e`
792			`Info (332119): 1.084 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
793	32	redbear	`Info (332119): 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]`
794			`Info (332119): 4.202 0.000 FPGA_CLK1_50`
795			`Info (332114): Report Metastability: Found 59 synchronizer chains.`
796			`Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.`
797			`Info (332114): Number of Synchronizer Chains Found: 59`
798			`Info (332114): Shortest Synchronizer Chain: 2 Registers`
799			`Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
800	35	redbear	`Info (332114): Worst Case Available Settling Time: 12.106 ns`
801	32	redbear	`Info (332114):`
802			`Info: Analyzing Slow 1100mV 0C Model`
803			`Info (334003): Started post-fitting delay annotation`
804			`Info (334004): Delay annotation completed successfully`
805			`Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.`
806			`Info (332098): Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout`
807			`Info (332098): Cell: m_x\|always3~0 from: dataf to: combout`
808			`Info (332098): From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457`
809			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter from: vco0ph[0] to: divclk`
810			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin[0] to: clkout`
811			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk`
812			`Info (332152): The following assignments are ignored by the derive_clock_uncertainty command`
813	35	redbear	`Info (332146): Worst-case setup slack is 1.204`
814	32	redbear	`Info (332119): Slack End Point TNS Clock`
815			`Info (332119): ========= =================== =====================`
816	35	redbear	`Info (332119): 1.204 0.000 FPGA_CLK1_50`
817			`Info (332146): Worst-case hold slack is 0.253`
818	32	redbear	`Info (332119): Slack End Point TNS Clock`
819			`Info (332119): ========= =================== =====================`
820	35	redbear	`Info (332119): 0.253 0.000 FPGA_CLK1_50`
821			`Info (332146): Worst-case recovery slack is 4.852`
822	32	redbear	`Info (332119): Slack End Point TNS Clock`
823			`Info (332119): ========= =================== =====================`
824	35	redbear	`Info (332119): 4.852 0.000 FPGA_CLK1_50`
825			`Info (332146): Worst-case removal slack is 0.920`
826	32	redbear	`Info (332119): Slack End Point TNS Clock`
827			`Info (332119): ========= =================== =====================`
828	35	redbear	`Info (332119): 0.920 0.000 FPGA_CLK1_50`
829			`Info (332146): Worst-case minimum pulse width slack is 0.465`
830	32	redbear	`Info (332119): Slack End Point TNS Clock`
831			`Info (332119): ========= =================== =====================`
832	35	redbear	`Info (332119): 0.465 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
833			`Info (332119): 0.633 0.000 din_a`
834			`Info (332119): 0.663 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
835			`Info (332119): 0.716 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e`
836			`Info (332119): 1.117 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
837	32	redbear	`Info (332119): 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]`
838			`Info (332119): 4.284 0.000 FPGA_CLK1_50`
839			`Info (332114): Report Metastability: Found 59 synchronizer chains.`
840			`Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.`
841			`Info (332114): Number of Synchronizer Chains Found: 59`
842			`Info (332114): Shortest Synchronizer Chain: 2 Registers`
843			`Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
844	35	redbear	`Info (332114): Worst Case Available Settling Time: 12.241 ns`
845	32	redbear	`Info (332114):`
846			`Info: Analyzing Fast 1100mV 85C Model`
847			`Info (334003): Started post-fitting delay annotation`
848			`Info (334004): Delay annotation completed successfully`
849			`Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.`
850			`Info (332098): Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout`
851			`Info (332098): Cell: m_x\|always3~0 from: dataf to: combout`
852			`Info (332098): From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457`
853			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter from: vco0ph[0] to: divclk`
854			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin[0] to: clkout`
855			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk`
856			`Info (332152): The following assignments are ignored by the derive_clock_uncertainty command`
857	35	redbear	`Info (332146): Worst-case setup slack is 4.542`
858	32	redbear	`Info (332119): Slack End Point TNS Clock`
859			`Info (332119): ========= =================== =====================`
860	35	redbear	`Info (332119): 4.542 0.000 FPGA_CLK1_50`
861			`Info (332146): Worst-case hold slack is 0.162`
862	32	redbear	`Info (332119): Slack End Point TNS Clock`
863			`Info (332119): ========= =================== =====================`
864	35	redbear	`Info (332119): 0.162 0.000 FPGA_CLK1_50`
865			`Info (332146): Worst-case recovery slack is 6.857`
866	32	redbear	`Info (332119): Slack End Point TNS Clock`
867			`Info (332119): ========= =================== =====================`
868	35	redbear	`Info (332119): 6.857 0.000 FPGA_CLK1_50`
869			`Info (332146): Worst-case removal slack is 0.574`
870	32	redbear	`Info (332119): Slack End Point TNS Clock`
871			`Info (332119): ========= =================== =====================`
872	35	redbear	`Info (332119): 0.574 0.000 FPGA_CLK1_50`
873			`Info (332146): Worst-case minimum pulse width slack is 0.799`
874	32	redbear	`Info (332119): Slack End Point TNS Clock`
875			`Info (332119): ========= =================== =====================`
876			`Info (332119): 0.799 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
877	35	redbear	`Info (332119): 0.812 0.000 din_a`
878			`Info (332119): 0.897 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e`
879			`Info (332119): 0.920 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
880	32	redbear	`Info (332119): 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]`
881	35	redbear	`Info (332119): 1.333 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
882	32	redbear	`Info (332119): 4.076 0.000 FPGA_CLK1_50`
883			`Info (332114): Report Metastability: Found 59 synchronizer chains.`
884			`Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.`
885			`Info (332114): Number of Synchronizer Chains Found: 59`
886			`Info (332114): Shortest Synchronizer Chain: 2 Registers`
887			`Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
888	35	redbear	`Info (332114): Worst Case Available Settling Time: 15.202 ns`
889	32	redbear	`Info (332114):`
890			`Info: Analyzing Fast 1100mV 0C Model`
891			`Info (334003): Started post-fitting delay annotation`
892			`Info (334004): Delay annotation completed successfully`
893			`Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.`
894			`Info (332098): Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout`
895			`Info (332098): Cell: m_x\|always3~0 from: dataf to: combout`
896			`Info (332098): From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457`
897			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter from: vco0ph[0] to: divclk`
898			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin[0] to: clkout`
899			`Info (332098): Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk`
900			`Info (332152): The following assignments are ignored by the derive_clock_uncertainty command`
901	35	redbear	`Info (332146): Worst-case setup slack is 5.038`
902	32	redbear	`Info (332119): Slack End Point TNS Clock`
903			`Info (332119): ========= =================== =====================`
904	35	redbear	`Info (332119): 5.038 0.000 FPGA_CLK1_50`
905			`Info (332146): Worst-case hold slack is 0.146`
906	32	redbear	`Info (332119): Slack End Point TNS Clock`
907			`Info (332119): ========= =================== =====================`
908	35	redbear	`Info (332119): 0.146 0.000 FPGA_CLK1_50`
909	32	redbear	`Info (332146): Worst-case recovery slack is 7.031`
910			`Info (332119): Slack End Point TNS Clock`
911			`Info (332119): ========= =================== =====================`
912			`Info (332119): 7.031 0.000 FPGA_CLK1_50`
913	35	redbear	`Info (332146): Worst-case removal slack is 0.524`
914	32	redbear	`Info (332119): Slack End Point TNS Clock`
915			`Info (332119): ========= =================== =====================`
916	35	redbear	`Info (332119): 0.524 0.000 FPGA_CLK1_50`
917			`Info (332146): Worst-case minimum pulse width slack is 0.793`
918	32	redbear	`Info (332119): Slack End Point TNS Clock`
919			`Info (332119): ========= =================== =====================`
920	35	redbear	`Info (332119): 0.793 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk`
921			`Info (332119): 0.828 0.000 din_a`
922			`Info (332119): 0.961 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e`
923			`Info (332119): 0.969 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i`
924	32	redbear	`Info (332119): 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]`
925	35	redbear	`Info (332119): 1.399 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i`
926	32	redbear	`Info (332119): 4.039 0.000 FPGA_CLK1_50`
927			`Info (332114): Report Metastability: Found 59 synchronizer chains.`
928			`Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.`
929			`Info (332114): Number of Synchronizer Chains Found: 59`
930			`Info (332114): Shortest Synchronizer Chain: 2 Registers`
931			`Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000`
932	35	redbear	`Info (332114): Worst Case Available Settling Time: 15.621 ns`
933	32	redbear	`Info (332114):`
934			`Info (332102): Design is not fully constrained for setup requirements`
935			`Info (332102): Design is not fully constrained for hold requirements`
936			`Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 1 warning`
937			`Info: Peak virtual memory: 1351 megabytes`
938	35	redbear	`Info: Processing ended: Fri Sep 15 08:19:10 2017`
939			`Info: Elapsed time: 00:00:54`
940			`Info: Total CPU time (on all processors): 00:01:15`
941	32	redbear
942

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