Subversion Repositories spacewiresystemc

# -------------------------------------------------------------------------- #

#

# Copyright (C) 2017  Intel Corporation. All rights reserved.

# Your use of Intel Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Intel Program License

# Subscription Agreement, the Intel Quartus Prime License Agreement,

# the Intel MegaCore Function License Agreement, or other

# applicable license agreement, including, without limitation,

# that your use is for the sole purpose of programming logic

# devices manufactured by Intel and sold by Intel or its

# authorized distributors.  Please refer to the applicable

# agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus Prime

# Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition

# Date created = 11:59:04  August 14, 2017

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               spw_fifo_ulight_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus Prime software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone V"

set_global_assignment -name DEVICE 5CSEMA4U23C6

set_global_assignment -name TOP_LEVEL_ENTITY SPW_ULIGHT_FIFO

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.1

set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:59:04  AUGUST 14, 2017"

set_global_assignment -name LAST_QUARTUS_VERSION "17.0.1 Lite Edition"

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"

set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50

set_location_assignment PIN_Y13 -to FPGA_CLK1_50

set_location_assignment PIN_AH16 -to KEY[1]

set_location_assignment PIN_AH17 -to KEY[0]

set_location_assignment PIN_AA23 -to LED[7]

set_location_assignment PIN_Y16 -to LED[6]

set_location_assignment PIN_AE26 -to LED[5]

set_location_assignment PIN_AF26 -to LED[4]

set_location_assignment PIN_V15 -to LED[3]

set_location_assignment PIN_V16 -to LED[2]

set_location_assignment PIN_AA24 -to LED[1]

set_location_assignment PIN_W15 -to LED[0]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED

set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM

set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 90.0

set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "EXTRA EFFORT"

set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING OFF

set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF

set_global_assignment -name AUTO_GLOBAL_CLOCK ON

set_global_assignment -name ALLOW_REGISTER_MERGING OFF

set_global_assignment -name ALLOW_REGISTER_DUPLICATION OFF

set_global_assignment -name AUTO_DELAY_CHAINS OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA

set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION OFF

set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS ON

set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"

set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED

set_instance_assignment -name IO_STANDARD LVDS -to din_a

set_instance_assignment -name IO_STANDARD LVDS -to dout_a

set_instance_assignment -name IO_STANDARD LVDS -to sin_a

set_instance_assignment -name IO_STANDARD LVDS -to sout_a

set_location_assignment PIN_Y15 -to din_a

set_location_assignment PIN_AA15 -to "din_a(n)"

set_location_assignment PIN_AG28 -to dout_a

set_location_assignment PIN_AH27 -to "dout_a(n)"

set_location_assignment PIN_AE20 -to sin_a

set_location_assignment PIN_AD20 -to "sin_a(n)"

set_location_assignment PIN_AF20 -to sout_a

set_location_assignment PIN_AG20 -to "sout_a(n)"

set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF

set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON

set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES OFF

set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF

set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF

set_global_assignment -name VERILOG_FILE ../../rtl/DEBUG_VERILOG/detector_tokens.v

set_global_assignment -name VERILOG_FILE ../../rtl/DEBUG_VERILOG/debounce.v

set_global_assignment -name VERILOG_FILE ../../rtl/DEBUG_VERILOG/clock_reduce.v

set_global_assignment -name VERILOG_FILE ../../rtl/RTL_VB/top_spw_ultra_light.v

set_global_assignment -name VERILOG_FILE ../../rtl/RTL_VB/spw_ulight_con_top_x.v

set_global_assignment -name VERILOG_FILE ../../rtl/RTL_VB/rx_spw.v

set_global_assignment -name VERILOG_FILE ../../rtl/RTL_VB/fsm_spw.v

set_global_assignment -name VERILOG_FILE ../../rtl/RTL_VB/fifo_tx.v

set_global_assignment -name VERILOG_FILE ../../rtl/RTL_VB/fifo_rx.v

set_global_assignment -name VERILOG_FILE ../../rtl/RTL_VB/tx_spw.v

set_global_assignment -name SDC_FILE sdc/spw_fifo_ulight.out.sdc

set_global_assignment -name QIP_FILE ulight_fifo/synthesis/ulight_fifo.qip

set_global_assignment -name VERILOG_FILE top_rtl/spw_fifo_ulight.v

set_global_assignment -name SEED 893763639

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top