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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [spw_ultra_light.h] - Blame information for rev 36

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1 32 redbear
#ifndef _ALTERA_SPW_ULTRA_LIGHT_H_
2
#define _ALTERA_SPW_ULTRA_LIGHT_H_
3
 
4
/*
5
 * This file was automatically generated by the swinfo2header utility.
6
 *
7
 * Created from SOPC Builder system 'ulight_fifo' in
8
 * file 'ulight_fifo.sopcinfo'.
9
 */
10
 
11
/*
12
 * This file contains macros for module 'hps_0' and devices
13
 * connected to the following master:
14
 *   h2f_axi_master
15
 *
16
 * Do not include this header file and another header file created for a
17
 * different module or master group at the same time.
18
 * Doing so may result in duplicate macro names.
19
 * Instead, use the system header file which has macros with unique names.
20
 */
21
 
22
/*
23
 * Macros for device 'led_pio_test', class 'altera_avalon_pio'
24
 * The macros are prefixed with 'LED_PIO_TEST_'.
25
 * The prefix is the slave descriptor.
26
 */
27
#define LED_PIO_TEST_COMPONENT_TYPE altera_avalon_pio
28
#define LED_PIO_TEST_COMPONENT_NAME led_pio_test
29
#define LED_PIO_TEST_BASE 0x0
30
#define LED_PIO_TEST_SPAN 16
31
#define LED_PIO_TEST_END 0xf
32
#define LED_PIO_TEST_BIT_CLEARING_EDGE_REGISTER 0
33
#define LED_PIO_TEST_BIT_MODIFYING_OUTPUT_REGISTER 0
34
#define LED_PIO_TEST_CAPTURE 0
35
#define LED_PIO_TEST_DATA_WIDTH 5
36
#define LED_PIO_TEST_DO_TEST_BENCH_WIRING 0
37
#define LED_PIO_TEST_DRIVEN_SIM_VALUE 0
38
#define LED_PIO_TEST_EDGE_TYPE NONE
39
#define LED_PIO_TEST_FREQ 50000000
40
#define LED_PIO_TEST_HAS_IN 0
41
#define LED_PIO_TEST_HAS_OUT 1
42
#define LED_PIO_TEST_HAS_TRI 0
43
#define LED_PIO_TEST_IRQ_TYPE NONE
44
#define LED_PIO_TEST_RESET_VALUE 0
45
 
46
/*
47
 * Macros for device 'timecode_rx', class 'altera_avalon_pio'
48
 * The macros are prefixed with 'TIMECODE_RX_'.
49
 * The prefix is the slave descriptor.
50
 */
51
#define TIMECODE_RX_COMPONENT_TYPE altera_avalon_pio
52
#define TIMECODE_RX_COMPONENT_NAME timecode_rx
53
#define TIMECODE_RX_BASE 0x10000
54
#define TIMECODE_RX_SPAN 16
55
#define TIMECODE_RX_END 0x1000f
56
#define TIMECODE_RX_BIT_CLEARING_EDGE_REGISTER 0
57
#define TIMECODE_RX_BIT_MODIFYING_OUTPUT_REGISTER 0
58
#define TIMECODE_RX_CAPTURE 0
59
#define TIMECODE_RX_DATA_WIDTH 8
60
#define TIMECODE_RX_DO_TEST_BENCH_WIRING 0
61
#define TIMECODE_RX_DRIVEN_SIM_VALUE 0
62
#define TIMECODE_RX_EDGE_TYPE NONE
63
#define TIMECODE_RX_FREQ 50000000
64
#define TIMECODE_RX_HAS_IN 1
65
#define TIMECODE_RX_HAS_OUT 0
66
#define TIMECODE_RX_HAS_TRI 0
67
#define TIMECODE_RX_IRQ_TYPE NONE
68
#define TIMECODE_RX_RESET_VALUE 0
69
 
70
/*
71
 * Macros for device 'timecode_tx_ready', class 'altera_avalon_pio'
72
 * The macros are prefixed with 'TIMECODE_TX_READY_'.
73
 * The prefix is the slave descriptor.
74
 */
75
#define TIMECODE_TX_READY_COMPONENT_TYPE altera_avalon_pio
76
#define TIMECODE_TX_READY_COMPONENT_NAME timecode_tx_ready
77
#define TIMECODE_TX_READY_BASE 0x1a000
78
#define TIMECODE_TX_READY_SPAN 16
79
#define TIMECODE_TX_READY_END 0x1a00f
80
#define TIMECODE_TX_READY_BIT_CLEARING_EDGE_REGISTER 0
81
#define TIMECODE_TX_READY_BIT_MODIFYING_OUTPUT_REGISTER 0
82
#define TIMECODE_TX_READY_CAPTURE 0
83
#define TIMECODE_TX_READY_DATA_WIDTH 1
84
#define TIMECODE_TX_READY_DO_TEST_BENCH_WIRING 0
85
#define TIMECODE_TX_READY_DRIVEN_SIM_VALUE 0
86
#define TIMECODE_TX_READY_EDGE_TYPE NONE
87
#define TIMECODE_TX_READY_FREQ 50000000
88
#define TIMECODE_TX_READY_HAS_IN 1
89
#define TIMECODE_TX_READY_HAS_OUT 0
90
#define TIMECODE_TX_READY_HAS_TRI 0
91
#define TIMECODE_TX_READY_IRQ_TYPE NONE
92
#define TIMECODE_TX_READY_RESET_VALUE 0
93
 
94
/*
95
 * Macros for device 'timecode_ready_rx', class 'altera_avalon_pio'
96
 * The macros are prefixed with 'TIMECODE_READY_RX_'.
97
 * The prefix is the slave descriptor.
98
 */
99
#define TIMECODE_READY_RX_COMPONENT_TYPE altera_avalon_pio
100
#define TIMECODE_READY_RX_COMPONENT_NAME timecode_ready_rx
101
#define TIMECODE_READY_RX_BASE 0x20000
102
#define TIMECODE_READY_RX_SPAN 16
103
#define TIMECODE_READY_RX_END 0x2000f
104
#define TIMECODE_READY_RX_BIT_CLEARING_EDGE_REGISTER 0
105
#define TIMECODE_READY_RX_BIT_MODIFYING_OUTPUT_REGISTER 0
106
#define TIMECODE_READY_RX_CAPTURE 0
107
#define TIMECODE_READY_RX_DATA_WIDTH 1
108
#define TIMECODE_READY_RX_DO_TEST_BENCH_WIRING 0
109
#define TIMECODE_READY_RX_DRIVEN_SIM_VALUE 0
110
#define TIMECODE_READY_RX_EDGE_TYPE NONE
111
#define TIMECODE_READY_RX_FREQ 50000000
112
#define TIMECODE_READY_RX_HAS_IN 1
113
#define TIMECODE_READY_RX_HAS_OUT 0
114
#define TIMECODE_READY_RX_HAS_TRI 0
115
#define TIMECODE_READY_RX_IRQ_TYPE NONE
116
#define TIMECODE_READY_RX_RESET_VALUE 0
117
 
118
/*
119
 * Macros for device 'data_info', class 'altera_avalon_pio'
120
 * The macros are prefixed with 'DATA_INFO_'.
121
 * The prefix is the slave descriptor.
122
 */
123
#define DATA_INFO_COMPONENT_TYPE altera_avalon_pio
124
#define DATA_INFO_COMPONENT_NAME data_info
125
#define DATA_INFO_BASE 0x2a000
126
#define DATA_INFO_SPAN 16
127
#define DATA_INFO_END 0x2a00f
128
#define DATA_INFO_BIT_CLEARING_EDGE_REGISTER 0
129
#define DATA_INFO_BIT_MODIFYING_OUTPUT_REGISTER 0
130
#define DATA_INFO_CAPTURE 0
131
#define DATA_INFO_DATA_WIDTH 14
132
#define DATA_INFO_DO_TEST_BENCH_WIRING 0
133
#define DATA_INFO_DRIVEN_SIM_VALUE 0
134
#define DATA_INFO_EDGE_TYPE NONE
135
#define DATA_INFO_FREQ 50000000
136
#define DATA_INFO_HAS_IN 1
137
#define DATA_INFO_HAS_OUT 0
138
#define DATA_INFO_HAS_TRI 0
139
#define DATA_INFO_IRQ_TYPE NONE
140
#define DATA_INFO_RESET_VALUE 0
141
 
142
/*
143
 * Macros for device 'data_flag_rx', class 'altera_avalon_pio'
144
 * The macros are prefixed with 'DATA_FLAG_RX_'.
145
 * The prefix is the slave descriptor.
146
 */
147
#define DATA_FLAG_RX_COMPONENT_TYPE altera_avalon_pio
148
#define DATA_FLAG_RX_COMPONENT_NAME data_flag_rx
149
#define DATA_FLAG_RX_BASE 0x30000
150
#define DATA_FLAG_RX_SPAN 16
151
#define DATA_FLAG_RX_END 0x3000f
152
#define DATA_FLAG_RX_BIT_CLEARING_EDGE_REGISTER 0
153
#define DATA_FLAG_RX_BIT_MODIFYING_OUTPUT_REGISTER 0
154
#define DATA_FLAG_RX_CAPTURE 0
155
#define DATA_FLAG_RX_DATA_WIDTH 9
156
#define DATA_FLAG_RX_DO_TEST_BENCH_WIRING 0
157
#define DATA_FLAG_RX_DRIVEN_SIM_VALUE 0
158
#define DATA_FLAG_RX_EDGE_TYPE NONE
159
#define DATA_FLAG_RX_FREQ 50000000
160
#define DATA_FLAG_RX_HAS_IN 1
161
#define DATA_FLAG_RX_HAS_OUT 0
162
#define DATA_FLAG_RX_HAS_TRI 0
163
#define DATA_FLAG_RX_IRQ_TYPE NONE
164
#define DATA_FLAG_RX_RESET_VALUE 0
165
 
166
/*
167
 * Macros for device 'clock_sel', class 'altera_avalon_pio'
168
 * The macros are prefixed with 'CLOCK_SEL_'.
169
 * The prefix is the slave descriptor.
170
 */
171
#define CLOCK_SEL_COMPONENT_TYPE altera_avalon_pio
172
#define CLOCK_SEL_COMPONENT_NAME clock_sel
173
#define CLOCK_SEL_BASE 0x3a000
174
#define CLOCK_SEL_SPAN 16
175
#define CLOCK_SEL_END 0x3a00f
176
#define CLOCK_SEL_BIT_CLEARING_EDGE_REGISTER 0
177
#define CLOCK_SEL_BIT_MODIFYING_OUTPUT_REGISTER 0
178
#define CLOCK_SEL_CAPTURE 0
179
#define CLOCK_SEL_DATA_WIDTH 3
180
#define CLOCK_SEL_DO_TEST_BENCH_WIRING 0
181
#define CLOCK_SEL_DRIVEN_SIM_VALUE 0
182
#define CLOCK_SEL_EDGE_TYPE NONE
183
#define CLOCK_SEL_FREQ 50000000
184
#define CLOCK_SEL_HAS_IN 0
185
#define CLOCK_SEL_HAS_OUT 1
186
#define CLOCK_SEL_HAS_TRI 0
187
#define CLOCK_SEL_IRQ_TYPE NONE
188
#define CLOCK_SEL_RESET_VALUE 0
189
 
190
/*
191
 * Macros for device 'data_read_en_rx', class 'altera_avalon_pio'
192
 * The macros are prefixed with 'DATA_READ_EN_RX_'.
193
 * The prefix is the slave descriptor.
194
 */
195
#define DATA_READ_EN_RX_COMPONENT_TYPE altera_avalon_pio
196
#define DATA_READ_EN_RX_COMPONENT_NAME data_read_en_rx
197
#define DATA_READ_EN_RX_BASE 0x40000
198
#define DATA_READ_EN_RX_SPAN 16
199
#define DATA_READ_EN_RX_END 0x4000f
200
#define DATA_READ_EN_RX_BIT_CLEARING_EDGE_REGISTER 0
201
#define DATA_READ_EN_RX_BIT_MODIFYING_OUTPUT_REGISTER 0
202
#define DATA_READ_EN_RX_CAPTURE 0
203
#define DATA_READ_EN_RX_DATA_WIDTH 1
204
#define DATA_READ_EN_RX_DO_TEST_BENCH_WIRING 0
205
#define DATA_READ_EN_RX_DRIVEN_SIM_VALUE 0
206
#define DATA_READ_EN_RX_EDGE_TYPE NONE
207
#define DATA_READ_EN_RX_FREQ 50000000
208
#define DATA_READ_EN_RX_HAS_IN 0
209
#define DATA_READ_EN_RX_HAS_OUT 1
210
#define DATA_READ_EN_RX_HAS_TRI 0
211
#define DATA_READ_EN_RX_IRQ_TYPE NONE
212
#define DATA_READ_EN_RX_RESET_VALUE 0
213
 
214
/*
215
 * Macros for device 'fsm_info', class 'altera_avalon_pio'
216
 * The macros are prefixed with 'FSM_INFO_'.
217
 * The prefix is the slave descriptor.
218
 */
219
#define FSM_INFO_COMPONENT_TYPE altera_avalon_pio
220
#define FSM_INFO_COMPONENT_NAME fsm_info
221
#define FSM_INFO_BASE 0x4a000
222
#define FSM_INFO_SPAN 16
223
#define FSM_INFO_END 0x4a00f
224
#define FSM_INFO_BIT_CLEARING_EDGE_REGISTER 0
225
#define FSM_INFO_BIT_MODIFYING_OUTPUT_REGISTER 0
226
#define FSM_INFO_CAPTURE 0
227
#define FSM_INFO_DATA_WIDTH 6
228
#define FSM_INFO_DO_TEST_BENCH_WIRING 0
229
#define FSM_INFO_DRIVEN_SIM_VALUE 0
230
#define FSM_INFO_EDGE_TYPE NONE
231
#define FSM_INFO_FREQ 50000000
232
#define FSM_INFO_HAS_IN 1
233
#define FSM_INFO_HAS_OUT 0
234
#define FSM_INFO_HAS_TRI 0
235
#define FSM_INFO_IRQ_TYPE NONE
236
#define FSM_INFO_RESET_VALUE 0
237
 
238
/*
239
 * Macros for device 'fifo_full_rx_status', class 'altera_avalon_pio'
240
 * The macros are prefixed with 'FIFO_FULL_RX_STATUS_'.
241
 * The prefix is the slave descriptor.
242
 */
243
#define FIFO_FULL_RX_STATUS_COMPONENT_TYPE altera_avalon_pio
244
#define FIFO_FULL_RX_STATUS_COMPONENT_NAME fifo_full_rx_status
245
#define FIFO_FULL_RX_STATUS_BASE 0x50000
246
#define FIFO_FULL_RX_STATUS_SPAN 16
247
#define FIFO_FULL_RX_STATUS_END 0x5000f
248
#define FIFO_FULL_RX_STATUS_BIT_CLEARING_EDGE_REGISTER 0
249
#define FIFO_FULL_RX_STATUS_BIT_MODIFYING_OUTPUT_REGISTER 0
250
#define FIFO_FULL_RX_STATUS_CAPTURE 0
251
#define FIFO_FULL_RX_STATUS_DATA_WIDTH 1
252
#define FIFO_FULL_RX_STATUS_DO_TEST_BENCH_WIRING 0
253
#define FIFO_FULL_RX_STATUS_DRIVEN_SIM_VALUE 0
254
#define FIFO_FULL_RX_STATUS_EDGE_TYPE NONE
255
#define FIFO_FULL_RX_STATUS_FREQ 50000000
256
#define FIFO_FULL_RX_STATUS_HAS_IN 1
257
#define FIFO_FULL_RX_STATUS_HAS_OUT 0
258
#define FIFO_FULL_RX_STATUS_HAS_TRI 0
259
#define FIFO_FULL_RX_STATUS_IRQ_TYPE NONE
260
#define FIFO_FULL_RX_STATUS_RESET_VALUE 0
261
 
262
/*
263
 * Macros for device 'counter_tx_fifo', class 'altera_avalon_pio'
264
 * The macros are prefixed with 'COUNTER_TX_FIFO_'.
265
 * The prefix is the slave descriptor.
266
 */
267
#define COUNTER_TX_FIFO_COMPONENT_TYPE altera_avalon_pio
268
#define COUNTER_TX_FIFO_COMPONENT_NAME counter_tx_fifo
269
#define COUNTER_TX_FIFO_BASE 0x5a000
270
#define COUNTER_TX_FIFO_SPAN 16
271
#define COUNTER_TX_FIFO_END 0x5a00f
272
#define COUNTER_TX_FIFO_BIT_CLEARING_EDGE_REGISTER 0
273
#define COUNTER_TX_FIFO_BIT_MODIFYING_OUTPUT_REGISTER 0
274
#define COUNTER_TX_FIFO_CAPTURE 0
275
#define COUNTER_TX_FIFO_DATA_WIDTH 6
276
#define COUNTER_TX_FIFO_DO_TEST_BENCH_WIRING 0
277
#define COUNTER_TX_FIFO_DRIVEN_SIM_VALUE 0
278
#define COUNTER_TX_FIFO_EDGE_TYPE NONE
279
#define COUNTER_TX_FIFO_FREQ 50000000
280
#define COUNTER_TX_FIFO_HAS_IN 1
281
#define COUNTER_TX_FIFO_HAS_OUT 0
282
#define COUNTER_TX_FIFO_HAS_TRI 0
283
#define COUNTER_TX_FIFO_IRQ_TYPE NONE
284
#define COUNTER_TX_FIFO_RESET_VALUE 0
285
 
286
/*
287
 * Macros for device 'fifo_empty_rx_status', class 'altera_avalon_pio'
288
 * The macros are prefixed with 'FIFO_EMPTY_RX_STATUS_'.
289
 * The prefix is the slave descriptor.
290
 */
291
#define FIFO_EMPTY_RX_STATUS_COMPONENT_TYPE altera_avalon_pio
292
#define FIFO_EMPTY_RX_STATUS_COMPONENT_NAME fifo_empty_rx_status
293
#define FIFO_EMPTY_RX_STATUS_BASE 0x60000
294
#define FIFO_EMPTY_RX_STATUS_SPAN 16
295
#define FIFO_EMPTY_RX_STATUS_END 0x6000f
296
#define FIFO_EMPTY_RX_STATUS_BIT_CLEARING_EDGE_REGISTER 0
297
#define FIFO_EMPTY_RX_STATUS_BIT_MODIFYING_OUTPUT_REGISTER 0
298
#define FIFO_EMPTY_RX_STATUS_CAPTURE 0
299
#define FIFO_EMPTY_RX_STATUS_DATA_WIDTH 1
300
#define FIFO_EMPTY_RX_STATUS_DO_TEST_BENCH_WIRING 0
301
#define FIFO_EMPTY_RX_STATUS_DRIVEN_SIM_VALUE 0
302
#define FIFO_EMPTY_RX_STATUS_EDGE_TYPE NONE
303
#define FIFO_EMPTY_RX_STATUS_FREQ 50000000
304
#define FIFO_EMPTY_RX_STATUS_HAS_IN 1
305
#define FIFO_EMPTY_RX_STATUS_HAS_OUT 0
306
#define FIFO_EMPTY_RX_STATUS_HAS_TRI 0
307
#define FIFO_EMPTY_RX_STATUS_IRQ_TYPE NONE
308
#define FIFO_EMPTY_RX_STATUS_RESET_VALUE 0
309
 
310
/*
311
 * Macros for device 'counter_rx_fifo', class 'altera_avalon_pio'
312
 * The macros are prefixed with 'COUNTER_RX_FIFO_'.
313
 * The prefix is the slave descriptor.
314
 */
315
#define COUNTER_RX_FIFO_COMPONENT_TYPE altera_avalon_pio
316
#define COUNTER_RX_FIFO_COMPONENT_NAME counter_rx_fifo
317
#define COUNTER_RX_FIFO_BASE 0x6a000
318
#define COUNTER_RX_FIFO_SPAN 16
319
#define COUNTER_RX_FIFO_END 0x6a00f
320
#define COUNTER_RX_FIFO_BIT_CLEARING_EDGE_REGISTER 0
321
#define COUNTER_RX_FIFO_BIT_MODIFYING_OUTPUT_REGISTER 0
322
#define COUNTER_RX_FIFO_CAPTURE 0
323
#define COUNTER_RX_FIFO_DATA_WIDTH 6
324
#define COUNTER_RX_FIFO_DO_TEST_BENCH_WIRING 0
325
#define COUNTER_RX_FIFO_DRIVEN_SIM_VALUE 0
326
#define COUNTER_RX_FIFO_EDGE_TYPE NONE
327
#define COUNTER_RX_FIFO_FREQ 50000000
328
#define COUNTER_RX_FIFO_HAS_IN 1
329
#define COUNTER_RX_FIFO_HAS_OUT 0
330
#define COUNTER_RX_FIFO_HAS_TRI 0
331
#define COUNTER_RX_FIFO_IRQ_TYPE NONE
332
#define COUNTER_RX_FIFO_RESET_VALUE 0
333
 
334
/*
335
 * Macros for device 'link_start', class 'altera_avalon_pio'
336
 * The macros are prefixed with 'LINK_START_'.
337
 * The prefix is the slave descriptor.
338
 */
339
#define LINK_START_COMPONENT_TYPE altera_avalon_pio
340
#define LINK_START_COMPONENT_NAME link_start
341
#define LINK_START_BASE 0x70000
342
#define LINK_START_SPAN 16
343
#define LINK_START_END 0x7000f
344
#define LINK_START_BIT_CLEARING_EDGE_REGISTER 0
345
#define LINK_START_BIT_MODIFYING_OUTPUT_REGISTER 0
346
#define LINK_START_CAPTURE 0
347
#define LINK_START_DATA_WIDTH 1
348
#define LINK_START_DO_TEST_BENCH_WIRING 0
349
#define LINK_START_DRIVEN_SIM_VALUE 0
350
#define LINK_START_EDGE_TYPE NONE
351
#define LINK_START_FREQ 50000000
352
#define LINK_START_HAS_IN 0
353
#define LINK_START_HAS_OUT 1
354
#define LINK_START_HAS_TRI 0
355
#define LINK_START_IRQ_TYPE NONE
356
#define LINK_START_RESET_VALUE 0
357
 
358
/*
359
 * Macros for device 'auto_start', class 'altera_avalon_pio'
360
 * The macros are prefixed with 'AUTO_START_'.
361
 * The prefix is the slave descriptor.
362
 */
363
#define AUTO_START_COMPONENT_TYPE altera_avalon_pio
364
#define AUTO_START_COMPONENT_NAME auto_start
365
#define AUTO_START_BASE 0x80000
366
#define AUTO_START_SPAN 16
367
#define AUTO_START_END 0x8000f
368
#define AUTO_START_BIT_CLEARING_EDGE_REGISTER 0
369
#define AUTO_START_BIT_MODIFYING_OUTPUT_REGISTER 0
370
#define AUTO_START_CAPTURE 0
371
#define AUTO_START_DATA_WIDTH 1
372
#define AUTO_START_DO_TEST_BENCH_WIRING 0
373
#define AUTO_START_DRIVEN_SIM_VALUE 0
374
#define AUTO_START_EDGE_TYPE NONE
375
#define AUTO_START_FREQ 50000000
376
#define AUTO_START_HAS_IN 0
377
#define AUTO_START_HAS_OUT 1
378
#define AUTO_START_HAS_TRI 0
379
#define AUTO_START_IRQ_TYPE NONE
380
#define AUTO_START_RESET_VALUE 0
381
 
382
/*
383
 * Macros for device 'link_disable', class 'altera_avalon_pio'
384
 * The macros are prefixed with 'LINK_DISABLE_'.
385
 * The prefix is the slave descriptor.
386
 */
387
#define LINK_DISABLE_COMPONENT_TYPE altera_avalon_pio
388
#define LINK_DISABLE_COMPONENT_NAME link_disable
389
#define LINK_DISABLE_BASE 0x90000
390
#define LINK_DISABLE_SPAN 16
391
#define LINK_DISABLE_END 0x9000f
392
#define LINK_DISABLE_BIT_CLEARING_EDGE_REGISTER 0
393
#define LINK_DISABLE_BIT_MODIFYING_OUTPUT_REGISTER 0
394
#define LINK_DISABLE_CAPTURE 0
395
#define LINK_DISABLE_DATA_WIDTH 1
396
#define LINK_DISABLE_DO_TEST_BENCH_WIRING 0
397
#define LINK_DISABLE_DRIVEN_SIM_VALUE 0
398
#define LINK_DISABLE_EDGE_TYPE NONE
399
#define LINK_DISABLE_FREQ 50000000
400
#define LINK_DISABLE_HAS_IN 0
401
#define LINK_DISABLE_HAS_OUT 1
402
#define LINK_DISABLE_HAS_TRI 0
403
#define LINK_DISABLE_IRQ_TYPE NONE
404
#define LINK_DISABLE_RESET_VALUE 0
405
 
406
/*
407
 * Macros for device 'write_data_fifo_tx', class 'altera_avalon_pio'
408
 * The macros are prefixed with 'WRITE_DATA_FIFO_TX_'.
409
 * The prefix is the slave descriptor.
410
 */
411
#define WRITE_DATA_FIFO_TX_COMPONENT_TYPE altera_avalon_pio
412
#define WRITE_DATA_FIFO_TX_COMPONENT_NAME write_data_fifo_tx
413
#define WRITE_DATA_FIFO_TX_BASE 0xa0000
414
#define WRITE_DATA_FIFO_TX_SPAN 16
415
#define WRITE_DATA_FIFO_TX_END 0xa000f
416
#define WRITE_DATA_FIFO_TX_BIT_CLEARING_EDGE_REGISTER 0
417
#define WRITE_DATA_FIFO_TX_BIT_MODIFYING_OUTPUT_REGISTER 0
418
#define WRITE_DATA_FIFO_TX_CAPTURE 0
419
#define WRITE_DATA_FIFO_TX_DATA_WIDTH 9
420
#define WRITE_DATA_FIFO_TX_DO_TEST_BENCH_WIRING 0
421
#define WRITE_DATA_FIFO_TX_DRIVEN_SIM_VALUE 0
422
#define WRITE_DATA_FIFO_TX_EDGE_TYPE NONE
423
#define WRITE_DATA_FIFO_TX_FREQ 50000000
424
#define WRITE_DATA_FIFO_TX_HAS_IN 0
425
#define WRITE_DATA_FIFO_TX_HAS_OUT 1
426
#define WRITE_DATA_FIFO_TX_HAS_TRI 0
427
#define WRITE_DATA_FIFO_TX_IRQ_TYPE NONE
428
#define WRITE_DATA_FIFO_TX_RESET_VALUE 0
429
 
430
/*
431
 * Macros for device 'write_en_tx', class 'altera_avalon_pio'
432
 * The macros are prefixed with 'WRITE_EN_TX_'.
433
 * The prefix is the slave descriptor.
434
 */
435
#define WRITE_EN_TX_COMPONENT_TYPE altera_avalon_pio
436
#define WRITE_EN_TX_COMPONENT_NAME write_en_tx
437
#define WRITE_EN_TX_BASE 0xb0000
438
#define WRITE_EN_TX_SPAN 16
439
#define WRITE_EN_TX_END 0xb000f
440
#define WRITE_EN_TX_BIT_CLEARING_EDGE_REGISTER 0
441
#define WRITE_EN_TX_BIT_MODIFYING_OUTPUT_REGISTER 0
442
#define WRITE_EN_TX_CAPTURE 0
443
#define WRITE_EN_TX_DATA_WIDTH 1
444
#define WRITE_EN_TX_DO_TEST_BENCH_WIRING 0
445
#define WRITE_EN_TX_DRIVEN_SIM_VALUE 0
446
#define WRITE_EN_TX_EDGE_TYPE NONE
447
#define WRITE_EN_TX_FREQ 50000000
448
#define WRITE_EN_TX_HAS_IN 0
449
#define WRITE_EN_TX_HAS_OUT 1
450
#define WRITE_EN_TX_HAS_TRI 0
451
#define WRITE_EN_TX_IRQ_TYPE NONE
452
#define WRITE_EN_TX_RESET_VALUE 0
453
 
454
/*
455
 * Macros for device 'fifo_full_tx_status', class 'altera_avalon_pio'
456
 * The macros are prefixed with 'FIFO_FULL_TX_STATUS_'.
457
 * The prefix is the slave descriptor.
458
 */
459
#define FIFO_FULL_TX_STATUS_COMPONENT_TYPE altera_avalon_pio
460
#define FIFO_FULL_TX_STATUS_COMPONENT_NAME fifo_full_tx_status
461
#define FIFO_FULL_TX_STATUS_BASE 0xc0000
462
#define FIFO_FULL_TX_STATUS_SPAN 16
463
#define FIFO_FULL_TX_STATUS_END 0xc000f
464
#define FIFO_FULL_TX_STATUS_BIT_CLEARING_EDGE_REGISTER 0
465
#define FIFO_FULL_TX_STATUS_BIT_MODIFYING_OUTPUT_REGISTER 0
466
#define FIFO_FULL_TX_STATUS_CAPTURE 0
467
#define FIFO_FULL_TX_STATUS_DATA_WIDTH 1
468
#define FIFO_FULL_TX_STATUS_DO_TEST_BENCH_WIRING 0
469
#define FIFO_FULL_TX_STATUS_DRIVEN_SIM_VALUE 0
470
#define FIFO_FULL_TX_STATUS_EDGE_TYPE NONE
471
#define FIFO_FULL_TX_STATUS_FREQ 50000000
472
#define FIFO_FULL_TX_STATUS_HAS_IN 1
473
#define FIFO_FULL_TX_STATUS_HAS_OUT 0
474
#define FIFO_FULL_TX_STATUS_HAS_TRI 0
475
#define FIFO_FULL_TX_STATUS_IRQ_TYPE NONE
476
#define FIFO_FULL_TX_STATUS_RESET_VALUE 0
477
 
478
/*
479
 * Macros for device 'fifo_empty_tx_status', class 'altera_avalon_pio'
480
 * The macros are prefixed with 'FIFO_EMPTY_TX_STATUS_'.
481
 * The prefix is the slave descriptor.
482
 */
483
#define FIFO_EMPTY_TX_STATUS_COMPONENT_TYPE altera_avalon_pio
484
#define FIFO_EMPTY_TX_STATUS_COMPONENT_NAME fifo_empty_tx_status
485
#define FIFO_EMPTY_TX_STATUS_BASE 0xd0000
486
#define FIFO_EMPTY_TX_STATUS_SPAN 16
487
#define FIFO_EMPTY_TX_STATUS_END 0xd000f
488
#define FIFO_EMPTY_TX_STATUS_BIT_CLEARING_EDGE_REGISTER 0
489
#define FIFO_EMPTY_TX_STATUS_BIT_MODIFYING_OUTPUT_REGISTER 0
490
#define FIFO_EMPTY_TX_STATUS_CAPTURE 0
491
#define FIFO_EMPTY_TX_STATUS_DATA_WIDTH 1
492
#define FIFO_EMPTY_TX_STATUS_DO_TEST_BENCH_WIRING 0
493
#define FIFO_EMPTY_TX_STATUS_DRIVEN_SIM_VALUE 0
494
#define FIFO_EMPTY_TX_STATUS_EDGE_TYPE NONE
495
#define FIFO_EMPTY_TX_STATUS_FREQ 50000000
496
#define FIFO_EMPTY_TX_STATUS_HAS_IN 1
497
#define FIFO_EMPTY_TX_STATUS_HAS_OUT 0
498
#define FIFO_EMPTY_TX_STATUS_HAS_TRI 0
499
#define FIFO_EMPTY_TX_STATUS_IRQ_TYPE NONE
500
#define FIFO_EMPTY_TX_STATUS_RESET_VALUE 0
501
 
502
/*
503
 * Macros for device 'timecode_tx_data', class 'altera_avalon_pio'
504
 * The macros are prefixed with 'TIMECODE_TX_DATA_'.
505
 * The prefix is the slave descriptor.
506
 */
507
#define TIMECODE_TX_DATA_COMPONENT_TYPE altera_avalon_pio
508
#define TIMECODE_TX_DATA_COMPONENT_NAME timecode_tx_data
509
#define TIMECODE_TX_DATA_BASE 0xe0000
510
#define TIMECODE_TX_DATA_SPAN 16
511
#define TIMECODE_TX_DATA_END 0xe000f
512
#define TIMECODE_TX_DATA_BIT_CLEARING_EDGE_REGISTER 0
513
#define TIMECODE_TX_DATA_BIT_MODIFYING_OUTPUT_REGISTER 0
514
#define TIMECODE_TX_DATA_CAPTURE 0
515
#define TIMECODE_TX_DATA_DATA_WIDTH 8
516
#define TIMECODE_TX_DATA_DO_TEST_BENCH_WIRING 0
517
#define TIMECODE_TX_DATA_DRIVEN_SIM_VALUE 0
518
#define TIMECODE_TX_DATA_EDGE_TYPE NONE
519
#define TIMECODE_TX_DATA_FREQ 50000000
520
#define TIMECODE_TX_DATA_HAS_IN 0
521
#define TIMECODE_TX_DATA_HAS_OUT 1
522
#define TIMECODE_TX_DATA_HAS_TRI 0
523
#define TIMECODE_TX_DATA_IRQ_TYPE NONE
524
#define TIMECODE_TX_DATA_RESET_VALUE 0
525
 
526
/*
527
 * Macros for device 'timecode_tx_enable', class 'altera_avalon_pio'
528
 * The macros are prefixed with 'TIMECODE_TX_ENABLE_'.
529
 * The prefix is the slave descriptor.
530
 */
531
#define TIMECODE_TX_ENABLE_COMPONENT_TYPE altera_avalon_pio
532
#define TIMECODE_TX_ENABLE_COMPONENT_NAME timecode_tx_enable
533
#define TIMECODE_TX_ENABLE_BASE 0xf0000
534
#define TIMECODE_TX_ENABLE_SPAN 16
535
#define TIMECODE_TX_ENABLE_END 0xf000f
536
#define TIMECODE_TX_ENABLE_BIT_CLEARING_EDGE_REGISTER 0
537
#define TIMECODE_TX_ENABLE_BIT_MODIFYING_OUTPUT_REGISTER 0
538
#define TIMECODE_TX_ENABLE_CAPTURE 0
539
#define TIMECODE_TX_ENABLE_DATA_WIDTH 1
540
#define TIMECODE_TX_ENABLE_DO_TEST_BENCH_WIRING 0
541
#define TIMECODE_TX_ENABLE_DRIVEN_SIM_VALUE 0
542
#define TIMECODE_TX_ENABLE_EDGE_TYPE NONE
543
#define TIMECODE_TX_ENABLE_FREQ 50000000
544
#define TIMECODE_TX_ENABLE_HAS_IN 0
545
#define TIMECODE_TX_ENABLE_HAS_OUT 1
546
#define TIMECODE_TX_ENABLE_HAS_TRI 0
547
#define TIMECODE_TX_ENABLE_IRQ_TYPE NONE
548
#define TIMECODE_TX_ENABLE_RESET_VALUE 0
549
 
550
 
551
#endif /* _ALTERA_SPW_ULTRA_LIGHT_H_ */

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