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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [top_rtl/] [spw_fifo_ulight.v.bak] - Blame information for rev 32

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Line No. Rev Author Line
1 32 redbear
module SPW_ULIGHT_FIFO(
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                                                                input   FPGA_CLK1_50,
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                                                                input          [1:0] KEY,
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                                                                input           din_a,
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                                                                input           sin_a,
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                                                                //input         din_b,
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                                                                //input         sin_b,
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                                                                output  dout_a,
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                                                                output  sout_a,
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                                                                //output        dout_b,
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                                                                //output        sout_b,
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                                                                //////////// LED ////////////
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                                                                /* 3.3-V LVTTL */
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                                                                output   [7:0] LED
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                                                        );

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