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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [clock_reduce.v] - Blame information for rev 30

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Line No. Rev Author Line
1 23 redbear 
//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
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module clock_reduce(
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                        input clk,
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                        input reset_n,
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                        output reg clk_reduced
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                   );
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reg [10:0] counter;
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always@(posedge clk)
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begin
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        if(!reset_n)
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        begin
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                counter <= 11'd0;
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                clk_reduced <= 1'b0;
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        end
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        else
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        begin
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                if(counter >=11'd0 && counter <=11'd24 )
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                begin
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                        clk_reduced <= 1'b1;
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                        counter <= counter + 11'd1;
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                end
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                else if(counter >=11'd25 && counter <=11'd49 )
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                begin
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                        clk_reduced <= 1'b0;
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                        counter <= counter + 11'd1;
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                end
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                else
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                begin
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                        clk_reduced <= 1'b1;
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                        counter <= 11'd0;
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                end
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        end
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end
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endmodule

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