OpenCores
URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [debounce.v] - Blame information for rev 30

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 23 redbear 
//+FHDR------------------------------------------------------------------------
2 
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
3 
//GLADIC Open Source RTL
4 
//-----------------------------------------------------------------------------
5 
//FILE NAME      :
6 
//DEPARTMENT     : IC Design / Verification
7 
//AUTHOR         : Felipe Fernandes da Costa
8 
//AUTHOR’S EMAIL :
9 
//-----------------------------------------------------------------------------
10 
//RELEASE HISTORY
11 
//VERSION DATE AUTHOR DESCRIPTION
12 
//1.0 YYYY-MM-DD name
13 
//-----------------------------------------------------------------------------
14 
//KEYWORDS : General file searching keywords, leave blank if none.
15 
//-----------------------------------------------------------------------------
16 
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
17 
//-----------------------------------------------------------------------------
18 
//PARAMETERS
19 
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
20 
//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
21 
//-----------------------------------------------------------------------------
22 
//REUSE ISSUES
23 
//Reset Strategy        :
24 
//Clock Domains         :
25 
//Critical Timing       :
26 
//Test Features         :
27 
//Asynchronous I/F      :
28 
//Scan Methodology      :
29 
//Instantiations        :
30 
//Synthesizable (y/n)   :
31 
//Other                 :
32 
//-FHDR------------------------------------------------------------------------
33 
module debounce_db(
34 
                    input CLK,
35 
                    input PB,
36 
 
37 
                    output reg PB_state,
38 
                    output reg PB_down
39 
                  );
40 
 
41 
 
42 
                  reg [15:0] counter;
43 
 
44 
 
45 
 
46 
always@(posedge CLK)
47 
begin
48 
 
49 
        if(PB)
50 
        begin
51 
                PB_state<= 1'b1;
52 
                counter <= 16'd0;
53 
                PB_down <= 1'b0;
54 
        end
55 
        else
56 
        begin
57 
 
58 
                if(counter >= 400)
59 
                begin
60 
                        PB_state<= 1'b0;
61 
                        PB_down <= 1'b1;
62 
                end
63 
                else
64 
                        counter <= counter + 16'd1;
65 
 
66 
        end
67 
 
68 
 
69 
end
70 
 
71 
 
72 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.