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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [detector_tokens.v] - Blame information for rev 37

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1 23 redbear
//+FHDR------------------------------------------------------------------------
2
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
3
//GLADIC Open Source RTL
4
//-----------------------------------------------------------------------------
5
//FILE NAME      :
6
//DEPARTMENT     : IC Design / Verification
7
//AUTHOR         : Felipe Fernandes da Costa
8
//AUTHOR’S EMAIL :
9
//-----------------------------------------------------------------------------
10
//RELEASE HISTORY
11
//VERSION DATE AUTHOR DESCRIPTION
12
//1.0 YYYY-MM-DD name
13
//-----------------------------------------------------------------------------
14
//KEYWORDS : General file searching keywords, leave blank if none.
15
//-----------------------------------------------------------------------------
16
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
17
//-----------------------------------------------------------------------------
18
//PARAMETERS
19
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
20
//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
21
//-----------------------------------------------------------------------------
22
//REUSE ISSUES
23
//Reset Strategy        :
24
//Clock Domains         :
25
//Critical Timing       :
26
//Test Features         :
27
//Asynchronous I/F      :
28
//Scan Methodology      :
29
//Instantiations        :
30
//Synthesizable (y/n)   :
31
//Other                 :
32
//-FHDR------------------------------------------------------------------------
33
module detector_tokens(
34
                                                                input  rx_din,
35
                                                                input  rx_sin,
36
                                                                input  rx_resetn,
37 26 redbear
                                                                //input clock_sys,
38
                                                                output reg rx_buffer_write,
39
                                                                output reg [13:0] info
40 23 redbear
                                                         );
41
 
42 26 redbear
        reg rx_error;
43 23 redbear
        wire rx_got_bit;
44 26 redbear
        reg rx_got_null;
45
        reg rx_got_nchar;
46
        reg rx_got_time_code;
47 23 redbear
        reg rx_got_fct;
48
 
49
        reg  [4:0] counter_neg;
50 26 redbear
        //reg  [3:0] counter_control;
51
        //reg  [3:0] counter_data;
52
        //reg  [5:0] counter_bit_found;
53
        reg control_bit_found;
54 23 redbear
 
55
        wire posedge_clk;
56
        wire negedge_clk;
57
 
58
        reg bit_c_0;//N
59
        reg bit_c_1;//P
60
        reg bit_c_2;//N
61
        reg bit_c_3;//P
62 26 redbear
        reg bit_c_ex;//P
63 23 redbear
 
64
        reg bit_d_0;//N
65
        reg bit_d_1;//P
66
        reg bit_d_2;//N
67
        reg bit_d_3;//P
68
        reg bit_d_4;//N
69
        reg bit_d_5;//P
70
        reg bit_d_6;//N
71
        reg bit_d_7;//P
72
        reg bit_d_8;//N
73
        reg bit_d_9;//P
74 26 redbear
        //reg bit_d_ex;//P
75 23 redbear
 
76
        reg is_control;
77
        reg is_data;
78
 
79
        reg last_is_control;
80
        reg last_is_data;
81
        reg last_is_timec;
82
 
83
        reg last_was_control;
84
        reg last_was_data;
85
        reg last_was_timec;
86
 
87
        reg [3:0] control;
88
        reg [3:0] control_r;
89
        reg [9:0] data;
90
        reg [9:0] timecode;
91
 
92
        reg [9:0] dta_timec;
93
 
94
        reg [3:0] control_l_r;
95
        reg [9:0] data_l_r;
96
 
97 26 redbear
        //reg parity_error;
98
        //wire check_c_d;
99 23 redbear
 
100
        reg rx_data_take;
101 26 redbear
        reg rx_data_take_0;
102 23 redbear
 
103 26 redbear
        //wire [13:0] info_w;
104 23 redbear
        reg first_time;
105
 
106 26 redbear
        wire ready_control;
107
        wire ready_data;
108
 
109
 
110 23 redbear
        //CLOCK RECOVERY
111
        assign posedge_clk      = (rx_din ^ rx_sin)?1'b1:1'b0;
112
        assign negedge_clk      = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;
113
 
114
        assign rx_got_bit       = (posedge_clk)?1'b1:1'b0;
115
 
116 26 redbear
        assign ready_control    = is_control;
117
        assign ready_data       = (counter_neg == 5'd5)?is_data:1'b0;
118 23 redbear
 
119
always@(posedge posedge_clk or negedge rx_resetn)
120
begin
121
 
122
        if(!rx_resetn)
123
        begin
124
                bit_d_1 <= 1'b0;
125
                bit_d_3 <= 1'b0;
126
                bit_d_5 <= 1'b0;
127
                bit_d_7 <= 1'b0;
128
                bit_d_9 <= 1'b0;
129
                first_time <= 1'b0;
130
        end
131
        else
132
        begin
133 26 redbear
                bit_d_1    <= rx_din;
134
                bit_d_3    <= bit_d_1;
135
                bit_d_5    <= bit_d_3;
136
                bit_d_7    <= bit_d_5;
137
                bit_d_9    <= bit_d_7;
138 23 redbear
                first_time <= 1'b1;
139
 
140
        end
141
 
142
end
143
 
144 26 redbear
always@(posedge posedge_clk or negedge rx_resetn)
145
begin
146
 
147
        if(!rx_resetn)
148
        begin
149
                bit_c_1   <= 1'b0;
150
                bit_c_3   <= 1'b0;
151
                bit_c_ex  <= 1'b0;
152
        end
153
        else
154
        begin
155
                bit_c_1 <= rx_din;
156
                bit_c_3 <= bit_c_1;
157
                bit_c_ex <= bit_c_3;
158
        end
159
 
160
end
161
 
162
 
163 23 redbear
always@(posedge negedge_clk or negedge rx_resetn)
164
begin
165
 
166
        if(!rx_resetn)
167
        begin
168
                bit_d_0 <= 1'b0;
169
                bit_d_2 <= 1'b0;
170
                bit_d_4 <= 1'b0;
171
                bit_d_6 <= 1'b0;
172
                bit_d_8 <= 1'b0;
173
        end
174
        else
175 26 redbear
        begin
176 23 redbear
                bit_d_0 <= rx_din;
177
                bit_d_2 <= bit_d_0;
178
                bit_d_4 <= bit_d_2;
179
                bit_d_6 <= bit_d_4;
180
                bit_d_8 <= bit_d_6;
181
        end
182
end
183
 
184
 
185 26 redbear
always@(posedge negedge_clk or negedge rx_resetn)
186 23 redbear
begin
187
 
188 26 redbear
        if(!rx_resetn)
189 23 redbear
        begin
190 26 redbear
                bit_c_0 <= 1'b0;
191
                bit_c_2 <= 1'b0;
192 23 redbear
        end
193 26 redbear
        else
194 23 redbear
        begin
195 26 redbear
 
196
                bit_c_0 <= rx_din;
197
                bit_c_2 <= bit_c_0;
198 23 redbear
        end
199
end
200
 
201 26 redbear
always@(posedge negedge_clk or negedge rx_resetn)
202 23 redbear
begin
203
 
204
        if(!rx_resetn)
205
        begin
206
                is_control <= 1'b0;
207
                is_data    <= 1'b0;
208 26 redbear
                control_bit_found <= 1'b0;
209 23 redbear
                counter_neg <= 5'd0;
210
        end
211
        else
212
        begin
213 26 redbear
                if(counter_neg == 5'd0)
214 23 redbear
                begin
215 26 redbear
                        control_bit_found <= rx_din;
216
                        is_control  <= 1'b0;
217
                        is_data     <= 1'b0;
218 23 redbear
                        counter_neg <= counter_neg + 5'd1;
219
                end
220 26 redbear
                else if(counter_neg == 5'd1 && control_bit_found)
221
                begin
222
                        is_control <= 1'b1;
223
                        is_data    <= 1'b0;
224
                        counter_neg <= counter_neg + 5'd1;
225
                end
226
                else if(counter_neg == 5'd1 && !control_bit_found)
227
                begin
228
                        is_control <= 1'b0;
229
                        is_data    <= 1'b1;
230
                        counter_neg <= counter_neg + 5'd1;
231
                end
232 23 redbear
                else
233
                begin
234 26 redbear
 
235 23 redbear
                        if(is_control)
236
                        begin
237 26 redbear
                                control_bit_found <= rx_din;
238
 
239 23 redbear
                                if(counter_neg == 5'd2)
240
                                begin
241
                                        counter_neg <= 5'd1;
242
                                        is_control  <= 1'b0;
243 26 redbear
                                        is_data     <= 1'b0;
244 23 redbear
                                end
245
                        end
246
                        else if(is_data)
247
                        begin
248
                                if(counter_neg == 5'd5)
249
                                begin
250 26 redbear
                                        control_bit_found <= rx_din;
251 23 redbear
                                        counter_neg <= 5'd1;
252
                                        is_data     <= 1'b0;
253 26 redbear
                                        is_control  <= 1'b0;
254 23 redbear
                                end
255
                                else
256
                                        counter_neg <= counter_neg + 5'd1;
257
                        end
258
                end
259 26 redbear
 
260 23 redbear
        end
261
end
262
 
263 26 redbear
always@(posedge negedge_clk or negedge rx_resetn)
264 23 redbear
begin
265
 
266 26 redbear
        if(!rx_resetn)
267 23 redbear
        begin
268 26 redbear
                rx_error <= 1'b0;
269
        end
270
        else
271
        begin
272
                if(last_is_control)
273 23 redbear
                begin
274 26 redbear
                        if(last_was_control)
275 23 redbear
                        begin
276 26 redbear
                                if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
277
                                begin
278
                                        rx_error <= 1'b1;
279
                                end
280 23 redbear
                        end
281 26 redbear
                        else if(last_was_timec)
282 23 redbear
                        begin
283 26 redbear
                                if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != control[3])
284
                                begin
285
                                        rx_error <= 1'b1;
286
                                end
287 23 redbear
                        end
288 26 redbear
                        else if(last_was_data)
289 23 redbear
                        begin
290 26 redbear
                                if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
291
                                begin
292
                                                rx_error <= 1'b1;
293
                                end
294 23 redbear
                        end
295 26 redbear
 
296
                        end
297
                        else if(last_is_data)
298
                        begin
299
                                if(last_was_control)
300
                                begin
301
                                        if(!(data[8]^control[1]^control[0]) != data[9])
302
                                        begin
303
                                                rx_error <= 1'b1;
304
                                        end
305
                                end
306
                                else if(last_was_timec)
307
                                begin
308
                                        if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != data[9])
309
                                        begin
310
                                                rx_error <= 1'b1;
311
                                        end
312
                                end
313
                                else if(last_was_data)
314
                                begin
315
                                        if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
316
                                        begin
317
                                                rx_error <= 1'b1;
318
                                        end
319
                                end
320
                        end
321 23 redbear
                end
322 26 redbear
 
323
end
324
 
325
always@(posedge negedge_clk or negedge rx_resetn)
326
begin
327
        if(!rx_resetn)
328
        begin
329
                rx_got_null       <= 1'b0;
330
                rx_got_nchar      <= 1'b0;
331
                rx_got_time_code  <= 1'b0;
332
                rx_got_fct        <= 1'b0;
333 23 redbear
        end
334 26 redbear
        else
335 23 redbear
        begin
336 26 redbear
                if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control)
337 23 redbear
                begin
338 26 redbear
                        rx_got_fct        <= 1'b1;
339
                        rx_got_null       <= 1'b0;
340
                        rx_got_nchar      <= 1'b0;
341
                        rx_got_time_code  <= 1'b0;
342 23 redbear
                end
343 26 redbear
                else if(control[2:0] != 3'd7 && last_is_data)
344 23 redbear
                begin
345 26 redbear
                        rx_got_nchar      <= 1'b1;
346
                        rx_got_null       <= 1'b0;
347
                        rx_got_time_code  <= 1'b0;
348
                        rx_got_fct        <= 1'b0;
349 23 redbear
                end
350 26 redbear
                else if(control[2:0] == 3'd7 && last_is_data)
351 23 redbear
                begin
352 26 redbear
                        rx_got_time_code  <= 1'b1;
353
                        rx_got_null       <= 1'b0;
354
                        rx_got_nchar      <= 1'b0;
355
                        rx_got_fct        <= 1'b0;
356 23 redbear
                end
357 26 redbear
                else if(control_l_r[2:0] == 3'd7 && control[2:0] == 3'd4 && last_is_control)
358
                begin
359
                        rx_got_null       <= 1'b1;
360
                        rx_got_nchar      <= 1'b0;
361
                        rx_got_time_code  <= 1'b0;
362
                        rx_got_fct        <= 1'b0;
363
                end
364
                else
365
                begin
366
                        rx_got_null       <= rx_got_null;
367
                        rx_got_nchar      <= rx_got_nchar;
368
                        rx_got_time_code  <= rx_got_time_code;
369
                        rx_got_fct        <= rx_got_fct;
370
                end
371 23 redbear
        end
372
end
373
 
374 26 redbear
 
375
always@(posedge negedge_clk or negedge rx_resetn)
376 23 redbear
begin
377 26 redbear
        if(!rx_resetn)
378
        begin
379
                rx_buffer_write <=  1'b0;
380
                rx_data_take_0  <=  1'b0;
381
        end
382
        else
383
        begin
384
                rx_data_take_0 <= rx_data_take;
385
                rx_buffer_write  <= rx_data_take_0;
386
        end
387
end
388 23 redbear
 
389 26 redbear
always@(posedge ready_control or negedge rx_resetn )
390
begin
391 23 redbear
        if(!rx_resetn)
392
        begin
393 26 redbear
                control_r               <= 4'd0;
394
        end
395
        else
396
        begin
397
                if(counter_neg == 5'd2)
398
                        control_r         <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
399
                else if(counter_neg == 5'd1 && control == 4'd7)
400
                        control_r         <= {bit_c_ex,bit_c_2,bit_c_3,bit_c_0};
401
                else
402
                        control_r         <= control_r;
403
        end
404
end
405
 
406
always@(posedge ready_data or negedge rx_resetn )
407
begin
408
        if(!rx_resetn)
409
        begin
410
                dta_timec               <= 10'd0;
411
        end
412
        else
413
        begin
414
                if(counter_neg == 5'd5)
415
                        dta_timec         <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
416
                else
417
                        dta_timec         <= dta_timec;
418
        end
419
end
420
 
421
always@(posedge posedge_clk or negedge rx_resetn )
422
begin
423
 
424
        if(!rx_resetn)
425
        begin
426 23 redbear
                control     <= 4'd0;
427
                control_l_r <= 4'd0;
428
 
429
                data            <= 10'd0;
430
                data_l_r        <= 10'd0;
431
                //rx_data_flag    <= 9'd0; 
432
                //rx_buffer_write <= 1'b0;
433
                //rx_data_take    <= 1'b0;
434
 
435
                timecode    <= 10'd0;
436
        //      rx_time_out <= 8'd0;
437
        //      rx_tick_out <= 1'b0;
438
 
439
                last_is_control <=1'b0;
440
                last_is_data    <=1'b0;
441
                last_is_timec   <=1'b0;
442
 
443
                last_was_control <=1'b0;
444
                last_was_data    <=1'b0;
445
                last_was_timec   <=1'b0;
446 26 redbear
 
447
                info             <= 14'd0;
448
                //rx_error       <= 1'b0;
449
                //rx_got_null    <= 1'b0;
450
                //rx_got_nchar   <= 1'b0;
451
                //rx_got_time_code <= 1'b0;
452
                //rx_got_fct     <= 1'b0;
453
 
454
                //meta_hold_setup    <= 1'b0;
455
                //meta_hold_setup_n  <= 1'b0;
456
                //meta_hold_setup_n_n<= 1'b0;
457 23 redbear
 
458
        end
459
        else
460
        begin
461
 
462 26 redbear
                //meta_hold_setup_n_n <= meta_hold_setup;
463
                //meta_hold_setup_n   <= meta_hold_setup_n_n; 
464 23 redbear
 
465 26 redbear
                if(ready_control)
466 23 redbear
                begin
467 26 redbear
                        control          <= control_r;
468
                        control_l_r      <= control;
469 23 redbear
 
470 26 redbear
                        last_is_control          <= 1'b1;
471
                        last_is_data             <= 1'b0;
472
                        last_is_timec            <= 1'b0;
473
                        last_was_control         <= last_is_control;
474
                        last_was_data            <= last_is_data ;
475
                        last_was_timec           <= last_is_timec;
476
 
477
                        info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
478
 
479
                end
480
                else if(ready_data)
481
                begin
482
                        if(control[2:0] != 3'd7)
483
                        begin
484
                                data            <= dta_timec;
485
                                last_is_control         <=1'b0;
486
                                last_is_data            <=1'b1;
487
                                last_is_timec           <=1'b0;
488
                                last_was_control        <= last_is_control;
489
                                last_was_data           <= last_is_data ;
490
                                last_was_timec          <= last_is_timec;
491
                        end
492
                        else if(control[2:0] == 3'd7)
493
                        begin
494
                                timecode        <= dta_timec;
495
                                last_is_control         <= 1'b0;
496
                                last_is_data            <= 1'b0;
497
                                last_is_timec           <= 1'b1;
498
                                last_was_control        <= last_is_control;
499
                                last_was_data           <= last_is_data ;
500
                                last_was_timec          <= last_is_timec;
501
                        end
502
 
503
                        info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
504
                end
505
                else if(last_is_data)
506
                begin
507
 
508 23 redbear
                        data_l_r                <= data;
509 26 redbear
 
510
                        info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
511
 
512
                        rx_data_take <= 1'b1;
513 23 redbear
                        //rx_tick_out  <= 1'b0;
514 26 redbear
 
515
                        //meta_hold_setup  <= 1'b0;
516 23 redbear
                end
517 26 redbear
                else if(last_is_timec)
518 23 redbear
                begin
519
                        //rx_tick_out  <= 1'b1;
520 26 redbear
                        rx_data_take <= 1'b1;
521 23 redbear
 
522 26 redbear
                        info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
523
 
524
                        //meta_hold_setup  <= 1'b0;
525 23 redbear
                end
526 26 redbear
                else if(last_is_control)
527 23 redbear
                begin
528
 
529 26 redbear
                        info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
530
 
531
                        rx_data_take    <= 1'b0;
532 23 redbear
 
533 26 redbear
                        if((control[2:0] == 3'd6) == 1'b1 )
534 23 redbear
                        begin
535
                                data <= 10'b0100000001;
536
                        end
537 26 redbear
                        else if(  (control[2:0] == 3'd5 ) == 1'b1 )
538 23 redbear
                        begin
539
                                data <= 10'b0100000000;
540
                        end
541
 
542
                end
543 26 redbear
                else
544
                        info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
545
 
546 23 redbear
        end
547
end
548
 
549
endmodule

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