Subversion Repositories spacewiresystemc

//+FHDR------------------------------------------------------------------------

//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved

//GLADIC Open Source RTL

//-----------------------------------------------------------------------------

//FILE NAME      :

//DEPARTMENT     : IC Design / Verification

//AUTHOR         : Felipe Fernandes da Costa

//AUTHOR’S EMAIL :

//-----------------------------------------------------------------------------

//RELEASE HISTORY

//VERSION DATE AUTHOR DESCRIPTION

//1.0 YYYY-MM-DD name

//-----------------------------------------------------------------------------

//KEYWORDS : General file searching keywords, leave blank if none.

//-----------------------------------------------------------------------------

//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008

//-----------------------------------------------------------------------------

//PARAMETERS

//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS

//e.g.DATA_WIDTH        [32,16] : width of the data : 32:

//-----------------------------------------------------------------------------

//REUSE ISSUES

//Reset Strategy        :

//Clock Domains         :

//Critical Timing       :

//Test Features         :

//Asynchronous I/F      :

//Scan Methodology      :

//Instantiations        :

//Synthesizable (y/n)   :

//Other                 :

//-FHDR------------------------------------------------------------------------

module write_axi(

                 input clock_recovery,

                 input clock_50,

                 input reset_n,

                 input [13:0] data_rec,

                 output reg [13:0] data_stand

                );

always@(posedge clock_50 or negedge reset_n )

begin

        if(!reset_n)

        begin

                data_stand <= 14'd0;

        end

        else

        begin

                if(clock_recovery)

                        data_stand <= data_rec;

                else

                        data_stand <= data_stand;

        end

end

endmodule