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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_rx.v] - Blame information for rev 34

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1 33 redbear 
//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
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module fifo_rx
34 
#(
35 
        parameter integer DWIDTH = 9,
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        parameter integer AWIDTH = 6
37 
)
38 
 
39 
(
40 
        input clock, reset, wr_en, rd_en,
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        input [DWIDTH-1:0] data_in,
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        output reg f_full,f_empty,
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        output reg open_slot_fct,
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        output reg overflow_credit_error,
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        output reg [DWIDTH-1:0] data_out,
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        output reg [AWIDTH-1:0] counter
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);
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49 
        reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
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51 
        reg [AWIDTH-1:0] wr_ptr;
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        reg [AWIDTH-1:0] rd_ptr;
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54 
        reg block_read;
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        reg block_write;
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57 
        reg [AWIDTH-1:0] credit_counter;
58 
 
59 
//Write pointer
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        always@(posedge clock or negedge reset)
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        begin
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                if (!reset)
63 
                begin
64 
                        wr_ptr <= {(AWIDTH){1'b0}};
65 34 redbear 
                        mem[0] <= {(DWIDTH){1'b0}};
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                        mem[1] <= {(DWIDTH){1'b0}};
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                        mem[2] <= {(DWIDTH){1'b0}};
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                        mem[3] <= {(DWIDTH){1'b0}};
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                        mem[4] <= {(DWIDTH){1'b0}};
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                        mem[5] <= {(DWIDTH){1'b0}};
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                        mem[6] <= {(DWIDTH){1'b0}};
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                        mem[7] <= {(DWIDTH){1'b0}};
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                        mem[8] <= {(DWIDTH){1'b0}};
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                        mem[9] <= {(DWIDTH){1'b0}};
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                        mem[10] <= {(DWIDTH){1'b0}};
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                        mem[11] <= {(DWIDTH){1'b0}};
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                        mem[12] <= {(DWIDTH){1'b0}};
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                        mem[13] <= {(DWIDTH){1'b0}};
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                        mem[14] <= {(DWIDTH){1'b0}};
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                        mem[15] <= {(DWIDTH){1'b0}};
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                        mem[16] <= {(DWIDTH){1'b0}};
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                        mem[17] <= {(DWIDTH){1'b0}};
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                        mem[18] <= {(DWIDTH){1'b0}};
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                        mem[19] <= {(DWIDTH){1'b0}};
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                        mem[20] <= {(DWIDTH){1'b0}};
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                        mem[21] <= {(DWIDTH){1'b0}};
88 
 
89 
                        mem[22] <= {(DWIDTH){1'b0}};
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                        mem[23] <= {(DWIDTH){1'b0}};
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                        mem[24] <= {(DWIDTH){1'b0}};
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                        mem[25] <= {(DWIDTH){1'b0}};
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                        mem[26] <= {(DWIDTH){1'b0}};
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                        mem[27] <= {(DWIDTH){1'b0}};
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                        mem[28] <= {(DWIDTH){1'b0}};
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                        mem[29] <= {(DWIDTH){1'b0}};
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                        mem[30] <= {(DWIDTH){1'b0}};
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                        mem[31] <= {(DWIDTH){1'b0}};
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                        mem[32] <= {(DWIDTH){1'b0}};
100 
 
101 
 
102 
                        mem[33] <= {(DWIDTH){1'b0}};
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                        mem[34] <= {(DWIDTH){1'b0}};
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                        mem[35] <= {(DWIDTH){1'b0}};
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                        mem[36] <= {(DWIDTH){1'b0}};
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                        mem[37] <= {(DWIDTH){1'b0}};
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                        mem[38] <= {(DWIDTH){1'b0}};
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                        mem[39] <= {(DWIDTH){1'b0}};
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                        mem[40] <= {(DWIDTH){1'b0}};
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                        mem[41] <= {(DWIDTH){1'b0}};
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                        mem[42] <= {(DWIDTH){1'b0}};
112 
                        mem[43] <= {(DWIDTH){1'b0}};
113 
 
114 
                        mem[44] <= {(DWIDTH){1'b0}};
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                        mem[45] <= {(DWIDTH){1'b0}};
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                        mem[46] <= {(DWIDTH){1'b0}};
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                        mem[47] <= {(DWIDTH){1'b0}};
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                        mem[48] <= {(DWIDTH){1'b0}};
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                        mem[49] <= {(DWIDTH){1'b0}};
120 
                        mem[50] <= {(DWIDTH){1'b0}};
121 
                        mem[51] <= {(DWIDTH){1'b0}};
122 
                        mem[52] <= {(DWIDTH){1'b0}};
123 
                        mem[53] <= {(DWIDTH){1'b0}};
124 
                        mem[54] <= {(DWIDTH){1'b0}};
125 
 
126 
                        mem[55] <= {(DWIDTH){1'b0}};
127 
                        mem[56] <= {(DWIDTH){1'b0}};
128 
                        mem[57] <= {(DWIDTH){1'b0}};
129 
                        mem[58] <= {(DWIDTH){1'b0}};
130 
                        mem[59] <= {(DWIDTH){1'b0}};
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                        mem[60] <= {(DWIDTH){1'b0}};
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                        mem[61] <= {(DWIDTH){1'b0}};
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                        mem[62] <= {(DWIDTH){1'b0}};
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                        mem[63] <= {(DWIDTH){1'b0}};
135 33 redbear 
                        block_write <= 1'b0;
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                        overflow_credit_error<=1'b0;
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                end
138 
                else
139 
                begin
140 
                        if(block_write)
141 
                        begin
142 
                                if(!wr_en)
143 34 redbear 
                                begin
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                                        block_write <= 1'b0;
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                                        wr_ptr <= wr_ptr + 6'd1;
146 
                                end
147 
                                //mem[wr_ptr-6'd1]<=data_in;
148 33 redbear 
                        end
149 
                        else if (wr_en && !f_full)
150 
                        begin
151 
                                block_write <= 1'b1;
152 
                                mem[wr_ptr]<=data_in;
153 34 redbear 
 
154 33 redbear 
                        end
155 
 
156 
                        if(wr_en && credit_counter > 6'd55)
157 
                        begin
158 
 
159 
                                overflow_credit_error<=1'b1;
160 
                        end
161 
                end
162 
        end
163 
 
164 
//FULL - EMPTY COUNTER
165 
 
166 
        always@(posedge clock or negedge reset)
167 
        begin
168 
                if (!reset)
169 
                begin
170 
                        f_full  <= 1'b0;
171 
                        f_empty <= 1'b1;
172 
                        counter <= {(AWIDTH){1'b0}};
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                        credit_counter <= 6'd55;
174 
                end
175 
                else
176 
                begin
177 
 
178 34 redbear 
                        if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
179 33 redbear 
                        begin
180 34 redbear 
                                if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
181 
                                        credit_counter   <= credit_counter - 6'd1 + 6'd8;
182 33 redbear 
                                else
183 34 redbear 
                                        credit_counter   <= credit_counter - 6'd1;
184 33 redbear 
                        end
185 34 redbear 
                        else if (wr_en && !f_full && !block_write)
186 
                        begin
187 
                                credit_counter   <= credit_counter - 6'd1;
188 
                        end
189 33 redbear 
                        else if(rd_en && !f_empty && !block_read)
190 
                        begin
191 
                                if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
192 34 redbear 
                                begin
193 33 redbear 
                                        credit_counter <= credit_counter + 6'd8;
194 34 redbear 
                                end
195 
                        end
196 
                        else
197 
                                credit_counter <= credit_counter;
198 33 redbear 
 
199 34 redbear 
                        if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
200 
                        begin
201 
                                counter <= counter;
202 
                        end
203 
                        else if (wr_en && !f_full && !block_write)
204 
                        begin
205 
                                counter <= counter + 6'd1;
206 
                        end
207 
                        else if(rd_en && !f_empty && !block_read)
208 
                        begin
209 33 redbear 
                                counter <= counter - 6'd1;
210 
                        end
211 34 redbear 
                        else
212 
                        begin
213 
                                counter <= counter;
214 
                        end
215 33 redbear 
 
216 
                        if(counter == 6'd63)
217 
                        begin
218 
                                f_full <= 1'b1;
219 
                        end
220 
                        else
221 
                        begin
222 
                                f_full <= 1'b0;
223 
                        end
224 
 
225 
                        if(counter == 6'd0)
226 
                        begin
227 
                                f_empty <= 1'b1;
228 
                        end
229 
                        else
230 
                        begin
231 
                                f_empty <= 1'b0;
232 
                        end
233 
                end
234 
        end
235 
 
236 
//Read pointer
237 
        always@(posedge clock or negedge reset)
238 
        begin
239 
                if (!reset)
240 
                begin
241 
                        rd_ptr <= {(AWIDTH){1'b0}};
242 
                        data_out <= 9'd0;
243 
                        open_slot_fct<= 1'b0;
244 
                        block_read <= 1'b0;
245 
                end
246 
                else
247 
                begin
248 
 
249 
                        if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
250 
                        begin
251 
                                open_slot_fct<= 1'b1;
252 
                        end
253 
                        else
254 
                        begin
255 
                                open_slot_fct<= 1'b0;
256 
                        end
257 34 redbear 
 
258 
                        if(block_read)
259 33 redbear 
                        begin
260 
                                if(!rd_en)
261 34 redbear 
                                begin
262 33 redbear 
                                        block_read<= 1'b0;
263 34 redbear 
                                end
264 33 redbear 
                        end
265 
                        else
266 
                        if(rd_en && !f_empty)
267 
                        begin
268 
                                block_read<= 1'b1;
269 34 redbear 
                                rd_ptr <= rd_ptr+ 6'd1;
270 33 redbear 
                        end
271 34 redbear 
 
272 
                        data_out  <= mem[rd_ptr];
273 
 
274 33 redbear 
                end
275 
        end
276 
 
277 
        //assign f_empty   = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
278 34 redbear 
        //assign wr        = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
279 
        //assign rd        = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
280 33 redbear 
 
281 
endmodule

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