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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Blame information for rev 40

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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
module fifo_tx
#(
        parameter integer DWIDTH = 9,
        parameter integer AWIDTH = 6
)
 
(
        input clock, reset, wr_en, rd_en,
        input [DWIDTH-1:0] data_in/* synthesis syn_noprune */,
        output reg f_full,write_tx,f_empty,
        output [DWIDTH-1:0] data_out/* synthesis syn_noprune */,
        output reg [AWIDTH-1:0] counter/* synthesis syn_noprune */
);
        reg [AWIDTH-1:0] wr_ptr/* synthesis syn_noprune */;
        reg [AWIDTH-1:0] rd_ptr/* synthesis syn_noprune */;
 
        reg  [1:0] state_data_write;
        reg  [1:0] next_state_data_write;
 
        reg  [1:0] state_data_read;
        reg  [1:0] next_state_data_read;
 
        //reg [AWIDTH-1:0] counter_writer/* synthesis syn_noprune */;
        //reg [AWIDTH-1:0] counter_reader/* synthesis syn_noprune */;
 
 
/****************************************/
 
always@(*)
begin
        next_state_data_write = state_data_write;
 
        case(state_data_write)
        2'd0:
        begin
                if(wr_en && !f_full)
                begin
                        next_state_data_write = 2'd1;
                end
                else
                begin
                        next_state_data_write = 2'd0;
                end
        end
        2'd1:
        begin
                if(wr_en)
                begin
                        next_state_data_write = 2'd1;
                end
                else
                begin
                        next_state_data_write = 2'd2;
                end
        end
        2'd2:
        begin
                next_state_data_write = 2'd0;
        end
        default:
        begin
                next_state_data_write = 2'd0;
        end
        endcase
end
 
/****************************************/
 
always@(*)
begin
        next_state_data_read = state_data_read;
 
        case(state_data_read)
        2'd0:
        begin
                if(counter > 6'd0)
                begin
                        next_state_data_read = 2'd1;
                end
                else
                begin
                        next_state_data_read = 2'd0;
                end
        end
        2'd1:
        begin
                if(rd_en && !f_empty)
                begin
                        next_state_data_read = 2'd2;
                end
                else
                begin
                        next_state_data_read = 2'd1;
                end
        end
        2'd2:
        begin
                if(rd_en)
                begin
                        next_state_data_read = 2'd2;
                end
                else
                begin
                        next_state_data_read = 2'd3;
                end
        end
        2'd3:
        begin
                next_state_data_read = 2'd0;
        end
        default:
        begin
                next_state_data_read = 2'd0;
        end
        endcase
end
 
//Write pointer
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        wr_ptr      <= {(AWIDTH){1'b0}};
                        state_data_write <= 2'd0;
                end
                else
                begin
 
                        state_data_write <= next_state_data_write;
 
                        case(state_data_write)
                        2'd0:
                        begin
                                wr_ptr <= wr_ptr;
                        end
                        2'd1:
                        begin
                                wr_ptr <= wr_ptr;
                        end
                        2'd2:
                        begin
                                wr_ptr <= wr_ptr + 6'd1;
                        end
                        default:
                        begin
                                wr_ptr <= wr_ptr;
                        end
                        endcase
                end
        end
 
//FULL - EMPTY COUNTER
always@(posedge clock or negedge reset)
begin
        if (!reset)
        begin
                f_full  <= 1'b0;
                f_empty <= 1'b0;
                counter <= {(AWIDTH){1'b0}};
        end
        else
        begin
 
                if(state_data_write == 2'd2)
                begin
                        counter <= counter + 6'd1;
                end
                else
                begin
                        if(counter > 6'd0 && state_data_read == 2'd3)
                                counter <= counter - 6'd1;
                        else
                                counter <= counter;
                end
 
                if(counter == 6'd63)
                begin
                        f_full  <= 1'b1;
                end
                else
                begin
                        f_full  <= 1'b0;
                end
 
                if(counter == 6'd0)
                begin
                        f_empty <= 1'b1;
                end
                else
                begin
                        f_empty <= 1'b0;
                end
        end
end
 
 
//Read pointer
always@(posedge clock or negedge reset)
begin
        if (!reset)
        begin
                rd_ptr     <= {(AWIDTH){1'b0}};
                write_tx   <= 1'b0;
                state_data_read <= 2'd0;
        end
        else
        begin
                state_data_read <= next_state_data_read;
                case(state_data_read)
                2'd0:
                begin
                        write_tx<= 1'b0;
                end
                2'd1:
                begin
                        if(rd_en && !f_empty)
                        begin
                                rd_ptr     <= rd_ptr + 6'd1;
                        end
                        else
                        begin
                                rd_ptr     <= rd_ptr;
                        end
 
                        write_tx<= 1'b1;
                end
                2'd2:
                begin
                        write_tx<= 1'b0;
                end
                2'd3:
                begin
                        write_tx<= 1'b0;
                end
                default:
                begin
                        rd_ptr     <= rd_ptr;
                end
                endcase
        end
end
 
mem_data mem_dta_fifo_tx(
 
                .clock(clock),
                .reset(reset),
 
                .data_in(data_in),
                .wr_ptr(wr_ptr),
                .rd_ptr(rd_ptr),
                .data_out(data_out)
);
 
endmodule

Line No.	Rev	Author	Line
1	33	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33			`module fifo_tx`
34			`#(`
35			`parameter integer DWIDTH = 9,`
36			`parameter integer AWIDTH = 6`
37			`)`
38
39			`(`
40			`input clock, reset, wr_en, rd_en,`
41	40	redbear	`input [DWIDTH-1:0] data_in/* synthesis syn_noprune */,`
42	33	redbear	`output reg f_full,write_tx,f_empty,`
43	40	redbear	`output [DWIDTH-1:0] data_out/* synthesis syn_noprune */,`
44			`output reg [AWIDTH-1:0] counter/* synthesis syn_noprune */`
45	33	redbear	`);`
46	40	redbear	`reg [AWIDTH-1:0] wr_ptr/* synthesis syn_noprune */;`
47			`reg [AWIDTH-1:0] rd_ptr/* synthesis syn_noprune */;`
48	33	redbear
49	37	redbear	`reg [1:0] state_data_write;`
50			`reg [1:0] next_state_data_write;`
51	33	redbear
52	37	redbear	`reg [1:0] state_data_read;`
53			`reg [1:0] next_state_data_read;`
54	40	redbear
55			`//reg [AWIDTH-1:0] counter_writer/* synthesis syn_noprune */;`
56			`//reg [AWIDTH-1:0] counter_reader/* synthesis syn_noprune */;`
57
58
59	37	redbear	`/****************************************/`
60
61			`always@(*)`
62			`begin`
63			`next_state_data_write = state_data_write;`
64
65			`case(state_data_write)`
66			`2'd0:`
67			`begin`
68			`if(wr_en && !f_full)`
69			`begin`
70			`next_state_data_write = 2'd1;`
71			`end`
72			`else`
73			`begin`
74			`next_state_data_write = 2'd0;`
75			`end`
76			`end`
77			`2'd1:`
78			`begin`
79			`if(wr_en)`
80			`begin`
81			`next_state_data_write = 2'd1;`
82			`end`
83			`else`
84			`begin`
85			`next_state_data_write = 2'd2;`
86			`end`
87			`end`
88			`2'd2:`
89			`begin`
90			`next_state_data_write = 2'd0;`
91			`end`
92			`default:`
93			`begin`
94			`next_state_data_write = 2'd0;`
95			`end`
96			`endcase`
97			`end`
98
99			`/****************************************/`
100
101			`always@(*)`
102			`begin`
103			`next_state_data_read = state_data_read;`
104
105			`case(state_data_read)`
106			`2'd0:`
107			`begin`
108	40	redbear	`if(counter > 6'd0)`
109	37	redbear	`begin`
110			`next_state_data_read = 2'd1;`
111			`end`
112			`else`
113			`begin`
114			`next_state_data_read = 2'd0;`
115			`end`
116			`end`
117			`2'd1:`
118			`begin`
119	40	redbear	`if(rd_en && !f_empty)`
120	37	redbear	`begin`
121	40	redbear	`next_state_data_read = 2'd2;`
122	37	redbear	`end`
123			`else`
124			`begin`
125	40	redbear	`next_state_data_read = 2'd1;`
126	37	redbear	`end`
127			`end`
128			`2'd2:`
129			`begin`
130	40	redbear	`if(rd_en)`
131			`begin`
132			`next_state_data_read = 2'd2;`
133			`end`
134			`else`
135			`begin`
136			`next_state_data_read = 2'd3;`
137			`end`
138			`end`
139			`2'd3:`
140			`begin`
141	37	redbear	`next_state_data_read = 2'd0;`
142			`end`
143			`default:`
144			`begin`
145			`next_state_data_read = 2'd0;`
146			`end`
147			`endcase`
148			`end`
149
150	33	redbear	`//Write pointer`
151			`always@(posedge clock or negedge reset)`
152			`begin`
153			`if (!reset)`
154			`begin`
155	34	redbear	`wr_ptr <= {(AWIDTH){1'b0}};`
156	37	redbear	`state_data_write <= 2'd0;`
157	33	redbear	`end`
158	34	redbear	`else`
159	33	redbear	`begin`
160
161	37	redbear	`state_data_write <= next_state_data_write;`
162	33	redbear
163	37	redbear	`case(state_data_write)`
164			`2'd0:`
165	33	redbear	`begin`
166	39	redbear	`wr_ptr <= wr_ptr;`
167	33	redbear	`end`
168	37	redbear	`2'd1:`
169	34	redbear	`begin`
170	40	redbear	`wr_ptr <= wr_ptr;`
171	34	redbear	`end`
172	37	redbear	`2'd2:`
173	33	redbear	`begin`
174	37	redbear	`wr_ptr <= wr_ptr + 6'd1;`
175	33	redbear	`end`
176	37	redbear	`default:`
177	34	redbear	`begin`
178	37	redbear	`wr_ptr <= wr_ptr;`
179	34	redbear	`end`
180	37	redbear	`endcase`
181			`end`
182			`end`
183	33	redbear
184	37	redbear	`//FULL - EMPTY COUNTER`
185			`always@(posedge clock or negedge reset)`
186			`begin`
187			`if (!reset)`
188			`begin`
189	40	redbear	`f_full <= 1'b0;`
190			`f_empty <= 1'b0;`
191	37	redbear	`counter <= {(AWIDTH){1'b0}};`
192			`end`
193			`else`
194			`begin`
195
196	39	redbear	`if(state_data_write == 2'd2)`
197	37	redbear	`begin`
198	40	redbear	`counter <= counter + 6'd1;`
199	37	redbear	`end`
200	40	redbear	`else`
201	37	redbear	`begin`
202	40	redbear	`if(counter > 6'd0 && state_data_read == 2'd3)`
203			`counter <= counter - 6'd1;`
204	33	redbear	`else`
205	40	redbear	`counter <= counter;`
206	37	redbear	`end`
207	40	redbear
208			`if(counter == 6'd63)`
209			`begin`
210			`f_full <= 1'b1;`
211			`end`
212	37	redbear	`else`
213			`begin`
214	40	redbear	`f_full <= 1'b0;`
215	37	redbear	`end`
216	33	redbear
217	40	redbear	`if(counter == 6'd0)`
218			`begin`
219			`f_empty <= 1'b1;`
220			`end`
221			`else`
222			`begin`
223			`f_empty <= 1'b0;`
224			`end`
225	39	redbear	`end`
226			`end`
227	33	redbear
228	39	redbear
229	37	redbear	`//Read pointer`
230			`always@(posedge clock or negedge reset)`
231			`begin`
232			`if (!reset)`
233			`begin`
234			`rd_ptr <= {(AWIDTH){1'b0}};`
235			`write_tx <= 1'b0;`
236			`state_data_read <= 2'd0;`
237			`end`
238			`else`
239			`begin`
240			`state_data_read <= next_state_data_read;`
241			`case(state_data_read)`
242			`2'd0:`
243			`begin`
244	40	redbear	`write_tx<= 1'b0;`
245			`end`
246			`2'd1:`
247			`begin`
248			`if(rd_en && !f_empty)`
249	33	redbear	`begin`
250	39	redbear	`rd_ptr <= rd_ptr + 6'd1;`
251	33	redbear	`end`
252	37	redbear	`else`
253	33	redbear	`begin`
254	40	redbear	`rd_ptr <= rd_ptr;`
255			`end`
256	39	redbear
257	40	redbear	`write_tx<= 1'b1;`
258	33	redbear	`end`
259	40	redbear	`2'd2:`
260	37	redbear	`begin`
261			`write_tx<= 1'b0;`
262			`end`
263	40	redbear	`2'd3:`
264	37	redbear	`begin`
265			`write_tx<= 1'b0;`
266			`end`
267			`default:`
268			`begin`
269			`rd_ptr <= rd_ptr;`
270			`end`
271			`endcase`
272	33	redbear	`end`
273	37	redbear	`end`
274	33	redbear
275	40	redbear	`mem_data mem_dta_fifo_tx(`
276
277			`.clock(clock),`
278			`.reset(reset),`
279
280			`.data_in(data_in),`
281			`.wr_ptr(wr_ptr),`
282			`.rd_ptr(rd_ptr),`
283			`.data_out(data_out)`
284			`);`
285
286	33	redbear	`endmodule`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Blame information for rev 40