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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fsm_spw.v] - Blame information for rev 12

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1 5 redbear 
//+FHDR------------------------------------------------------------------------
2 
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
3 
//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
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34 
`timescale 1ns/1ns
35 
 
36 
module FSM_SPW (
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                input  pclk,
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                input  resetn,
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40 
                //fsm status control
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                input  auto_start,
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                input  link_start,
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                input  link_disable,
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45 
                //rx status input control
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                input  rx_error,
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                input  rx_credit_error,
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                input  rx_got_bit,
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                input  rx_got_null,
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                input  rx_got_nchar,
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                input  rx_got_time_code,
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                input  rx_got_fct,
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                output rx_resetn,
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55 
                //tx status control
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                output enable_tx,
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                output send_null_tx,
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                output send_fct_tx,
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60 
                output [5:0] fsm_state
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62 
              );
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localparam [5:0]  error_reset   = 6'b00_0000,
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                  error_wait    = 6'b00_0001,
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                  ready         = 6'b00_0010,
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                  started       = 6'b00_0100,
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                  connecting    = 6'b00_1000,
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                  run           = 6'b01_0000;
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71 
        reg [5:0] state_fsm;
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        reg [5:0] next_state_fsm;
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        reg [11:0] after128us;
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        reg [11:0] after64us;
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        reg [11:0] after850ns;
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78 
//
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assign enable_tx    = (!resetn | state_fsm == error_reset | state_fsm == error_wait)?1'b0:1'b1;
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81 
//
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assign rx_resetn    = (state_fsm == error_reset)?1'b0:1'b1;
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84 
//
85 12 redbear 
assign send_null_tx = (state_fsm == started | state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
86 5 redbear 
 
87 
//
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assign send_fct_tx  = (state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
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90 
//
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assign fsm_state    = state_fsm;
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93 
always@(*)
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begin
95 
 
96 
        next_state_fsm = state_fsm;
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98 
        case(state_fsm)
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        error_reset:
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        begin
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102 
                if(after64us == 12'd639)
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                begin
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                        next_state_fsm = error_wait;
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                end
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                else
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                begin
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                        next_state_fsm = error_reset;
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                end
110 
 
111 
        end
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        error_wait:
113 
        begin
114 
 
115 
                if(after128us == 12'd1279)
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                begin
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                        next_state_fsm = ready;
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                end
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                else if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
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                begin
121 
                        next_state_fsm = error_reset;
122 
                end
123 
 
124 
        end
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        ready:
126 
        begin
127 
 
128 
                if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
129 
                begin
130 
                        next_state_fsm = error_reset;
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                end
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                else if((!link_disable) && (link_start |(auto_start && rx_got_null)))
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                begin
134 
                        next_state_fsm = started;
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                end
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137 
        end
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        started:
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        begin
140 
 
141 
                if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 )
142 
                begin
143 
                        next_state_fsm = error_reset;
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                end
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                else if(rx_got_null && rx_got_bit)
146 
                begin
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                        next_state_fsm = connecting;
148 
                end
149 
 
150 
        end
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        connecting:
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        begin
153 
 
154 
                if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 )
155 
                begin
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                        next_state_fsm = error_reset;
157 
                end
158 
                else if(rx_got_fct)
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                begin
160 
                        next_state_fsm = run;
161 
                end
162 
 
163 
        end
164 
        run:
165 
        begin
166 
 
167 
                if(rx_error | rx_credit_error | link_disable  | after850ns == 12'd85)
168 
                begin
169 
                        next_state_fsm = error_reset;
170 
                end
171 
                else
172 
                begin
173 
                        next_state_fsm = run;
174 
                end
175 
 
176 
        end
177 
        endcase
178 
end
179 
 
180 
always@(posedge pclk)
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begin
182 
        if(!resetn)
183 
        begin
184 
                state_fsm <= error_reset;
185 
        end
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        else
187 
        begin
188 
 
189 
                state_fsm <= next_state_fsm;
190 
 
191 
                case(state_fsm)
192 
                error_reset:
193 
                begin
194 
                end
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                error_wait:
196 
                begin
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                end
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                ready:
199 
                begin
200 
                end
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                started:
202 
                begin
203 
                end
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                connecting:
205 
                begin
206 
                end
207 
                run:
208 
                begin
209 
                end
210 
                endcase
211 
        end
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end
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214 
always@(posedge pclk)
215 
begin
216 
 
217 
        if(!resetn)
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        begin
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                after128us <= 12'd0;
220 
        end
221 
        else
222 
        begin
223 
                if(state_fsm == error_wait | state_fsm == started | state_fsm == connecting)
224 
                begin
225 
                        if(after128us < 12'd1279)
226 
                                after128us <= after128us + 12'd1;
227 
                        else
228 
                                after128us <= 12'd0;
229 
                end
230 
                else
231 
                begin
232 
                                after128us <= 12'd0;
233 
                end
234 
        end
235 
 
236 
end
237 
 
238 
always@(posedge pclk)
239 
begin
240 
 
241 
        if(!resetn)
242 
        begin
243 
                after64us <= 12'd0;
244 
        end
245 
        else
246 
        begin
247 
                if(state_fsm == error_reset && (auto_start | link_start))
248 
                begin
249 
                        if(after64us < 12'd639)
250 
                                after64us <= after64us + 12'd1;
251 
                        else
252 
                                after64us <= 12'd0;
253 
                end
254 
                else
255 
                begin
256 
                        after64us <= 12'd0;
257 
                end
258 
        end
259 
 
260 
end
261 
 
262 
always@(posedge pclk)
263 
begin
264 
 
265 
        if(!resetn | rx_got_bit)
266 
        begin
267 
                after850ns <= 12'd0;
268 
        end
269 
        else
270 
        begin
271 12 redbear 
                if(after850ns < 12'd85 && state_fsm == run)
272 5 redbear 
                        after850ns <= after850ns + 12'd1;
273 
                else
274 
                        after850ns <= 12'd0;
275 
        end
276 
 
277 
end
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279 
endmodule

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