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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module FSM_SPW (
                input  pclk,
                input  resetn,
 
                //fsm status control
                input  auto_start,
                input  link_start,
                input  link_disable,
 
                //rx status input control
                input  rx_error,
                input  rx_credit_error,
                input  rx_got_bit,
                input  rx_got_null,
                input  rx_got_nchar,
                input  rx_got_time_code,
                input  rx_got_fct,
                output rx_resetn,
 
                //tx status control
                output enable_tx,
                output send_null_tx,
                output send_fct_tx,
 
                output [5:0] fsm_state
 
              );
 
localparam [5:0]  error_reset   = 6'b00_0000,
                  error_wait    = 6'b00_0001,
                  ready         = 6'b00_0010,
                  started       = 6'b00_0100,
                  connecting    = 6'b00_1000,
                  run           = 6'b01_0000;
 
        reg [5:0] state_fsm;
        reg [5:0] next_state_fsm;
 
        reg [11:0] after128us;
        reg [11:0] after64us;
        reg [11:0] after850ns;
 
//
assign enable_tx    = (!resetn | state_fsm == error_reset | state_fsm == error_wait)?1'b0:1'b1;
 
//
assign rx_resetn    = (state_fsm == error_reset)?1'b0:1'b1;
 
//
assign send_null_tx = (state_fsm == started | state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
 
//
assign send_fct_tx  = (state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
 
//
assign fsm_state    = state_fsm;
 
always@(*)
begin
 
        next_state_fsm = state_fsm;
 
        case(state_fsm)
        error_reset:
        begin
 
                if(after64us == 12'd639)
                begin
                        next_state_fsm = error_wait;
                end
                else
                begin
                        next_state_fsm = error_reset;
                end
 
        end
        error_wait:
        begin
 
                if(after128us == 12'd1279)
                begin
                        next_state_fsm = ready;
                end
                else if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
                begin
                        next_state_fsm = error_reset;
                end
 
        end
        ready:
        begin
 
                if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
                begin
                        next_state_fsm = error_reset;
                end
                else if((!link_disable) & (link_start |(auto_start && rx_got_null)))
                begin
                        next_state_fsm = started;
                end
 
        end
        started:
        begin
 
                if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
                begin
                        next_state_fsm = error_reset;
                end
                else if(rx_got_null & rx_got_bit)
                begin
                        next_state_fsm = connecting;
                end
 
        end
        connecting:
        begin
 
                if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
                begin
                        next_state_fsm = error_reset;
                end
                else if(rx_got_fct)
                begin
                        next_state_fsm = run;
                end
 
        end
        run:
        begin
 
                if(rx_error | rx_credit_error | link_disable  | after850ns == 12'd85)
                begin
                        next_state_fsm = error_reset;
                end
                else
                begin
                        next_state_fsm = run;
                end
 
        end
        endcase
end
 
always@(posedge pclk)
begin
        if(!resetn)
        begin
                state_fsm <= error_reset;
        end
        else
        begin
 
                state_fsm <= next_state_fsm;
 
                case(state_fsm)
                error_reset:
                begin
                end
                error_wait:
                begin
                end
                ready:
                begin
                end
                started:
                begin
                end
                connecting:
                begin
                end
                run:
                begin
                end
                endcase
 
        end
end
 
always@(posedge pclk)
begin
 
        if(!resetn)
        begin
                after128us <= 12'd0;
        end
        else
        begin
 
                if(next_state_fsm == connecting && state_fsm == started)
                begin
                        after128us <= 12'd0;
                end
                else if(state_fsm == error_wait || state_fsm == started || state_fsm == connecting)
                begin
                        if(after128us < 12'd1279)
                                after128us <= after128us + 12'd1;
                        else
                                after128us <= 12'd0;
                end
                else
                begin
                                after128us <= 12'd0;
                end
        end
 
end
 
always@(posedge pclk)
begin
 
        if(!resetn)
        begin
                after64us <= 12'd0;
        end
        else
        begin
                if(state_fsm == error_reset && (auto_start | link_start))
                begin
                        if(after64us < 12'd639)
                                after64us <= after64us + 12'd1;
                        else
                                after64us <= 12'd0;
                end
                else
                begin
                        after64us <= 12'd0;
                end
        end
 
end
 
always@(posedge pclk)
begin
 
        if(!resetn)
        begin
                after850ns <= 12'd0;
        end
        else
        begin
                if(state_fsm != run)
                begin
                        after850ns <= 12'd0;
                end
                else
                begin
                        if(rx_got_bit)
                        begin
                                after850ns <= 12'd0;
                        end
                        else
                        begin
                                if(after850ns < 12'd85 && state_fsm == run)
                                        after850ns <= after850ns + 12'd1;
                                else
                                        after850ns <= 12'd0;
                        end
                end
        end
 
end
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module FSM_SPW (`
37			`input pclk,`
38			`input resetn,`
39
40			`//fsm status control`
41			`input auto_start,`
42			`input link_start,`
43			`input link_disable,`
44
45			`//rx status input control`
46			`input rx_error,`
47			`input rx_credit_error,`
48			`input rx_got_bit,`
49			`input rx_got_null,`
50			`input rx_got_nchar,`
51			`input rx_got_time_code,`
52			`input rx_got_fct,`
53			`output rx_resetn,`
54
55			`//tx status control`
56			`output enable_tx,`
57			`output send_null_tx,`
58			`output send_fct_tx,`
59
60			`output [5:0] fsm_state`
61
62			`);`
63
64			`localparam [5:0] error_reset = 6'b00_0000,`
65			`error_wait = 6'b00_0001,`
66			`ready = 6'b00_0010,`
67			`started = 6'b00_0100,`
68			`connecting = 6'b00_1000,`
69			`run = 6'b01_0000;`
70
71			`reg [5:0] state_fsm;`
72			`reg [5:0] next_state_fsm;`
73
74			`reg [11:0] after128us;`
75			`reg [11:0] after64us;`
76			`reg [11:0] after850ns;`
77
78			`//`
79			`assign enable_tx = (!resetn \| state_fsm == error_reset \| state_fsm == error_wait)?1'b0:1'b1;`
80
81			`//`
82			`assign rx_resetn = (state_fsm == error_reset)?1'b0:1'b1;`
83
84			`//`
85	12	redbear	`assign send_null_tx = (state_fsm == started \| state_fsm == connecting \| state_fsm == run)?1'b1:1'b0;`
86	5	redbear
87			`//`
88			`assign send_fct_tx = (state_fsm == connecting \| state_fsm == run)?1'b1:1'b0;`
89
90			`//`
91			`assign fsm_state = state_fsm;`
92
93			`always@(*)`
94			`begin`
95
96			`next_state_fsm = state_fsm;`
97
98			`case(state_fsm)`
99			`error_reset:`
100			`begin`
101
102			`if(after64us == 12'd639)`
103			`begin`
104			`next_state_fsm = error_wait;`
105			`end`
106			`else`
107			`begin`
108			`next_state_fsm = error_reset;`
109			`end`
110
111			`end`
112			`error_wait:`
113			`begin`
114
115			`if(after128us == 12'd1279)`
116			`begin`
117			`next_state_fsm = ready;`
118			`end`
119			`else if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code)`
120			`begin`
121			`next_state_fsm = error_reset;`
122			`end`
123
124			`end`
125			`ready:`
126			`begin`
127
128			`if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code)`
129			`begin`
130			`next_state_fsm = error_reset;`
131			`end`
132	25	redbear	`else if((!link_disable) & (link_start \|(auto_start && rx_got_null)))`
133	5	redbear	`begin`
134			`next_state_fsm = started;`
135			`end`
136
137			`end`
138			`started:`
139			`begin`
140
141	25	redbear	`if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code \| after128us == 12'd1279)`
142	5	redbear	`begin`
143			`next_state_fsm = error_reset;`
144			`end`
145	25	redbear	`else if(rx_got_null & rx_got_bit)`
146	5	redbear	`begin`
147			`next_state_fsm = connecting;`
148			`end`
149
150			`end`
151			`connecting:`
152			`begin`
153
154	25	redbear	`if(rx_error \| rx_got_nchar \| rx_got_time_code \| after128us == 12'd1279)`
155	5	redbear	`begin`
156			`next_state_fsm = error_reset;`
157			`end`
158			`else if(rx_got_fct)`
159			`begin`
160			`next_state_fsm = run;`
161			`end`
162
163			`end`
164			`run:`
165			`begin`
166
167			`if(rx_error \| rx_credit_error \| link_disable \| after850ns == 12'd85)`
168			`begin`
169			`next_state_fsm = error_reset;`
170			`end`
171			`else`
172			`begin`
173			`next_state_fsm = run;`
174			`end`
175
176			`end`
177			`endcase`
178			`end`
179
180			`always@(posedge pclk)`
181			`begin`
182			`if(!resetn)`
183			`begin`
184			`state_fsm <= error_reset;`
185			`end`
186			`else`
187			`begin`
188
189			`state_fsm <= next_state_fsm;`
190
191			`case(state_fsm)`
192			`error_reset:`
193			`begin`
194			`end`
195			`error_wait:`
196			`begin`
197			`end`
198			`ready:`
199			`begin`
200			`end`
201			`started:`
202			`begin`
203			`end`
204			`connecting:`
205			`begin`
206			`end`
207			`run:`
208			`begin`
209			`end`
210			`endcase`
211	25	redbear
212	5	redbear	`end`
213			`end`
214
215			`always@(posedge pclk)`
216			`begin`
217
218			`if(!resetn)`
219			`begin`
220			`after128us <= 12'd0;`
221			`end`
222			`else`
223			`begin`
224	25	redbear
225			`if(next_state_fsm == connecting && state_fsm == started)`
226	5	redbear	`begin`
227	25	redbear	`after128us <= 12'd0;`
228			`end`
229			`else if(state_fsm == error_wait \|\| state_fsm == started \|\| state_fsm == connecting)`
230			`begin`
231	5	redbear	`if(after128us < 12'd1279)`
232			`after128us <= after128us + 12'd1;`
233			`else`
234			`after128us <= 12'd0;`
235			`end`
236			`else`
237			`begin`
238			`after128us <= 12'd0;`
239			`end`
240			`end`
241
242			`end`
243
244			`always@(posedge pclk)`
245			`begin`
246
247			`if(!resetn)`
248			`begin`
249			`after64us <= 12'd0;`
250			`end`
251			`else`
252			`begin`
253			`if(state_fsm == error_reset && (auto_start \| link_start))`
254			`begin`
255			`if(after64us < 12'd639)`
256			`after64us <= after64us + 12'd1;`
257			`else`
258			`after64us <= 12'd0;`
259			`end`
260			`else`
261			`begin`
262			`after64us <= 12'd0;`
263			`end`
264			`end`
265
266			`end`
267
268			`always@(posedge pclk)`
269			`begin`
270
271	18	redbear	`if(!resetn)`
272	5	redbear	`begin`
273			`after850ns <= 12'd0;`
274			`end`
275			`else`
276			`begin`
277	25	redbear	`if(state_fsm != run)`
278	18	redbear	`begin`
279			`after850ns <= 12'd0;`
280			`end`
281	5	redbear	`else`
282	18	redbear	`begin`
283	25	redbear	`if(rx_got_bit)`
284			`begin`
285			`after850ns <= 12'd0;`
286			`end`
287	18	redbear	`else`
288	25	redbear	`begin`
289			`if(after850ns < 12'd85 && state_fsm == run)`
290			`after850ns <= after850ns + 12'd1;`
291			`else`
292			`after850ns <= 12'd0;`
293			`end`
294	18	redbear	`end`
295	5	redbear	`end`
296
297			`end`
298
299			`endmodule`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fsm_spw.v] - Blame information for rev 25