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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Blame information for rev 40

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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module RX_SPW (
                        input  rx_din,
                        input  rx_sin,
 
                        input  rx_resetn,
 
                        output rx_error,
 
                        output reg rx_got_bit,
                        output rx_got_null,
                        output rx_got_nchar,
                        output rx_got_time_code,
                        output rx_got_fct,
                        output rx_got_fct_fsm,
 
                        output [8:0] rx_data_flag,
                        output rx_buffer_write,
 
                        output [7:0] rx_time_out,
                        output rx_tick_out
                 );
 
 
        wire [5:0] counter_neg/* synthesis syn_replicate = 0 */;
 
        wire posedge_clk;
        wire negedge_clk;
 
        wire bit_c_0;//N
        wire bit_c_1;//P
        wire bit_c_2;//N
        wire bit_c_3;//P
 
        wire bit_d_0;//N
        wire bit_d_1;//P
        wire bit_d_2;//N
        wire bit_d_3;//P
        wire bit_d_4;//N
        wire bit_d_5;//P
        wire bit_d_6;//N
        wire bit_d_7;//P
        wire bit_d_8;//N
        wire bit_d_9;//P
 
        wire [1:0] state_data_process;
 
        wire is_control/* synthesis dont_replicate */;
        wire last_is_control;
        wire last_is_data;
        wire last_is_timec;
 
        wire [2:0] control_p_r/* synthesis dont_replicate */;
        wire [7:0] timecode/* synthesis dont_replicate */;
 
        wire [2:0] control_l_r/* synthesis dont_replicate */;
 
        wire [8:0] dta_timec_p/* synthesis dont_replicate */;
 
        reg ready_control;
        reg ready_data;
 
        wire ready_control_p_r;
        wire ready_data_p_r;
 
        wire parity_rec_c;
        wire parity_rec_d;
 
        wire parity_rec_c_gen;
        wire parity_rec_d_gen;
 
        wire rx_error_c;
        wire rx_error_d;
 
        wire posedge_p/* synthesis syn_replicate = 0 */;
 
        reg f_time;
 
        //CLOCK RECOVERY
        assign posedge_clk      = posedge_p;
        assign negedge_clk      = (f_time)?!posedge_p:1'b0;
 
        assign rx_time_out      = timecode;
 
        buf (posedge_p,rx_din ^ rx_sin);
 
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                f_time          <= 1'b0;
        end
        else
        begin
                f_time          <= 1'b1;
        end
end
 
always@(*)
begin
 
        rx_got_bit = 1'b0;
 
        if(rx_din | rx_sin)
        begin
                rx_got_bit = 1'b1;
        end
end
 
 
always@(*)
begin
        ready_control = 1'b0;
        ready_data    = 1'b0;
 
        if(is_control && counter_neg == 6'd4 && !posedge_p)
        begin
                ready_control = 1'b1;
                ready_data    = 1'b0;
        end
        else if(!is_control && counter_neg == 6'd32 && !posedge_p)
        begin
                ready_control = 1'b0;
                ready_data    = 1'b1;
        end
end
 
 
rx_buffer_fsm buffer_fsm(
                .posedge_clk(posedge_clk),
                .rx_resetn(rx_resetn),
 
                .last_is_data(last_is_data),
                .last_is_timec(last_is_timec),
                .last_is_control(last_is_control),
 
                .rx_got_null(rx_got_null),
                .rx_got_nchar(rx_got_nchar),
                .rx_got_time_code(rx_got_time_code)
                );
 
rx_data_buffer_data_w  buffer_data_flag(
                        .negedge_clk(negedge_clk),
                        .rx_resetn(rx_resetn),
 
                        .state_data_process(state_data_process),
                        .control(control_p_r),
                        .last_is_timec(last_is_timec),
                        .last_is_data(last_is_data),
                        .last_is_control(last_is_control),
 
                        .rx_buffer_write(rx_buffer_write),
                        .rx_tick_out(rx_tick_out)
 
                        );
 
 
rx_control_data_rdy control_data_rdy(
                                .posedge_clk(posedge_clk),
                                .rx_resetn(rx_resetn),
 
                                .rx_error_c(rx_error_c),
                                .rx_error_d(rx_error_d),
 
                                .control(control_p_r),
                                .control_l_r(control_l_r[2:0]),
 
                                .is_control(is_control),
                                .counter_neg(counter_neg),
 
                                .last_is_control(last_is_control),
 
                                .rx_error(rx_error),
                                .ready_control_p_r(ready_control_p_r),
                                .ready_data_p_r(ready_data_p_r),
                                .rx_got_fct_fsm(rx_got_fct_fsm)
                          );
 
 
rx_data_control_p data_control(
                                .posedge_clk(posedge_clk),
                                .rx_resetn(rx_resetn),
 
                                .bit_c_3(bit_c_3),
                                .bit_c_2(bit_c_2),
                                .bit_c_1(bit_c_1),
                                .bit_c_0(bit_c_0),
 
                                .bit_d_9(bit_d_9),
                                .bit_d_8(bit_d_8),
                                .bit_d_0(bit_d_0),
                                .bit_d_1(bit_d_1),
                                .bit_d_2(bit_d_2),
                                .bit_d_3(bit_d_3),
                                .bit_d_4(bit_d_4),
                                .bit_d_5(bit_d_5),
                                .bit_d_6(bit_d_6),
                                .bit_d_7(bit_d_7),
 
                                .last_is_control(last_is_control),
                                .last_is_data(last_is_data),
 
                                .is_control(is_control),
                                .counter_neg(counter_neg),
 
                                .dta_timec_p(dta_timec_p),
                                .parity_rec_d(parity_rec_d),
                                .parity_rec_d_gen(parity_rec_d_gen),
 
                                .control_p_r(control_p_r),
                                .control_l_r(control_l_r),
                                .parity_rec_c(parity_rec_c),
                                .parity_rec_c_gen(parity_rec_c_gen)
                        );
 
 
bit_capture_data capture_d(
                        .negedge_clk(negedge_clk),
                        .posedge_clk(posedge_clk),
                        .rx_resetn(rx_resetn),
 
                        .rx_din(rx_din),
 
                        .bit_d_0(bit_d_0),//N
                        .bit_d_1(bit_d_1),//P
                        .bit_d_2(bit_d_2),//N
                        .bit_d_3(bit_d_3),//P
                        .bit_d_4(bit_d_4),//N
                        .bit_d_5(bit_d_5),//P
                        .bit_d_6(bit_d_6),//N
                        .bit_d_7(bit_d_7),//P
                        .bit_d_8(bit_d_8),//N
                        .bit_d_9(bit_d_9)//P
                  );
 
bit_capture_control capture_c(
                        .negedge_clk(negedge_clk),
                        .posedge_clk(posedge_clk),
                        .rx_resetn(rx_resetn),
 
                        .rx_din(rx_din),
 
                        .bit_c_0(bit_c_0),
                        .bit_c_1(bit_c_1),
                        .bit_c_2(bit_c_2),
                        .bit_c_3(bit_c_3)
                  );
 
counter_neg cnt_neg(
                        .negedge_clk(negedge_clk),
                        .rx_resetn(rx_resetn),
                        .rx_din(rx_din),
                        .is_control(is_control),
                        .counter_neg(counter_neg)
                  );
 
rx_data_receive rx_dtarcv (
                                .posedge_clk(posedge_clk),
                                .rx_resetn(rx_resetn),
 
                                .ready_control_p_r(ready_control_p_r),
                                .ready_data_p_r(ready_data_p_r),
                                .ready_control(ready_control),
                                .ready_data(ready_data),
 
                                .parity_rec_c(parity_rec_c),
                                .parity_rec_d(parity_rec_d),
 
                                .parity_rec_c_gen(parity_rec_c_gen),
                                .parity_rec_d_gen(parity_rec_d_gen),
 
                                .control_p_r(control_p_r),
                                .dta_timec_p(dta_timec_p),
 
                                .control_l_r(control_l_r),
                                .state_data_process(state_data_process),
 
                                .last_is_control(last_is_control),
                                .last_is_data(last_is_data),
                                .last_is_timec(last_is_timec),
 
                                .rx_error_c(rx_error_c),
                                .rx_error_d(rx_error_d),
                                .rx_got_fct(rx_got_fct),
 
                                .rx_data_flag(rx_data_flag),
 
                                .timecode(timecode)
                      );
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module RX_SPW (`
37			`input rx_din,`
38			`input rx_sin,`
39
40			`input rx_resetn,`
41
42	37	redbear	`output rx_error,`
43	5	redbear
44	33	redbear	`output reg rx_got_bit,`
45	40	redbear	`output rx_got_null,`
46			`output rx_got_nchar,`
47			`output rx_got_time_code,`
48			`output rx_got_fct,`
49			`output rx_got_fct_fsm,`
50	5	redbear
51	40	redbear	`output [8:0] rx_data_flag,`
52			`output rx_buffer_write,`
53	5	redbear
54	25	redbear	`output [7:0] rx_time_out,`
55	40	redbear	`output rx_tick_out`
56	5	redbear	`);`
57
58
59	40	redbear	`wire [5:0] counter_neg/* synthesis syn_replicate = 0 */;`
60	5	redbear
61			`wire posedge_clk;`
62			`wire negedge_clk;`
63
64	40	redbear	`wire bit_c_0;//N`
65			`wire bit_c_1;//P`
66			`wire bit_c_2;//N`
67			`wire bit_c_3;//P`
68	37	redbear
69	40	redbear	`wire bit_d_0;//N`
70			`wire bit_d_1;//P`
71			`wire bit_d_2;//N`
72			`wire bit_d_3;//P`
73			`wire bit_d_4;//N`
74			`wire bit_d_5;//P`
75			`wire bit_d_6;//N`
76			`wire bit_d_7;//P`
77			`wire bit_d_8;//N`
78			`wire bit_d_9;//P`
79	5	redbear
80	40	redbear	`wire [1:0] state_data_process;`
81	5	redbear
82	40	redbear	`wire is_control/* synthesis dont_replicate */;`
83			`wire last_is_control;`
84			`wire last_is_data;`
85			`wire last_is_timec;`
86	5	redbear
87	40	redbear	`wire [2:0] control_p_r/* synthesis dont_replicate */;`
88			`wire [7:0] timecode/* synthesis dont_replicate */;`
89	5	redbear
90	40	redbear	`wire [2:0] control_l_r/* synthesis dont_replicate */;`
91	5	redbear
92	40	redbear	`wire [8:0] dta_timec_p/* synthesis dont_replicate */;`
93	5	redbear
94	33	redbear	`reg ready_control;`
95			`reg ready_data;`
96	23	redbear
97	40	redbear	`wire ready_control_p_r;`
98			`wire ready_data_p_r;`
99	33	redbear
100	40	redbear	`wire parity_rec_c;`
101			`wire parity_rec_d;`
102	33	redbear
103	40	redbear	`wire parity_rec_c_gen;`
104			`wire parity_rec_d_gen;`
105	37	redbear
106	40	redbear	`wire rx_error_c;`
107			`wire rx_error_d;`
108	37	redbear
109	40	redbear	`wire posedge_p/* synthesis syn_replicate = 0 */;`
110
111			`reg f_time;`
112	25	redbear
113	14	redbear	`//CLOCK RECOVERY`
114	33	redbear	`assign posedge_clk = posedge_p;`
115	40	redbear	`assign negedge_clk = (f_time)?!posedge_p:1'b0;`
116	5	redbear
117	40	redbear	`assign rx_time_out = timecode;`
118	5	redbear
119	40	redbear	`buf (posedge_p,rx_din ^ rx_sin);`
120	37	redbear
121	5	redbear
122	14	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
123	5	redbear	`begin`
124	14	redbear
125			`if(!rx_resetn)`
126	5	redbear	`begin`
127	40	redbear	`f_time <= 1'b0;`
128	5	redbear	`end`
129			`else`
130			`begin`
131	40	redbear	`f_time <= 1'b1;`
132	5	redbear	`end`
133			`end`
134
135	40	redbear	`always@(*)`
136	5	redbear	`begin`
137	14	redbear
138	40	redbear	`rx_got_bit = 1'b0;`
139	25	redbear
140	40	redbear	`if(rx_din \| rx_sin)`
141	5	redbear	`begin`
142	40	redbear	`rx_got_bit = 1'b1;`
143	23	redbear	`end`
144			`end`
145	14	redbear
146	25	redbear
147	40	redbear	`always@(*)`
148	23	redbear	`begin`
149	40	redbear	`ready_control = 1'b0;`
150			`ready_data = 1'b0;`
151	23	redbear
152	40	redbear	`if(is_control && counter_neg == 6'd4 && !posedge_p)`
153	23	redbear	`begin`
154	40	redbear	`ready_control = 1'b1;`
155			`ready_data = 1'b0;`
156	23	redbear	`end`
157	40	redbear	`else if(!is_control && counter_neg == 6'd32 && !posedge_p)`
158	23	redbear	`begin`
159	40	redbear	`ready_control = 1'b0;`
160			`ready_data = 1'b1;`
161	23	redbear	`end`
162			`end`
163
164
165	40	redbear	`rx_buffer_fsm buffer_fsm(`
166			`.posedge_clk(posedge_clk),`
167			`.rx_resetn(rx_resetn),`
168
169			`.last_is_data(last_is_data),`
170			`.last_is_timec(last_is_timec),`
171			`.last_is_control(last_is_control),`
172	25	redbear
173	40	redbear	`.rx_got_null(rx_got_null),`
174			`.rx_got_nchar(rx_got_nchar),`
175			`.rx_got_time_code(rx_got_time_code)`
176			`);`
177	25	redbear
178	40	redbear	`rx_data_buffer_data_w buffer_data_flag(`
179			`.negedge_clk(negedge_clk),`
180			`.rx_resetn(rx_resetn),`
181	5	redbear
182	40	redbear	`.state_data_process(state_data_process),`
183			`.control(control_p_r),`
184			`.last_is_timec(last_is_timec),`
185			`.last_is_data(last_is_data),`
186			`.last_is_control(last_is_control),`
187	33	redbear
188	40	redbear	`.rx_buffer_write(rx_buffer_write),`
189			`.rx_tick_out(rx_tick_out)`
190
191			`);`
192	5	redbear
193	33	redbear
194	40	redbear	`rx_control_data_rdy control_data_rdy(`
195			`.posedge_clk(posedge_clk),`
196			`.rx_resetn(rx_resetn),`
197	33	redbear
198	40	redbear	`.rx_error_c(rx_error_c),`
199			`.rx_error_d(rx_error_d),`
200	25	redbear
201	40	redbear	`.control(control_p_r),`
202			`.control_l_r(control_l_r[2:0]),`
203	23	redbear
204	40	redbear	`.is_control(is_control),`
205			`.counter_neg(counter_neg),`
206
207			`.last_is_control(last_is_control),`
208	5	redbear
209	40	redbear	`.rx_error(rx_error),`
210			`.ready_control_p_r(ready_control_p_r),`
211			`.ready_data_p_r(ready_data_p_r),`
212			`.rx_got_fct_fsm(rx_got_fct_fsm)`
213			`);`
214	33	redbear
215
216	40	redbear	`rx_data_control_p data_control(`
217			`.posedge_clk(posedge_clk),`
218			`.rx_resetn(rx_resetn),`
219	5	redbear
220	40	redbear	`.bit_c_3(bit_c_3),`
221			`.bit_c_2(bit_c_2),`
222			`.bit_c_1(bit_c_1),`
223			`.bit_c_0(bit_c_0),`
224	33	redbear
225	40	redbear	`.bit_d_9(bit_d_9),`
226			`.bit_d_8(bit_d_8),`
227			`.bit_d_0(bit_d_0),`
228			`.bit_d_1(bit_d_1),`
229			`.bit_d_2(bit_d_2),`
230			`.bit_d_3(bit_d_3),`
231			`.bit_d_4(bit_d_4),`
232			`.bit_d_5(bit_d_5),`
233			`.bit_d_6(bit_d_6),`
234			`.bit_d_7(bit_d_7),`
235	39	redbear
236	40	redbear	`.last_is_control(last_is_control),`
237			`.last_is_data(last_is_data),`
238	37	redbear
239	40	redbear	`.is_control(is_control),`
240			`.counter_neg(counter_neg),`
241	33	redbear
242	40	redbear	`.dta_timec_p(dta_timec_p),`
243			`.parity_rec_d(parity_rec_d),`
244			`.parity_rec_d_gen(parity_rec_d_gen),`
245	38	redbear
246	40	redbear	`.control_p_r(control_p_r),`
247			`.control_l_r(control_l_r),`
248			`.parity_rec_c(parity_rec_c),`
249			`.parity_rec_c_gen(parity_rec_c_gen)`
250			`);`
251	38	redbear
252
253	40	redbear	`bit_capture_data capture_d(`
254			`.negedge_clk(negedge_clk),`
255			`.posedge_clk(posedge_clk),`
256			`.rx_resetn(rx_resetn),`
257
258			`.rx_din(rx_din),`
259
260			`.bit_d_0(bit_d_0),//N`
261			`.bit_d_1(bit_d_1),//P`
262			`.bit_d_2(bit_d_2),//N`
263			`.bit_d_3(bit_d_3),//P`
264			`.bit_d_4(bit_d_4),//N`
265			`.bit_d_5(bit_d_5),//P`
266			`.bit_d_6(bit_d_6),//N`
267			`.bit_d_7(bit_d_7),//P`
268			`.bit_d_8(bit_d_8),//N`
269			`.bit_d_9(bit_d_9)//P`
270			`);`
271	33	redbear
272	40	redbear	`bit_capture_control capture_c(`
273			`.negedge_clk(negedge_clk),`
274			`.posedge_clk(posedge_clk),`
275			`.rx_resetn(rx_resetn),`
276
277			`.rx_din(rx_din),`
278
279			`.bit_c_0(bit_c_0),`
280			`.bit_c_1(bit_c_1),`
281			`.bit_c_2(bit_c_2),`
282			`.bit_c_3(bit_c_3)`
283			`);`
284	33	redbear
285	40	redbear	`counter_neg cnt_neg(`
286			`.negedge_clk(negedge_clk),`
287			`.rx_resetn(rx_resetn),`
288			`.rx_din(rx_din),`
289			`.is_control(is_control),`
290			`.counter_neg(counter_neg)`
291			`);`
292	33	redbear
293	40	redbear	`rx_data_receive rx_dtarcv (`
294			`.posedge_clk(posedge_clk),`
295			`.rx_resetn(rx_resetn),`
296
297			`.ready_control_p_r(ready_control_p_r),`
298			`.ready_data_p_r(ready_data_p_r),`
299			`.ready_control(ready_control),`
300			`.ready_data(ready_data),`
301	33	redbear
302	40	redbear	`.parity_rec_c(parity_rec_c),`
303			`.parity_rec_d(parity_rec_d),`
304	33	redbear
305	40	redbear	`.parity_rec_c_gen(parity_rec_c_gen),`
306			`.parity_rec_d_gen(parity_rec_d_gen),`
307	5	redbear
308	40	redbear	`.control_p_r(control_p_r),`
309			`.dta_timec_p(dta_timec_p),`
310	37	redbear
311	40	redbear	`.control_l_r(control_l_r),`
312			`.state_data_process(state_data_process),`
313	37	redbear
314	40	redbear	`.last_is_control(last_is_control),`
315			`.last_is_data(last_is_data),`
316			`.last_is_timec(last_is_timec),`
317	37	redbear
318	40	redbear	`.rx_error_c(rx_error_c),`
319			`.rx_error_d(rx_error_d),`
320			`.rx_got_fct(rx_got_fct),`
321	37	redbear
322	40	redbear	`.rx_data_flag(rx_data_flag),`
323	5	redbear
324	40	redbear	`.timecode(timecode)`
325			`);`
326	25	redbear
327	5	redbear	`endmodule`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Blame information for rev 40