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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module RX_SPW (
                        input  rx_din,
                        input  rx_sin,
 
                        input  rx_resetn,
 
                        output rx_error,
 
                        output rx_got_bit,
                        output rx_got_null,
                        output rx_got_nchar,
                        output rx_got_time_code,
                        output rx_got_fct,
 
                        output reg [8:0] rx_data_flag,
                        output reg rx_buffer_write,
 
                        output reg [7:0] rx_time_out,
                        output reg rx_tick_out
                 );
 
 
        reg  [4:0] counter_neg;
 
        wire posedge_clk;
        wire negedge_clk;
 
        reg bit_c_0;//N
        reg bit_c_1;//P
        reg bit_c_2;//N
        reg bit_c_3;//P
 
        reg bit_d_0;//N
        reg bit_d_1;//P
        reg bit_d_2;//N
        reg bit_d_3;//P
        reg bit_d_4;//N
        reg bit_d_5;//P
        reg bit_d_6;//N
        reg bit_d_7;//P
        reg bit_d_8;//N
        reg bit_d_9;//P
 
        reg is_control;
        reg is_data;
 
        reg last_is_control;
        reg last_is_data;
        reg last_is_timec;
 
        reg last_was_control;
        reg last_was_data;
        reg last_was_timec;
 
        reg [3:0] control;
        reg [9:0] data;
        reg [9:0] timecode;
 
        reg [3:0] control_l_r;
        reg [9:0] data_l_r;
 
        reg parity_error;
        wire check_c_d;
 
        reg rx_data_take;
 
        //CLOCK RECOVERY
        assign posedge_clk      = (rx_din ^ rx_sin)?1'b1:1'b0;
        assign negedge_clk      = (!(rx_din ^ rx_sin))?1'b1:1'b0;
 
        assign check_c_d        = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
 
        assign rx_got_null      = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
        assign rx_got_fct       = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
 
        assign rx_got_bit       = (posedge_clk)?1'b1:1'b0;
 
        assign rx_error         =  parity_error;
 
        assign rx_got_nchar     = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
        assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_1 <= 1'b0;
                bit_c_3 <= 1'b0;
 
                bit_d_1 <= 1'b0;
                bit_d_3 <= 1'b0;
                bit_d_5 <= 1'b0;
                bit_d_7 <= 1'b0;
                bit_d_9 <= 1'b0;
        end
        else
        begin
                bit_c_1 <= rx_din;
                bit_c_3 <= bit_c_1;
 
                bit_d_1 <= rx_din;
                bit_d_3 <= bit_d_1;
                bit_d_5 <= bit_d_3;
                bit_d_7 <= bit_d_5;
                bit_d_9 <= bit_d_7;
 
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_0 <= 1'b0;
                bit_c_2 <= 1'b0;
 
                bit_d_0 <= 1'b0;
                bit_d_2 <= 1'b0;
                bit_d_4 <= 1'b0;
                bit_d_6 <= 1'b0;
                bit_d_8 <= 1'b0;
 
                is_control <= 1'b0;
                is_data    <= 1'b0;
 
                counter_neg <= 5'd0;
 
        end
        else
        begin
 
 
                bit_c_0 <= rx_din;
                bit_c_2 <= bit_c_0;
 
                bit_d_0 <= rx_din;
                bit_d_2 <= bit_d_0;
                bit_d_4 <= bit_d_2;
                bit_d_6 <= bit_d_4;
                bit_d_8 <= bit_d_6;
 
                if(counter_neg == 5'd1)
                begin
                        if(bit_c_0)
                        begin
                                is_control <= 1'b1;
                                is_data    <= 1'b0;
                        end
                        else
                        begin
                                is_control <= 1'b0;
                                is_data    <= 1'b1;
                        end
 
                        counter_neg <= counter_neg + 5'd1;
 
                end
                else
                begin
                        if(is_control)
                        begin
                                if(counter_neg == 5'd2)
                                begin
                                        counter_neg <= 5'd1;
                                        is_control  <= 1'b0;
                                end
                                else
                                        counter_neg <= counter_neg + 5'd1;
                        end
                        else if(is_data)
                        begin
                                if(counter_neg == 5'd5)
                                begin
                                        counter_neg <= 5'd1;
                                        is_data     <= 1'b0;
                                end
                                else
                                        counter_neg <= counter_neg + 5'd1;
                        end
                        else
                        begin
                                counter_neg <= counter_neg + 5'd1;
                        end
                end
        end
end
 
always@(*)
begin
 
        parity_error = 1'b0;
 
        if(last_is_control)
        begin
                if(last_was_control)
                begin
                        if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_timec)
                begin
                        if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != control[3])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_data)
                begin
                        if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
                        begin
                                parity_error = 1'b1;
                        end
                end
        end
        else if(last_is_data)
        begin
                if(last_was_control)
                begin
                        if(!(data[8]^control[1]^control[0]) != data[9])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_timec)
                begin
                        if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != data[9])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_data)
                begin
                        if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
                        begin
                                parity_error = 1'b1;
                        end
                end
        end
 
end
 
always@(posedge check_c_d or negedge rx_resetn )
begin
 
        if(!rx_resetn)
        begin
                control     <= 4'd0;
                control_l_r <= 4'd0;
 
                data            <= 10'd0;
                data_l_r        <= 10'd0;
                rx_data_flag    <= 9'd0;
                rx_buffer_write <= 1'b0;
                rx_data_take    <= 1'b0;
 
                timecode    <= 10'd0;
                rx_time_out <= 8'd0;
                rx_tick_out <= 1'b0;
 
                last_is_control <=1'b0;
                last_is_data    <=1'b0;
                last_is_timec   <=1'b0;
 
                last_was_control <=1'b0;
                last_was_data    <=1'b0;
                last_was_timec   <=1'b0;
 
        end
        else
        begin
 
                rx_buffer_write <= rx_data_take;
                rx_data_flag <= data[8:0];
 
                rx_time_out <= timecode;
 
                if((control[2:0] != 3'd7 & is_data) == 1'b1)
                begin
 
                        data                    <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
                        data_l_r                <= data;
 
                        rx_data_take <= 1'b1;
                        rx_tick_out  <= 1'b0;
 
                        last_is_control         <=1'b0;
                        last_is_data            <=1'b1;
                        last_is_timec           <=1'b0;
                        last_was_control        <= last_is_control;
                        last_was_data           <= last_is_data ;
                        last_was_timec          <= last_is_timec;
                end
                else if((control[2:0] == 3'd7 & is_data) == 1'b1)
                begin
 
                        timecode                 <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
                        rx_tick_out  <= 1'b1;
                        rx_data_take <= 1'b0;
 
                        last_is_control         <= 1'b0;
                        last_is_data            <= 1'b0;
                        last_is_timec           <= 1'b1;
                        last_was_control        <= last_is_control;
                        last_was_data           <= last_is_data ;
                        last_was_timec          <= last_is_timec;
                end
                else if({bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd6 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd13 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd5 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd15 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd7 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd4 |  | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd12)
                begin
 
                        control          <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
                        control_l_r      <= control[3:0];
 
                        if((control[2:0] == 3'd6 & is_control) == 1'b1 )
                        begin
                                data <= 10'b0100000001;
                                rx_data_take <= 1'b1;
                        end
                        else if(  (control[2:0] == 3'd5 & is_control) == 1'b1 )
                        begin
                                data <= 10'b0100000000;
                                rx_data_take <= 1'b1;
                        end
                        else
                        begin
                                rx_data_take    <= 1'b0;
                        end
 
                        rx_tick_out  <= 1'b0;
 
                        last_is_control          <= 1'b1;
                        last_is_data             <= 1'b0;
                        last_is_timec            <= 1'b0;
                        last_was_control         <= last_is_control;
                        last_was_data            <= last_is_data ;
                        last_was_timec           <= last_is_timec;
                end
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module RX_SPW (`
37			`input rx_din,`
38			`input rx_sin,`
39
40			`input rx_resetn,`
41
42			`output rx_error,`
43
44			`output rx_got_bit,`
45			`output rx_got_null,`
46			`output rx_got_nchar,`
47			`output rx_got_time_code,`
48			`output rx_got_fct,`
49
50	19	redbear	`output reg [8:0] rx_data_flag,`
51			`output reg rx_buffer_write,`
52	5	redbear
53	19	redbear	`output reg [7:0] rx_time_out,`
54			`output reg rx_tick_out`
55	5	redbear	`);`
56
57
58			`reg [4:0] counter_neg;`
59
60			`wire posedge_clk;`
61			`wire negedge_clk;`
62
63	14	redbear	`reg bit_c_0;//N`
64			`reg bit_c_1;//P`
65			`reg bit_c_2;//N`
66			`reg bit_c_3;//P`
67	5	redbear
68	14	redbear	`reg bit_d_0;//N`
69			`reg bit_d_1;//P`
70			`reg bit_d_2;//N`
71			`reg bit_d_3;//P`
72			`reg bit_d_4;//N`
73			`reg bit_d_5;//P`
74			`reg bit_d_6;//N`
75			`reg bit_d_7;//P`
76			`reg bit_d_8;//N`
77			`reg bit_d_9;//P`
78	5	redbear
79	14	redbear	`reg is_control;`
80			`reg is_data;`
81	5	redbear
82	14	redbear	`reg last_is_control;`
83			`reg last_is_data;`
84			`reg last_is_timec;`
85	5	redbear
86			`reg last_was_control;`
87			`reg last_was_data;`
88	14	redbear	`reg last_was_timec;`
89	5	redbear
90	14	redbear	`reg [3:0] control;`
91			`reg [9:0] data;`
92			`reg [9:0] timecode;`
93	5	redbear
94	14	redbear	`reg [3:0] control_l_r;`
95			`reg [9:0] data_l_r;`
96	5	redbear
97	14	redbear	`reg parity_error;`
98			`wire check_c_d;`
99	5	redbear
100	19	redbear	`reg rx_data_take;`
101
102	14	redbear	`//CLOCK RECOVERY`
103			`assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;`
104			`assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;`
105	5	redbear
106	14	redbear	`assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 \| (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 \| (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;`
107	5	redbear
108	14	redbear	`assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;`
109			`assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;`
110	5	redbear
111			`assign rx_got_bit = (posedge_clk)?1'b1:1'b0;`
112
113	14	redbear	`assign rx_error = parity_error;`
114	5	redbear
115	14	redbear	`assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;`
116			`assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;`
117	5	redbear
118	14	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
119	5	redbear	`begin`
120	14	redbear
121			`if(!rx_resetn)`
122	5	redbear	`begin`
123	14	redbear	`bit_c_1 <= 1'b0;`
124			`bit_c_3 <= 1'b0;`
125
126			`bit_d_1 <= 1'b0;`
127			`bit_d_3 <= 1'b0;`
128			`bit_d_5 <= 1'b0;`
129			`bit_d_7 <= 1'b0;`
130			`bit_d_9 <= 1'b0;`
131	5	redbear	`end`
132			`else`
133			`begin`
134	14	redbear	`bit_c_1 <= rx_din;`
135			`bit_c_3 <= bit_c_1;`
136
137			`bit_d_1 <= rx_din;`
138			`bit_d_3 <= bit_d_1;`
139			`bit_d_5 <= bit_d_3;`
140			`bit_d_7 <= bit_d_5;`
141			`bit_d_9 <= bit_d_7;`
142
143	5	redbear	`end`
144	14	redbear
145	5	redbear	`end`
146
147	14	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
148	5	redbear	`begin`
149	14	redbear
150			`if(!rx_resetn)`
151	5	redbear	`begin`
152	14	redbear	`bit_c_0 <= 1'b0;`
153			`bit_c_2 <= 1'b0;`
154
155			`bit_d_0 <= 1'b0;`
156			`bit_d_2 <= 1'b0;`
157			`bit_d_4 <= 1'b0;`
158			`bit_d_6 <= 1'b0;`
159			`bit_d_8 <= 1'b0;`
160
161			`is_control <= 1'b0;`
162			`is_data <= 1'b0;`
163
164			`counter_neg <= 5'd0;`
165
166	5	redbear	`end`
167			`else`
168			`begin`
169	14	redbear
170
171			`bit_c_0 <= rx_din;`
172			`bit_c_2 <= bit_c_0;`
173
174			`bit_d_0 <= rx_din;`
175			`bit_d_2 <= bit_d_0;`
176			`bit_d_4 <= bit_d_2;`
177			`bit_d_6 <= bit_d_4;`
178			`bit_d_8 <= bit_d_6;`
179
180			`if(counter_neg == 5'd1)`
181	5	redbear	`begin`
182	14	redbear	`if(bit_c_0)`
183			`begin`
184			`is_control <= 1'b1;`
185			`is_data <= 1'b0;`
186			`end`
187			`else`
188			`begin`
189			`is_control <= 1'b0;`
190			`is_data <= 1'b1;`
191			`end`
192
193			`counter_neg <= counter_neg + 5'd1;`
194
195	5	redbear	`end`
196			`else`
197			`begin`
198	14	redbear	`if(is_control)`
199			`begin`
200			`if(counter_neg == 5'd2)`
201			`begin`
202			`counter_neg <= 5'd1;`
203			`is_control <= 1'b0;`
204			`end`
205			`else`
206			`counter_neg <= counter_neg + 5'd1;`
207			`end`
208			`else if(is_data)`
209			`begin`
210			`if(counter_neg == 5'd5)`
211			`begin`
212			`counter_neg <= 5'd1;`
213			`is_data <= 1'b0;`
214			`end`
215			`else`
216			`counter_neg <= counter_neg + 5'd1;`
217			`end`
218			`else`
219			`begin`
220			`counter_neg <= counter_neg + 5'd1;`
221			`end`
222			`end`
223	5	redbear	`end`
224			`end`
225
226			`always@(*)`
227			`begin`
228
229			`parity_error = 1'b0;`
230
231	14	redbear	`if(last_is_control)`
232	5	redbear	`begin`
233	14	redbear	`if(last_was_control)`
234	5	redbear	`begin`
235	14	redbear	`if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])`
236			`begin`
237			`parity_error = 1'b1;`
238			`end`
239	5	redbear	`end`
240	14	redbear	`else if(last_was_timec)`
241	5	redbear	`begin`
242	14	redbear	`if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])`
243			`begin`
244			`parity_error = 1'b1;`
245			`end`
246	5	redbear	`end`
247	14	redbear	`else if(last_was_data)`
248	5	redbear	`begin`
249	14	redbear	`if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])`
250			`begin`
251			`parity_error = 1'b1;`
252			`end`
253	5	redbear	`end`
254			`end`
255	14	redbear	`else if(last_is_data)`
256	5	redbear	`begin`
257	14	redbear	`if(last_was_control)`
258	5	redbear	`begin`
259	14	redbear	`if(!(data[8]^control[1]^control[0]) != data[9])`
260			`begin`
261			`parity_error = 1'b1;`
262			`end`
263	5	redbear	`end`
264	14	redbear	`else if(last_was_timec)`
265	5	redbear	`begin`
266	14	redbear	`if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])`
267			`begin`
268			`parity_error = 1'b1;`
269			`end`
270	5	redbear	`end`
271	14	redbear	`else if(last_was_data)`
272	5	redbear	`begin`
273	14	redbear	`if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])`
274			`begin`
275			`parity_error = 1'b1;`
276			`end`
277	5	redbear	`end`
278			`end`
279	14	redbear
280	5	redbear	`end`
281
282	14	redbear	`always@(posedge check_c_d or negedge rx_resetn )`
283	5	redbear	`begin`
284
285	14	redbear	`if(!rx_resetn)`
286	5	redbear	`begin`
287	14	redbear	`control <= 4'd0;`
288			`control_l_r <= 4'd0;`
289	5	redbear
290	19	redbear	`data <= 10'd0;`
291			`data_l_r <= 10'd0;`
292			`rx_data_flag <= 9'd0;`
293			`rx_buffer_write <= 1'b0;`
294			`rx_data_take <= 1'b0;`
295	5	redbear
296	14	redbear	`timecode <= 10'd0;`
297	19	redbear	`rx_time_out <= 8'd0;`
298			`rx_tick_out <= 1'b0;`
299	5	redbear
300	14	redbear	`last_is_control <=1'b0;`
301			`last_is_data <=1'b0;`
302			`last_is_timec <=1'b0;`
303	5	redbear
304	14	redbear	`last_was_control <=1'b0;`
305			`last_was_data <=1'b0;`
306			`last_was_timec <=1'b0;`
307	5	redbear
308			`end`
309			`else`
310			`begin`
311	19	redbear
312			`rx_buffer_write <= rx_data_take;`
313			`rx_data_flag <= data[8:0];`
314
315			`rx_time_out <= timecode;`
316
317	14	redbear	`if((control[2:0] != 3'd7 & is_data) == 1'b1)`
318			`begin`
319	5	redbear
320	19	redbear	`data <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
321	14	redbear	`data_l_r <= data;`
322	19	redbear
323			`rx_data_take <= 1'b1;`
324			`rx_tick_out <= 1'b0;`
325	5	redbear
326	14	redbear	`last_is_control <=1'b0;`
327			`last_is_data <=1'b1;`
328			`last_is_timec <=1'b0;`
329			`last_was_control <= last_is_control;`
330			`last_was_data <= last_is_data ;`
331			`last_was_timec <= last_is_timec;`
332			`end`
333			`else if((control[2:0] == 3'd7 & is_data) == 1'b1)`
334			`begin`
335
336			`timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
337	19	redbear	`rx_tick_out <= 1'b1;`
338			`rx_data_take <= 1'b0;`
339	14	redbear
340			`last_is_control <= 1'b0;`
341			`last_is_data <= 1'b0;`
342			`last_is_timec <= 1'b1;`
343			`last_was_control <= last_is_control;`
344			`last_was_data <= last_is_data ;`
345			`last_was_timec <= last_is_timec;`
346			`end`
347			`else if({bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd6 \| {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd13 \| {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd5 \| {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd15 \| {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd7 \| {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd4 \| \| {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd12)`
348			`begin`
349
350			`control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`
351			`control_l_r <= control[3:0];`
352	19	redbear
353			`if((control[2:0] == 3'd6 & is_control) == 1'b1 )`
354	14	redbear	`begin`
355	19	redbear	`data <= 10'b0100000001;`
356			`rx_data_take <= 1'b1;`
357	14	redbear	`end`
358	19	redbear	`else if( (control[2:0] == 3'd5 & is_control) == 1'b1 )`
359			`begin`
360			`data <= 10'b0100000000;`
361			`rx_data_take <= 1'b1;`
362			`end`
363			`else`
364			`begin`
365			`rx_data_take <= 1'b0;`
366			`end`
367
368			`rx_tick_out <= 1'b0;`
369
370	14	redbear	`last_is_control <= 1'b1;`
371			`last_is_data <= 1'b0;`
372			`last_is_timec <= 1'b0;`
373			`last_was_control <= last_is_control;`
374			`last_was_data <= last_is_data ;`
375			`last_was_timec <= last_is_timec;`
376			`end`
377	5	redbear	`end`
378			`end`
379
380			`endmodule`

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