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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Blame information for rev 25

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1 5 redbear
//+FHDR------------------------------------------------------------------------
2
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
3
//GLADIC Open Source RTL
4
//-----------------------------------------------------------------------------
5
//FILE NAME      :
6
//DEPARTMENT     : IC Design / Verification
7
//AUTHOR         : Felipe Fernandes da Costa
8
//AUTHOR’S EMAIL :
9
//-----------------------------------------------------------------------------
10
//RELEASE HISTORY
11
//VERSION DATE AUTHOR DESCRIPTION
12
//1.0 YYYY-MM-DD name
13
//-----------------------------------------------------------------------------
14
//KEYWORDS : General file searching keywords, leave blank if none.
15
//-----------------------------------------------------------------------------
16
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
17
//-----------------------------------------------------------------------------
18
//PARAMETERS
19
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
20
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
21
//-----------------------------------------------------------------------------
22
//REUSE ISSUES
23
//Reset Strategy        :
24
//Clock Domains         :
25
//Critical Timing       :
26
//Test Features         :
27
//Asynchronous I/F      :
28
//Scan Methodology      :
29
//Instantiations        :
30
//Synthesizable (y/n)   :
31
//Other                 :
32
//-FHDR------------------------------------------------------------------------
33
 
34
`timescale 1ns/1ns
35
 
36
module RX_SPW (
37
                        input  rx_din,
38
                        input  rx_sin,
39
 
40
                        input  rx_resetn,
41
 
42 25 redbear
                        output reg rx_error,
43 5 redbear
 
44
                        output rx_got_bit,
45 25 redbear
                        output reg rx_got_null,
46
                        output reg rx_got_nchar,
47
                        output reg rx_got_time_code,
48 23 redbear
                        output reg rx_got_fct,
49 25 redbear
                        output reg rx_got_fct_fsm,
50 5 redbear
 
51 19 redbear
                        output reg [8:0] rx_data_flag,
52
                        output reg rx_buffer_write,
53 5 redbear
 
54 25 redbear
                        output [7:0] rx_time_out,
55 19 redbear
                        output reg rx_tick_out
56 5 redbear
                 );
57
 
58
 
59
        reg  [4:0] counter_neg;
60 25 redbear
        reg control_bit_found;
61 5 redbear
 
62
        wire posedge_clk;
63
        wire negedge_clk;
64
 
65 14 redbear
        reg bit_c_0;//N
66
        reg bit_c_1;//P
67
        reg bit_c_2;//N
68
        reg bit_c_3;//P
69 25 redbear
        reg bit_c_ex;//P
70 5 redbear
 
71 14 redbear
        reg bit_d_0;//N
72
        reg bit_d_1;//P
73
        reg bit_d_2;//N
74
        reg bit_d_3;//P
75
        reg bit_d_4;//N
76
        reg bit_d_5;//P
77
        reg bit_d_6;//N
78
        reg bit_d_7;//P
79
        reg bit_d_8;//N
80
        reg bit_d_9;//P
81 5 redbear
 
82 14 redbear
        reg is_control;
83
        reg is_data;
84 5 redbear
 
85 14 redbear
        reg last_is_control;
86
        reg last_is_data;
87
        reg last_is_timec;
88 5 redbear
 
89
        reg last_was_control;
90
        reg last_was_data;
91 14 redbear
        reg last_was_timec;
92 5 redbear
 
93 14 redbear
        reg [3:0] control;
94 23 redbear
        reg [3:0] control_r;
95 14 redbear
        reg [9:0] data;
96
        reg [9:0] timecode;
97 5 redbear
 
98 14 redbear
        reg [3:0] control_l_r;
99
        reg [9:0] data_l_r;
100 5 redbear
 
101 23 redbear
        reg [9:0] dta_timec;
102
 
103 19 redbear
        reg rx_data_take;
104 25 redbear
        reg rx_data_take_0;
105 19 redbear
 
106 23 redbear
        reg first_time;
107
 
108 25 redbear
        wire ready_control;
109
        wire ready_data;
110
 
111 14 redbear
        //CLOCK RECOVERY
112
        assign posedge_clk      = (rx_din ^ rx_sin)?1'b1:1'b0;
113 23 redbear
        assign negedge_clk      = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;
114 5 redbear
 
115
        assign rx_got_bit       = (posedge_clk)?1'b1:1'b0;
116
 
117 25 redbear
        assign rx_time_out      = timecode[7:0];
118 5 redbear
 
119 25 redbear
        assign ready_control    = is_control;
120
        assign ready_data       = (counter_neg == 5'd5)?is_data:1'b0;
121 5 redbear
 
122 14 redbear
always@(posedge posedge_clk or negedge rx_resetn)
123 5 redbear
begin
124 14 redbear
 
125
        if(!rx_resetn)
126 5 redbear
        begin
127 25 redbear
                bit_d_1  <= 1'b0;
128
                bit_d_3  <= 1'b0;
129
                bit_d_5  <= 1'b0;
130
                bit_d_7  <= 1'b0;
131
                bit_d_9  <= 1'b0;
132 23 redbear
                first_time <= 1'b0;
133 5 redbear
        end
134
        else
135
        begin
136 25 redbear
                bit_d_1  <= rx_din;
137
                bit_d_3  <= bit_d_1;
138
                bit_d_5  <= bit_d_3;
139
                bit_d_7  <= bit_d_5;
140
                bit_d_9  <= bit_d_7;
141 23 redbear
                first_time <= 1'b1;
142 5 redbear
        end
143 14 redbear
 
144 5 redbear
end
145
 
146 14 redbear
always@(posedge negedge_clk or negedge rx_resetn)
147 5 redbear
begin
148 14 redbear
 
149
        if(!rx_resetn)
150 5 redbear
        begin
151 14 redbear
                bit_d_0 <= 1'b0;
152
                bit_d_2 <= 1'b0;
153
                bit_d_4 <= 1'b0;
154
                bit_d_6 <= 1'b0;
155
                bit_d_8 <= 1'b0;
156 25 redbear
 
157 5 redbear
        end
158
        else
159
        begin
160 14 redbear
                bit_d_0 <= rx_din;
161
                bit_d_2 <= bit_d_0;
162
                bit_d_4 <= bit_d_2;
163
                bit_d_6 <= bit_d_4;
164
                bit_d_8 <= bit_d_6;
165 23 redbear
        end
166
end
167 14 redbear
 
168 25 redbear
always@(posedge posedge_clk or negedge rx_resetn)
169 23 redbear
begin
170 25 redbear
 
171
        if(!rx_resetn)
172 23 redbear
        begin
173 25 redbear
                bit_c_1   <= 1'b0;
174
                bit_c_3   <= 1'b0;
175
                bit_c_ex  <= 1'b0;
176 23 redbear
        end
177 25 redbear
        else
178
        begin
179
                bit_c_1 <= rx_din;
180
                bit_c_3 <= bit_c_1;
181
                bit_c_ex <= bit_c_3;
182
        end
183
 
184 23 redbear
end
185
 
186 25 redbear
always@(posedge negedge_clk or negedge rx_resetn)
187 23 redbear
begin
188
 
189 25 redbear
        if(!rx_resetn)
190 23 redbear
        begin
191 25 redbear
                bit_c_0   <= 1'b0;
192
                bit_c_2   <= 1'b0;
193 23 redbear
        end
194 25 redbear
        else
195 23 redbear
        begin
196 25 redbear
                bit_c_0 <= rx_din;
197
                bit_c_2 <= bit_c_0;
198 23 redbear
        end
199
end
200
 
201 25 redbear
 
202 23 redbear
always@(posedge negedge_clk or negedge rx_resetn)
203
begin
204
 
205
        if(!rx_resetn)
206
        begin
207
                is_control <= 1'b0;
208
                is_data    <= 1'b0;
209 25 redbear
                control_bit_found <= 1'b0;
210 23 redbear
                counter_neg <= 5'd0;
211
        end
212
        else
213
        begin
214 25 redbear
                if(counter_neg == 5'd0)
215 5 redbear
                begin
216 25 redbear
                        control_bit_found <= rx_din;
217
                        is_control  <= 1'b0;
218
                        is_data     <= 1'b0;
219 14 redbear
                        counter_neg <= counter_neg + 5'd1;
220 5 redbear
                end
221 25 redbear
                else if(counter_neg == 5'd1 && control_bit_found)
222
                begin
223
                        is_control <= 1'b1;
224
                        is_data    <= 1'b0;
225
                        counter_neg <= counter_neg + 5'd1;
226
                end
227
                else if(counter_neg == 5'd1 && !control_bit_found)
228
                begin
229
                        is_control <= 1'b0;
230
                        is_data    <= 1'b1;
231
                        counter_neg <= counter_neg + 5'd1;
232
                end
233 5 redbear
                else
234
                begin
235 25 redbear
 
236 14 redbear
                        if(is_control)
237
                        begin
238 25 redbear
 
239
 
240 14 redbear
                                if(counter_neg == 5'd2)
241
                                begin
242 25 redbear
                                        control_bit_found <= rx_din;
243
 
244 14 redbear
                                        counter_neg <= 5'd1;
245
                                        is_control  <= 1'b0;
246 25 redbear
                                        is_data     <= 1'b0;
247 14 redbear
                                end
248
                        end
249
                        else if(is_data)
250
                        begin
251
                                if(counter_neg == 5'd5)
252
                                begin
253 25 redbear
                                        control_bit_found <= rx_din;
254
 
255 14 redbear
                                        counter_neg <= 5'd1;
256
                                        is_data     <= 1'b0;
257 25 redbear
                                        is_control  <= 1'b0;
258 14 redbear
                                end
259
                                else
260
                                        counter_neg <= counter_neg + 5'd1;
261
                        end
262
                end
263 25 redbear
 
264 5 redbear
        end
265
end
266
 
267
always@(*)
268
begin
269
 
270 25 redbear
        rx_got_fct = 1'b0;
271 5 redbear
 
272 25 redbear
        if(negedge_clk)
273 5 redbear
        begin
274 25 redbear
                if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && ready_control)
275 5 redbear
                begin
276 25 redbear
                        rx_got_fct = 1'b1;
277 5 redbear
                end
278 25 redbear
        end
279
 
280
end
281
 
282
always@(posedge negedge_clk or negedge rx_resetn)
283
begin
284
 
285
 
286
        if(!rx_resetn)
287
        begin
288
                rx_error <= 1'b0;
289
        end
290
        else
291
        begin
292
                if(last_is_control)
293 5 redbear
                begin
294 25 redbear
                        if(last_was_control)
295 14 redbear
                        begin
296 25 redbear
                                if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
297
                                begin
298
                                        rx_error <= 1'b1;
299
                                end
300 14 redbear
                        end
301 25 redbear
                        else if(last_was_timec)
302
                        begin
303
                                if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != control[3])
304
                                begin
305
                                        rx_error <= 1'b1;
306
                                end
307
                        end
308
                        else if(last_was_data)
309
                        begin
310
                                if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
311
                                begin
312
                                        rx_error <= 1'b1;
313
                                end
314
                        end
315
 
316 5 redbear
                end
317 25 redbear
                else if(last_is_data)
318 5 redbear
                begin
319 25 redbear
                        if(last_was_control)
320 14 redbear
                        begin
321 25 redbear
                                if(!(data[8]^control[1]^control[0]) != data[9])
322
                                begin
323
                                        rx_error <= 1'b1;
324
                                end
325 14 redbear
                        end
326 25 redbear
                        else if(last_was_timec)
327
                        begin
328
                                if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != data[9])
329
                                begin
330
                                        rx_error <= 1'b1;
331
                                end
332
                        end
333
                        else if(last_was_data)
334
                        begin
335
                                if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
336
                                begin
337
                                        rx_error <= 1'b1;
338
                                end
339
                        end
340 5 redbear
                end
341 25 redbear
 
342 5 redbear
        end
343 25 redbear
end
344
 
345
always@(posedge negedge_clk or negedge rx_resetn)
346
begin
347
 
348
        if(!rx_resetn)
349 5 redbear
        begin
350 25 redbear
                rx_got_null       <= 1'b0;
351
                rx_got_nchar      <= 1'b0;
352
                rx_got_time_code  <= 1'b0;
353
        end
354
        else
355
        begin
356
                if(control[2:0] != 3'd7 && last_is_data )
357 5 redbear
                begin
358 25 redbear
                        rx_got_nchar      <= 1'b1;
359 5 redbear
                end
360 25 redbear
                else if(control[2:0] == 3'd7 && last_is_data)
361 5 redbear
                begin
362 25 redbear
                        rx_got_time_code  <= 1'b1;
363 5 redbear
                end
364 25 redbear
                else if(control_l_r[2:0] == 3'd7 && control[2:0] == 3'd4 && last_is_control)
365 5 redbear
                begin
366 25 redbear
                        rx_got_null       <= 1'b1;
367 5 redbear
                end
368 25 redbear
                else
369
                begin
370
                        rx_got_null       <= rx_got_null;
371
                        rx_got_time_code  <= rx_got_time_code;
372
                        rx_got_nchar      <= rx_got_nchar;
373
                end
374 5 redbear
        end
375
end
376
 
377 25 redbear
always@(posedge negedge_clk or negedge rx_resetn)
378 5 redbear
begin
379 25 redbear
        if(!rx_resetn)
380
        begin
381
                rx_got_fct_fsm   <= 1'b0;
382
                rx_buffer_write <=  1'b0;
383
                rx_data_take_0  <=  1'b0;
384
        end
385
        else
386
        begin
387
                rx_data_take_0 <= rx_data_take;
388
                rx_buffer_write  <= rx_data_take_0;
389 5 redbear
 
390 25 redbear
                if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control)
391
                        rx_got_fct_fsm <= 1'b1;
392
                else
393
                        rx_got_fct_fsm <= rx_got_fct_fsm;
394
        end
395
end
396
 
397
always@(posedge ready_control or negedge rx_resetn )
398
begin
399 14 redbear
        if(!rx_resetn)
400 5 redbear
        begin
401 25 redbear
                control_r               <= 4'd0;
402
        end
403
        else
404
        begin
405
                if(counter_neg == 5'd2)
406
                        control_r         <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
407
                else if(counter_neg == 5'd1 && control == 4'd7)
408
                        control_r         <= {bit_c_ex,bit_c_2,bit_c_3,bit_c_0};
409
                else
410
                        control_r         <= control_r;
411
        end
412
end
413 23 redbear
 
414 5 redbear
 
415 25 redbear
always@(posedge ready_data or negedge rx_resetn )
416
begin
417
        if(!rx_resetn)
418
        begin
419
                dta_timec               <= 10'd0;
420
        end
421
        else
422
        begin
423
                if(counter_neg == 5'd5)
424
                        dta_timec         <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
425
                else
426
                        dta_timec         <= dta_timec;
427
        end
428
end
429 5 redbear
 
430 25 redbear
always@(posedge posedge_clk or negedge rx_resetn )
431
begin
432 5 redbear
 
433 25 redbear
        if(!rx_resetn)
434
        begin
435 5 redbear
 
436 25 redbear
                control_l_r     <= 4'd0;
437
                control         <= 4'd0;
438
                data            <=  10'd0;
439
                data_l_r        <=  10'd0;
440
                rx_data_flag    <=  9'd0;
441
                rx_data_take    <=  1'b0;
442
 
443
 
444
                timecode        <=  10'd0;
445
                rx_tick_out     <=  1'b0;
446
 
447
                last_is_control <=  1'b0;
448
                last_is_data    <=  1'b0;
449
                last_is_timec   <=  1'b0;
450
 
451
                last_was_control <= 1'b0;
452
                last_was_data    <= 1'b0;
453
                last_was_timec   <= 1'b0;
454
 
455 5 redbear
        end
456
        else
457
        begin
458 19 redbear
 
459 25 redbear
                if(ready_control)
460
                begin
461
                        control          <= control_r;
462
                        control_l_r      <= control;
463 19 redbear
 
464 25 redbear
                        last_is_control          <= 1'b1;
465
                        last_is_data             <= 1'b0;
466
                        last_is_timec            <= 1'b0;
467
                        last_was_control         <= last_is_control;
468
                        last_was_data            <= last_is_data ;
469
                        last_was_timec           <= last_is_timec;
470
                end
471
                else if(ready_data)
472 14 redbear
                begin
473 5 redbear
 
474 25 redbear
                        if(control[2:0] != 3'd7)
475
                        begin
476
                                rx_data_flag    <= dta_timec[8:0];
477
                                data            <= dta_timec;
478
                                last_is_control         <=1'b0;
479
                                last_is_data            <=1'b1;
480
                                last_is_timec           <=1'b0;
481
                                last_was_control        <= last_is_control;
482
                                last_was_data           <= last_is_data ;
483
                                last_was_timec          <= last_is_timec;
484
                        end
485
                        else if(control[2:0] == 3'd7)
486
                        begin
487
                                timecode        <= dta_timec;
488
                                last_is_control         <= 1'b0;
489
                                last_is_data            <= 1'b0;
490
                                last_is_timec           <= 1'b1;
491
                                last_was_control        <= last_is_control;
492
                                last_was_data           <= last_is_data ;
493
                                last_was_timec          <= last_is_timec;
494
                        end
495
                end
496
                else if(last_is_timec)
497
                begin
498
 
499 14 redbear
                        data_l_r                <= data;
500 19 redbear
 
501
                        rx_data_take <= 1'b1;
502
                        rx_tick_out  <= 1'b0;
503 5 redbear
 
504 25 redbear
                        //meta_hold_setup        <= 1'b0;
505 14 redbear
                end
506 25 redbear
                else if(last_is_data)
507 14 redbear
                begin
508
 
509 19 redbear
                        rx_tick_out  <= 1'b1;
510
                        rx_data_take <= 1'b0;
511 25 redbear
 
512
                        //meta_hold_setup        <= 1'b0;
513
 
514 14 redbear
                end
515 25 redbear
                else if(last_is_control)
516 14 redbear
                begin
517 25 redbear
                        //if(control == 4'd6 || control == 4'd13 || control == 4'd5 || control == 4'd15 || control == 4'd7 || control == 4'd4 || control == 4'd12) 
518 14 redbear
 
519 25 redbear
                        if((control[2:0] == 3'd6) == 1'b1 )
520 14 redbear
                        begin
521 19 redbear
                                data <= 10'b0100000001;
522
                                rx_data_take <= 1'b1;
523 14 redbear
                        end
524 25 redbear
                        else if((control[2:0] == 3'd5) == 1'b1 )
525 19 redbear
                        begin
526
                                data <= 10'b0100000000;
527
                                rx_data_take <= 1'b1;
528
                        end
529
                        else
530
                        begin
531
                                rx_data_take    <= 1'b0;
532
                        end
533
 
534
                        rx_tick_out  <= 1'b0;
535
 
536 25 redbear
                        //meta_hold_setup        <= 1'b0;
537 14 redbear
                end
538 25 redbear
 
539 5 redbear
        end
540
end
541
 
542
endmodule

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