URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Blame information for rev 34

Go to most recent revision | Details | Compare with Previous | View Log


//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module RX_SPW (
                        input  rx_din,
                        input  rx_sin,
 
                        input  rx_resetn,
 
                        output reg rx_error,
 
                        output reg rx_got_bit,
                        output reg rx_got_null,
                        output reg rx_got_nchar,
                        output reg rx_got_time_code,
                        output reg rx_got_fct,
                        output reg rx_got_fct_fsm,
 
                        output reg [8:0] rx_data_flag,
                        output reg rx_buffer_write,
 
                        output [7:0] rx_time_out,
                        output reg rx_tick_out
                 );
 
 
        reg  [5:0] counter_neg;
        reg control_bit_found;
        reg data_bit_found;
 
        wire posedge_clk;
        wire negedge_clk;
 
        reg bit_c_0;//N
        reg bit_c_1;//P
        reg bit_c_2;//N
        reg bit_c_3;//P
 
        reg bit_d_0;//N
        reg bit_d_1;//P
        reg bit_d_2;//N
        reg bit_d_3;//P
        reg bit_d_4;//N
        reg bit_d_5;//P
        reg bit_d_6;//N
        reg bit_d_7;//P
        reg bit_d_8;//N
        reg bit_d_9;//P
 
        reg is_control;
        //reg is_data;
 
        reg last_is_control;
        reg last_is_data;
        reg last_is_timec;
 
        reg last_was_control;
        reg last_was_data;
        reg last_was_timec;
 
        reg [3:0] control;
        reg [3:0] control_r;
        reg [3:0] control_p_r;
        reg [9:0] data;
        reg [9:0] timecode;
 
        reg [3:0] control_l_r;
        reg [9:0] data_l_r;
 
        reg [9:0] dta_timec;
        reg [9:0] dta_timec_p;
 
        reg rx_data_take;
        reg rx_data_take_0;
 
        reg ready_control;
        reg ready_data;
 
        reg ready_control_p;
        reg ready_data_p;
 
        reg ready_control_p_r;
        reg ready_data_p_r;
 
        reg posedge_p;
 
        //CLOCK RECOVERY
        assign posedge_clk      = posedge_p;
        assign negedge_clk      = !posedge_p;
 
        assign rx_time_out      = timecode[7:0];
 
always@(*)
begin
 
        rx_got_bit = 1'b0;
 
        if(rx_din | rx_sin)
        begin
                rx_got_bit = 1'b1;
        end
end
 
always@(*)
begin
        ready_control    = 1'b0;
        ready_data       = 1'b0;
 
        if(counter_neg[5:0] == 6'd4 && !posedge_p)
        begin
                ready_control = 1'b1;
        end
        else if(counter_neg[5:0] == 6'd32 && !posedge_p)
        begin
                ready_data       = 1'b1;
        end
end
 
 
always@(*)
begin
        ready_control_p    = 1'b0;
        ready_data_p       = 1'b0;
 
        if(counter_neg[5:0] == 6'd4 && posedge_p)
        begin
                ready_control_p = 1'b1;
        end
        else if(counter_neg[5:0] == 6'd32 && posedge_p)
        begin
                ready_data_p       = 1'b1;
        end
end
 
always@(*)
begin
        posedge_p = 1'b0;
 
        if(rx_din ^ rx_sin)
        begin
                posedge_p = 1'b1;
        end
        else
        begin
                posedge_p = 1'b0;
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_d_1  <= 1'b0;
                bit_d_3  <= 1'b0;
                bit_d_5  <= 1'b0;
                bit_d_7  <= 1'b0;
                bit_d_9  <= 1'b0;
        end
        else
        begin
                bit_d_1  <= rx_din;
                bit_d_3  <= bit_d_1;
                bit_d_5  <= bit_d_3;
                bit_d_7  <= bit_d_5;
                bit_d_9  <= bit_d_7;
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_d_0 <= 1'b0;
                bit_d_2 <= 1'b0;
                bit_d_4 <= 1'b0;
                bit_d_6 <= 1'b0;
                bit_d_8 <= 1'b0;
 
        end
        else
        begin
                bit_d_0 <= rx_din;
                bit_d_2 <= bit_d_0;
                bit_d_4 <= bit_d_2;
                bit_d_6 <= bit_d_4;
                bit_d_8 <= bit_d_6;
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_1   <= 1'b0;
                bit_c_3   <= 1'b0;
        end
        else
        begin
                bit_c_1 <= rx_din;
                bit_c_3 <= bit_c_1;
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_0   <= 1'b0;
                bit_c_2   <= 1'b0;
        end
        else
        begin
                bit_c_0 <= rx_din;
                bit_c_2 <= bit_c_0;
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                rx_got_fct <= 1'b0;
        end
        else
        begin
                if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
                begin
                        rx_got_fct <= 1'b1;
                end
                else
                begin
                        rx_got_fct <= 1'b0;
                end
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
 
        if(!rx_resetn)
        begin
                rx_error <= 1'b0;
        end
        else
        begin
                if(last_is_control == 1'b1)
                begin
                        if(last_was_control == 1'b1)
                        begin
                                if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
                                begin
                                        rx_error <= 1'b1;
                                end
                                else
                                begin
                                        rx_error <= 1'b0;
                                end
                        end
                        else if(last_was_timec == 1'b1)
                        begin
                                if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != control[3])
                                begin
                                        rx_error <= 1'b1;
                                end
                                else
                                begin
                                        rx_error <= 1'b0;
                                end
                        end
                        else if(last_was_data == 1'b1)
                        begin
                                if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
                                begin
                                        rx_error <= 1'b1;
                                end
                                else
                                begin
                                        rx_error <= 1'b0;
                                end
                        end
 
                end
                else if(last_is_data == 1'b1)
                begin
                        if(last_was_control == 1'b1)
                        begin
                                if(!(data[8]^control[1]^control[0]) != data[9])
                                begin
                                        rx_error <= 1'b1;
                                end
                                else
                                begin
                                        rx_error <= 1'b0;
                                end
                        end
                        else if(last_was_timec == 1'b1)
                        begin
                                if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != data[9])
                                begin
                                        rx_error <= 1'b1;
                                end
                                else
                                begin
                                        rx_error <= 1'b0;
                                end
                        end
                        else if(last_was_data == 1'b1)
                        begin
                                if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
                                begin
                                        rx_error <= 1'b1;
                                end
                                else
                                begin
                                        rx_error <= 1'b0;
                                end
                        end
                end
 
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                rx_got_null       <= 1'b0;
                rx_got_nchar      <= 1'b0;
                rx_got_time_code  <= 1'b0;
        end
        else
        begin
                if(last_is_data == 1'b1 )
                begin
                        rx_got_nchar      <= 1'b1;
                end
                else if(last_is_timec  == 1'b1)
                begin
                        rx_got_time_code  <= 1'b1;
                end
                else if(last_is_control == 1'b1)
                begin
                        rx_got_null       <= 1'b1;
                end
                else
                begin
                        rx_got_null       <= 1'b0;
                        rx_got_nchar      <= 1'b0;
                        rx_got_time_code  <= 1'b0;
                end
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
        if(!rx_resetn)
        begin
                rx_got_fct_fsm  <=  1'b0;
                rx_buffer_write <=  1'b0;
                rx_data_take_0  <=  1'b0;
                ready_control_p_r <= 1'b0;
                ready_data_p_r  <=  1'b0;
 
        end
        else
        begin
                rx_data_take_0 <= rx_data_take;
                rx_buffer_write  <= rx_data_take_0;
 
 
                if(ready_control || ready_control_p)
                begin
                        if(is_control)
                                ready_control_p_r <= 1'b1;
                end
                else
                begin
                        ready_control_p_r <= 1'b0;
                end
 
                if(ready_data || ready_data_p)
                begin
                        if(!is_control)
                                ready_data_p_r <= 1'b1;
                end
                else
                begin
                        ready_data_p_r <= 1'b0;
                end
 
                if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
                        rx_got_fct_fsm <= 1'b1;
                else
                        rx_got_fct_fsm <= rx_got_fct_fsm;
        end
end
 
always@(posedge ready_control or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                control_r               <= 4'd0;
        end
        else
        begin
                //if(is_control)
                        control_r         <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
        end
end
 
always@(posedge ready_control_p or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                control_p_r             <= 4'd0;
        end
        else
        begin
                //if(is_control)
                        control_p_r       <= control_r;
        end
end
 
 
 
always@(posedge ready_data or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                dta_timec               <= 10'd0;
        end
        else
        begin
                //if(!is_control)
                        dta_timec         <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
        end
end
 
 
always@(posedge ready_data_p or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                dta_timec_p             <= 10'd0;
        end
        else
        begin
                //if(!is_control)
                        dta_timec_p  <= dta_timec;
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                is_control <= 1'b0;
                control_bit_found <= 1'b0;
                counter_neg[5:0]  <= 6'd1;
        end
        else
        begin
 
                control_bit_found <= rx_din;
 
                case(counter_neg)
                6'd1:
                begin
                        counter_neg[5:0]  <=  6'd2;
                end
                6'd2:
                begin
                        if(control_bit_found == 1'b1)
                        begin
                                is_control  <= 1'b1;
                        end
                        else
                        begin
                                is_control  <= 1'b0;
                        end
 
                        counter_neg[5:0] <= 6'd4;
                end
                6'd4:
                begin
                        if(is_control == 1'b1)
                        begin
                                counter_neg[5:0] <= 6'd2;
                                is_control <= 1'b0;
                        end
                        else
                        begin
                                counter_neg[5:0] <= 6'd8;
                        end
                end
                6'd8:
                begin
                        counter_neg[5:0] <= 6'd16;
                end
                6'd16:
                begin
                        counter_neg[5:0] <= 6'd32;
                end
                6'd32:
                begin
                        is_control <= 1'b0;
                        counter_neg[5:0] <= 6'd2;
                end
                default:
                begin
                        is_control <= is_control;
                        counter_neg[5:0] <= counter_neg[5:0];
                end
                endcase
 
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn )
begin
 
        if(!rx_resetn)
        begin
 
                control_l_r     <= 4'd0;
                control         <= 4'd0;
                data            <=  10'd0;
                data_l_r        <=  10'd0;
                rx_data_flag    <=  9'd0;
                rx_data_take    <=  1'b0;
 
 
                timecode        <=  10'd0;
                rx_tick_out     <=  1'b0;
 
                last_is_control <=  1'b0;
                last_is_data    <=  1'b0;
                last_is_timec   <=  1'b0;
 
                last_was_control <= 1'b0;
                last_was_data    <= 1'b0;
                last_was_timec   <= 1'b0;
 
        end
        else
        begin
 
                if(ready_control_p_r)
                begin
                        control          <= control_p_r;
                        control_l_r      <= control;
 
                        last_is_control          <= 1'b1;
                        last_is_data             <= 1'b0;
                        last_is_timec            <= 1'b0;
                        last_was_control         <= last_is_control;
                        last_was_data            <= last_is_data ;
                        last_was_timec           <= last_is_timec;
                end
                else if(ready_data_p_r)
                begin
 
                        if(control[2:0] != 3'd7)
                        begin
                                rx_data_flag    <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
                                data            <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
                                data_l_r        <= data;
                                last_is_control         <=1'b0;
                                last_is_data            <=1'b1;
                                last_is_timec           <=1'b0;
                                last_was_control        <= last_is_control;
                                last_was_data           <= last_is_data ;
                                last_was_timec          <= last_is_timec;
                        end
                        else if(control[2:0] == 3'd7)
                        begin
                                timecode        <= dta_timec;
                                last_is_control         <= 1'b0;
                                last_is_data            <= 1'b0;
                                last_is_timec           <= 1'b1;
                                last_was_control        <= last_is_control;
                                last_was_data           <= last_is_data ;
                                last_was_timec          <= last_is_timec;
                        end
                end
                else if(last_is_timec == 1'b1)
                begin
                        rx_data_take <= 1'b0;
                        rx_tick_out  <= 1'b1;
                end
                else if(last_is_data == 1'b1)
                begin
 
                        rx_tick_out  <= 1'b0;
                        rx_data_take <= 1'b1;
                end
                else if(last_is_control == 1'b1)
                begin
 
                        if(control[2:0] == 3'd6)
                        begin
                                rx_data_flag <= 9'd257;
                                rx_data_take <= 1'b1;
                        end
                        else if(control[2:0] == 3'd5)
                        begin
                                rx_data_flag <= 9'd256;
                                rx_data_take <= 1'b1;
                        end
                        else
                        begin
                                rx_data_take    <= 1'b0;
                        end
 
                        rx_tick_out  <= 1'b0;
                end
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module RX_SPW (`
37			`input rx_din,`
38			`input rx_sin,`
39
40			`input rx_resetn,`
41
42	25	redbear	`output reg rx_error,`
43	5	redbear
44	33	redbear	`output reg rx_got_bit,`
45	25	redbear	`output reg rx_got_null,`
46			`output reg rx_got_nchar,`
47			`output reg rx_got_time_code,`
48	23	redbear	`output reg rx_got_fct,`
49	25	redbear	`output reg rx_got_fct_fsm,`
50	5	redbear
51	19	redbear	`output reg [8:0] rx_data_flag,`
52			`output reg rx_buffer_write,`
53	5	redbear
54	25	redbear	`output [7:0] rx_time_out,`
55	19	redbear	`output reg rx_tick_out`
56	5	redbear	`);`
57
58
59	33	redbear	`reg [5:0] counter_neg;`
60	25	redbear	`reg control_bit_found;`
61	33	redbear	`reg data_bit_found;`
62	5	redbear
63			`wire posedge_clk;`
64			`wire negedge_clk;`
65
66	14	redbear	`reg bit_c_0;//N`
67			`reg bit_c_1;//P`
68			`reg bit_c_2;//N`
69			`reg bit_c_3;//P`
70	5	redbear
71	14	redbear	`reg bit_d_0;//N`
72			`reg bit_d_1;//P`
73			`reg bit_d_2;//N`
74			`reg bit_d_3;//P`
75			`reg bit_d_4;//N`
76			`reg bit_d_5;//P`
77			`reg bit_d_6;//N`
78			`reg bit_d_7;//P`
79			`reg bit_d_8;//N`
80			`reg bit_d_9;//P`
81	5	redbear
82	14	redbear	`reg is_control;`
83	33	redbear	`//reg is_data;`
84	5	redbear
85	14	redbear	`reg last_is_control;`
86			`reg last_is_data;`
87			`reg last_is_timec;`
88	5	redbear
89			`reg last_was_control;`
90			`reg last_was_data;`
91	14	redbear	`reg last_was_timec;`
92	5	redbear
93	14	redbear	`reg [3:0] control;`
94	23	redbear	`reg [3:0] control_r;`
95	33	redbear	`reg [3:0] control_p_r;`
96	14	redbear	`reg [9:0] data;`
97			`reg [9:0] timecode;`
98	5	redbear
99	14	redbear	`reg [3:0] control_l_r;`
100			`reg [9:0] data_l_r;`
101	5	redbear
102	23	redbear	`reg [9:0] dta_timec;`
103	33	redbear	`reg [9:0] dta_timec_p;`
104	23	redbear
105	19	redbear	`reg rx_data_take;`
106	25	redbear	`reg rx_data_take_0;`
107	19	redbear
108	33	redbear	`reg ready_control;`
109			`reg ready_data;`
110	23	redbear
111	33	redbear	`reg ready_control_p;`
112			`reg ready_data_p;`
113
114			`reg ready_control_p_r;`
115			`reg ready_data_p_r;`
116
117			`reg posedge_p;`
118	25	redbear
119	14	redbear	`//CLOCK RECOVERY`
120	33	redbear	`assign posedge_clk = posedge_p;`
121			`assign negedge_clk = !posedge_p;`
122	5	redbear
123	25	redbear	`assign rx_time_out = timecode[7:0];`
124	5	redbear
125	33	redbear	`always@(*)`
126			`begin`
127	5	redbear
128	33	redbear	`rx_got_bit = 1'b0;`
129
130			`if(rx_din \| rx_sin)`
131			`begin`
132			`rx_got_bit = 1'b1;`
133			`end`
134			`end`
135
136			`always@(*)`
137			`begin`
138			`ready_control = 1'b0;`
139			`ready_data = 1'b0;`
140
141			`if(counter_neg[5:0] == 6'd4 && !posedge_p)`
142			`begin`
143			`ready_control = 1'b1;`
144			`end`
145			`else if(counter_neg[5:0] == 6'd32 && !posedge_p)`
146			`begin`
147			`ready_data = 1'b1;`
148			`end`
149			`end`
150
151
152			`always@(*)`
153			`begin`
154			`ready_control_p = 1'b0;`
155			`ready_data_p = 1'b0;`
156
157			`if(counter_neg[5:0] == 6'd4 && posedge_p)`
158			`begin`
159			`ready_control_p = 1'b1;`
160			`end`
161			`else if(counter_neg[5:0] == 6'd32 && posedge_p)`
162			`begin`
163			`ready_data_p = 1'b1;`
164			`end`
165			`end`
166
167			`always@(*)`
168			`begin`
169			`posedge_p = 1'b0;`
170
171	34	redbear	`if(rx_din ^ rx_sin)`
172	33	redbear	`begin`
173			`posedge_p = 1'b1;`
174			`end`
175			`else`
176			`begin`
177			`posedge_p = 1'b0;`
178			`end`
179			`end`
180
181	14	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
182	5	redbear	`begin`
183	14	redbear
184			`if(!rx_resetn)`
185	5	redbear	`begin`
186	25	redbear	`bit_d_1 <= 1'b0;`
187			`bit_d_3 <= 1'b0;`
188			`bit_d_5 <= 1'b0;`
189			`bit_d_7 <= 1'b0;`
190			`bit_d_9 <= 1'b0;`
191	5	redbear	`end`
192			`else`
193			`begin`
194	25	redbear	`bit_d_1 <= rx_din;`
195			`bit_d_3 <= bit_d_1;`
196			`bit_d_5 <= bit_d_3;`
197			`bit_d_7 <= bit_d_5;`
198			`bit_d_9 <= bit_d_7;`
199	5	redbear	`end`
200	14	redbear
201	5	redbear	`end`
202
203	14	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
204	5	redbear	`begin`
205	14	redbear
206			`if(!rx_resetn)`
207	5	redbear	`begin`
208	14	redbear	`bit_d_0 <= 1'b0;`
209			`bit_d_2 <= 1'b0;`
210			`bit_d_4 <= 1'b0;`
211			`bit_d_6 <= 1'b0;`
212			`bit_d_8 <= 1'b0;`
213	25	redbear
214	5	redbear	`end`
215			`else`
216			`begin`
217	14	redbear	`bit_d_0 <= rx_din;`
218			`bit_d_2 <= bit_d_0;`
219			`bit_d_4 <= bit_d_2;`
220			`bit_d_6 <= bit_d_4;`
221			`bit_d_8 <= bit_d_6;`
222	23	redbear	`end`
223			`end`
224	14	redbear
225	25	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
226	23	redbear	`begin`
227	25	redbear
228			`if(!rx_resetn)`
229	23	redbear	`begin`
230	25	redbear	`bit_c_1 <= 1'b0;`
231			`bit_c_3 <= 1'b0;`
232	23	redbear	`end`
233	25	redbear	`else`
234			`begin`
235			`bit_c_1 <= rx_din;`
236			`bit_c_3 <= bit_c_1;`
237			`end`
238
239	23	redbear	`end`
240
241	25	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
242	23	redbear	`begin`
243
244	25	redbear	`if(!rx_resetn)`
245	23	redbear	`begin`
246	25	redbear	`bit_c_0 <= 1'b0;`
247			`bit_c_2 <= 1'b0;`
248	23	redbear	`end`
249	25	redbear	`else`
250	23	redbear	`begin`
251	25	redbear	`bit_c_0 <= rx_din;`
252			`bit_c_2 <= bit_c_0;`
253	23	redbear	`end`
254			`end`
255
256			`always@(posedge negedge_clk or negedge rx_resetn)`
257			`begin`
258
259			`if(!rx_resetn)`
260			`begin`
261	33	redbear	`rx_got_fct <= 1'b0;`
262	23	redbear	`end`
263			`else`
264	33	redbear	`begin`
265			`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))`
266	5	redbear	`begin`
267	33	redbear	`rx_got_fct <= 1'b1;`
268	5	redbear	`end`
269			`else`
270			`begin`
271	33	redbear	`rx_got_fct <= 1'b0;`
272	5	redbear	`end`
273	25	redbear	`end`
274			`end`
275
276			`always@(posedge negedge_clk or negedge rx_resetn)`
277			`begin`
278
279
280			`if(!rx_resetn)`
281			`begin`
282			`rx_error <= 1'b0;`
283			`end`
284			`else`
285			`begin`
286	33	redbear	`if(last_is_control == 1'b1)`
287	5	redbear	`begin`
288	33	redbear	`if(last_was_control == 1'b1)`
289	14	redbear	`begin`
290	25	redbear	`if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])`
291			`begin`
292			`rx_error <= 1'b1;`
293			`end`
294	33	redbear	`else`
295			`begin`
296			`rx_error <= 1'b0;`
297			`end`
298	14	redbear	`end`
299	33	redbear	`else if(last_was_timec == 1'b1)`
300	25	redbear	`begin`
301			`if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])`
302			`begin`
303			`rx_error <= 1'b1;`
304			`end`
305	33	redbear	`else`
306			`begin`
307			`rx_error <= 1'b0;`
308			`end`
309	25	redbear	`end`
310	33	redbear	`else if(last_was_data == 1'b1)`
311	25	redbear	`begin`
312			`if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])`
313			`begin`
314			`rx_error <= 1'b1;`
315			`end`
316	33	redbear	`else`
317			`begin`
318			`rx_error <= 1'b0;`
319			`end`
320	25	redbear	`end`
321
322	5	redbear	`end`
323	33	redbear	`else if(last_is_data == 1'b1)`
324	5	redbear	`begin`
325	33	redbear	`if(last_was_control == 1'b1)`
326	14	redbear	`begin`
327	25	redbear	`if(!(data[8]^control[1]^control[0]) != data[9])`
328			`begin`
329			`rx_error <= 1'b1;`
330			`end`
331	33	redbear	`else`
332			`begin`
333			`rx_error <= 1'b0;`
334			`end`
335	14	redbear	`end`
336	33	redbear	`else if(last_was_timec == 1'b1)`
337	25	redbear	`begin`
338			`if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])`
339			`begin`
340			`rx_error <= 1'b1;`
341			`end`
342	33	redbear	`else`
343			`begin`
344			`rx_error <= 1'b0;`
345			`end`
346	25	redbear	`end`
347	33	redbear	`else if(last_was_data == 1'b1)`
348	25	redbear	`begin`
349			`if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])`
350			`begin`
351			`rx_error <= 1'b1;`
352			`end`
353	33	redbear	`else`
354			`begin`
355			`rx_error <= 1'b0;`
356			`end`
357	25	redbear	`end`
358	5	redbear	`end`
359	25	redbear
360	5	redbear	`end`
361	25	redbear	`end`
362
363			`always@(posedge negedge_clk or negedge rx_resetn)`
364			`begin`
365
366			`if(!rx_resetn)`
367	5	redbear	`begin`
368	25	redbear	`rx_got_null <= 1'b0;`
369			`rx_got_nchar <= 1'b0;`
370			`rx_got_time_code <= 1'b0;`
371			`end`
372			`else`
373			`begin`
374	33	redbear	`if(last_is_data == 1'b1 )`
375	5	redbear	`begin`
376	25	redbear	`rx_got_nchar <= 1'b1;`
377	5	redbear	`end`
378	33	redbear	`else if(last_is_timec == 1'b1)`
379	5	redbear	`begin`
380	25	redbear	`rx_got_time_code <= 1'b1;`
381	5	redbear	`end`
382	33	redbear	`else if(last_is_control == 1'b1)`
383	5	redbear	`begin`
384	25	redbear	`rx_got_null <= 1'b1;`
385	5	redbear	`end`
386	25	redbear	`else`
387			`begin`
388	33	redbear	`rx_got_null <= 1'b0;`
389			`rx_got_nchar <= 1'b0;`
390			`rx_got_time_code <= 1'b0;`
391	25	redbear	`end`
392	5	redbear	`end`
393			`end`
394
395	25	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
396	5	redbear	`begin`
397	25	redbear	`if(!rx_resetn)`
398			`begin`
399	33	redbear	`rx_got_fct_fsm <= 1'b0;`
400	25	redbear	`rx_buffer_write <= 1'b0;`
401			`rx_data_take_0 <= 1'b0;`
402	33	redbear	`ready_control_p_r <= 1'b0;`
403			`ready_data_p_r <= 1'b0;`
404
405	25	redbear	`end`
406			`else`
407			`begin`
408			`rx_data_take_0 <= rx_data_take;`
409			`rx_buffer_write <= rx_data_take_0;`
410	5	redbear
411	33	redbear
412			`if(ready_control \|\| ready_control_p)`
413			`begin`
414			`if(is_control)`
415			`ready_control_p_r <= 1'b1;`
416			`end`
417			`else`
418			`begin`
419			`ready_control_p_r <= 1'b0;`
420			`end`
421
422			`if(ready_data \|\| ready_data_p)`
423			`begin`
424			`if(!is_control)`
425			`ready_data_p_r <= 1'b1;`
426			`end`
427			`else`
428			`begin`
429			`ready_data_p_r <= 1'b0;`
430			`end`
431
432			`if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)`
433	25	redbear	`rx_got_fct_fsm <= 1'b1;`
434			`else`
435			`rx_got_fct_fsm <= rx_got_fct_fsm;`
436			`end`
437			`end`
438
439			`always@(posedge ready_control or negedge rx_resetn )`
440			`begin`
441	14	redbear	`if(!rx_resetn)`
442	5	redbear	`begin`
443	25	redbear	`control_r <= 4'd0;`
444			`end`
445			`else`
446			`begin`
447	33	redbear	`//if(is_control)`
448	25	redbear	`control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`
449			`end`
450			`end`
451	23	redbear
452	33	redbear	`always@(posedge ready_control_p or negedge rx_resetn )`
453			`begin`
454			`if(!rx_resetn)`
455			`begin`
456			`control_p_r <= 4'd0;`
457			`end`
458			`else`
459			`begin`
460			`//if(is_control)`
461			`control_p_r <= control_r;`
462			`end`
463			`end`
464	5	redbear
465	33	redbear
466
467	25	redbear	`always@(posedge ready_data or negedge rx_resetn )`
468			`begin`
469			`if(!rx_resetn)`
470			`begin`
471			`dta_timec <= 10'd0;`
472			`end`
473			`else`
474			`begin`
475	33	redbear	`//if(!is_control)`
476	25	redbear	`dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
477			`end`
478			`end`
479	5	redbear
480	33	redbear
481			`always@(posedge ready_data_p or negedge rx_resetn )`
482			`begin`
483			`if(!rx_resetn)`
484			`begin`
485			`dta_timec_p <= 10'd0;`
486			`end`
487			`else`
488			`begin`
489			`//if(!is_control)`
490			`dta_timec_p <= dta_timec;`
491			`end`
492			`end`
493
494			`always@(posedge negedge_clk or negedge rx_resetn)`
495			`begin`
496
497			`if(!rx_resetn)`
498			`begin`
499			`is_control <= 1'b0;`
500			`control_bit_found <= 1'b0;`

Browse

Tools

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Blame information for rev 34