URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Blame information for rev 37

Go to most recent revision | Details | Compare with Previous | View Log


//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module RX_SPW (
                        input  rx_din,
                        input  rx_sin,
 
                        input  rx_resetn,
 
                        output rx_error,
 
                        output reg rx_got_bit,
                        output reg rx_got_null,
                        output reg rx_got_nchar,
                        output reg rx_got_time_code,
                        output reg rx_got_fct,
                        output reg rx_got_fct_fsm,
 
                        output reg [8:0] rx_data_flag,
                        output reg rx_buffer_write,
 
                        output [7:0] rx_time_out,
                        output reg rx_tick_out
                 );
 
 
        reg  [5:0] counter_neg;
        reg control_bit_found;
        reg data_bit_found;
 
        wire posedge_clk;
        wire negedge_clk;
 
        reg  [1:0] state_data_process;
        reg  [1:0] next_state_data_process;
 
        reg bit_c_0;//N
        reg bit_c_1;//P
        reg bit_c_2;//N
        reg bit_c_3;//P
 
        reg bit_d_0;//N
        reg bit_d_1;//P
        reg bit_d_2;//N
        reg bit_d_3;//P
        reg bit_d_4;//N
        reg bit_d_5;//P
        reg bit_d_6;//N
        reg bit_d_7;//P
        reg bit_d_8;//N
        reg bit_d_9;//P
 
        reg is_control;
        reg parity_received;
 
        reg last_is_control;
        reg last_is_data;
        reg last_is_timec;
 
        //reg last_was_control;
        //reg last_was_data;
        //reg last_was_timec;
 
        reg [3:0] control;
        reg [3:0] control_r;
        reg [3:0] control_p_r;
        reg [9:0] data;
        reg [9:0] timecode;
 
        reg [3:0] control_l_r;
        //reg [9:0] data_l_r;
 
        reg [9:0] dta_timec;
        reg [9:0] dta_timec_p;
 
        reg rx_data_take;
        reg rx_data_take_0;
 
        reg rx_got_fct_take;
        reg rx_got_fct_take_0;
        reg rx_got_fct_take_1;
        reg rx_got_fct_take_2;
        reg rx_got_fct_take_3;
 
        reg ready_control;
        reg ready_data;
 
        reg ready_control_p;
        reg ready_data_p;
 
        reg ready_control_p_r;
        reg ready_data_p_r;
 
        reg parity_rec_c;
        reg parity_rec_d;
 
        reg rx_error_c;
        reg rx_error_d;
 
        reg posedge_p;
 
        //CLOCK RECOVERY
        assign posedge_clk      = posedge_p;
        assign negedge_clk      = !posedge_p;
 
        assign rx_time_out      = timecode[7:0];
 
        assign rx_error         = rx_error_c | rx_error_d;
 
always@(*)
begin
 
        rx_got_bit = 1'b0;
 
        if(rx_din | rx_sin)
        begin
                rx_got_bit = 1'b1;
        end
end
 
always@(*)
begin
        ready_control    = 1'b0;
        ready_data       = 1'b0;
 
        if(counter_neg[5:0] == 6'd4 && !posedge_p)
        begin
                ready_control = 1'b1;
        end
        else if(counter_neg[5:0] == 6'd32 && !posedge_p)
        begin
                ready_data       = 1'b1;
        end
end
 
 
always@(*)
begin
        ready_control_p    = 1'b0;
        ready_data_p       = 1'b0;
 
        if(counter_neg[5:0] == 6'd4 && posedge_p)
        begin
                ready_control_p = 1'b1;
        end
        else if(counter_neg[5:0] == 6'd32 && posedge_p)
        begin
                ready_data_p       = 1'b1;
        end
end
 
always@(*)
begin
        posedge_p = 1'b0;
 
        if(rx_din ^ rx_sin)
        begin
                posedge_p = 1'b1;
        end
        else
        begin
                posedge_p = 1'b0;
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_d_1  <= 1'b0;
                bit_d_3  <= 1'b0;
                bit_d_5  <= 1'b0;
                bit_d_7  <= 1'b0;
                bit_d_9  <= 1'b0;
        end
        else
        begin
                bit_d_1  <= rx_din;
                bit_d_3  <= bit_d_1;
                bit_d_5  <= bit_d_3;
                bit_d_7  <= bit_d_5;
                bit_d_9  <= bit_d_7;
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_d_0 <= 1'b0;
                bit_d_2 <= 1'b0;
                bit_d_4 <= 1'b0;
                bit_d_6 <= 1'b0;
                bit_d_8 <= 1'b0;
 
        end
        else
        begin
                bit_d_0 <= rx_din;
                bit_d_2 <= bit_d_0;
                bit_d_4 <= bit_d_2;
                bit_d_6 <= bit_d_4;
                bit_d_8 <= bit_d_6;
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_1   <= 1'b0;
                bit_c_3   <= 1'b0;
        end
        else
        begin
                bit_c_1 <= rx_din;
                bit_c_3 <= bit_c_1;
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_0   <= 1'b0;
                bit_c_2   <= 1'b0;
        end
        else
        begin
                bit_c_0 <= rx_din;
                bit_c_2 <= bit_c_0;
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                rx_got_fct        <= 1'b0;
                rx_got_fct_take   <= 1'b0;
                rx_got_fct_take_0 <= 1'b0;
                rx_got_fct_take_1 <= 1'b0;
                rx_got_fct_take_2 <= 1'b0;
                rx_got_fct_take_3 <= 1'b0;
        end
        else
        begin
                if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
                begin
                        rx_got_fct_take <= 1'b1;
                        rx_got_fct_take_0 <= rx_got_fct_take;
                        rx_got_fct_take_1 <= rx_got_fct_take_0;
                        rx_got_fct_take_2 <= rx_got_fct_take_1;
                        rx_got_fct_take_3 <= rx_got_fct_take_2;
                        rx_got_fct <= rx_got_fct_take | rx_got_fct_take_0 | rx_got_fct_take_1 | rx_got_fct_take_2 | rx_got_fct_take_3;
                end
                else
                begin
                        rx_got_fct_take <= 1'b0;
                        rx_got_fct_take_0 <= rx_got_fct_take;
                        rx_got_fct_take_1 <= rx_got_fct_take_0;
                        rx_got_fct_take_2 <= rx_got_fct_take_1;
                        rx_got_fct_take_3 <= rx_got_fct_take_2;
                        rx_got_fct <= rx_got_fct_take | rx_got_fct_take_0 | rx_got_fct_take_1 | rx_got_fct_take_2 | rx_got_fct_take_3;
                end
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                rx_got_null       <= 1'b0;
                rx_got_nchar      <= 1'b0;
                rx_got_time_code  <= 1'b0;
        end
        else
        begin
                if(last_is_data == 1'b1 )
                begin
                        rx_got_nchar      <= 1'b1;
                end
                else if(last_is_timec  == 1'b1)
                begin
                        rx_got_time_code  <= 1'b1;
                end
                else if(last_is_control == 1'b1)
                begin
                        rx_got_null       <= 1'b1;
                end
                else
                begin
                        rx_got_null       <= 1'b0;
                        rx_got_nchar      <= 1'b0;
                        rx_got_time_code  <= 1'b0;
                end
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
        if(!rx_resetn)
        begin
                rx_got_fct_fsm  <=  1'b0;
                rx_buffer_write <=  1'b0;
                rx_data_take_0  <=  1'b0;
                ready_control_p_r <= 1'b0;
                ready_data_p_r  <=  1'b0;
 
        end
        else
        begin
                rx_data_take_0 <= rx_data_take;
                rx_buffer_write  <= rx_data_take_0;
 
 
                if(ready_control || ready_control_p)
                begin
                        if(is_control)
                                ready_control_p_r <= 1'b1;
                        else
                                ready_control_p_r <= 1'b0;
                end
                else
                begin
                        ready_control_p_r <= 1'b0;
                end
 
                if(ready_data || ready_data_p)
                begin
                        if(!is_control)
                                ready_data_p_r <= 1'b1;
                        else
                                ready_data_p_r <= 1'b0;
                end
                else
                begin
                        ready_data_p_r <= 1'b0;
                end
 
                if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
                        rx_got_fct_fsm <= 1'b1;
                else
                        rx_got_fct_fsm <= rx_got_fct_fsm;
        end
end
 
always@(posedge ready_control or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                control_r               <= 4'd0;
                parity_rec_c            <= 1'b0;
        end
        else
        begin
                control_r         <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
                parity_rec_c      <= bit_c_3;
        end
end
 
always@(posedge ready_control_p or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                control_p_r             <= 4'd0;
 
        end
        else
        begin
                control_p_r       <= control_r;
        end
end
 
 
 
always@(posedge ready_data or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                dta_timec               <= 10'd0;
                parity_rec_d            <= 1'b0;
        end
        else
        begin
                dta_timec         <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
                parity_rec_d      <= bit_d_9;
        end
end
 
 
always@(posedge ready_data_p or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                dta_timec_p             <= 10'd0;
        end
        else
        begin
                dta_timec_p  <= dta_timec;
        end
end
 
always@(*)
begin
 
        rx_error_d = 1'b0;
 
        if(last_is_control && ready_data_p)
        begin
                if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)
                begin
                        rx_error_d = 1'b1;
                end
        end
        else if(last_is_data && ready_data_p)
        begin
                if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)
                begin
                        rx_error_d = 1'b1;
                end
        end
end
 
always@(*)
begin
 
        rx_error_c = 1'b0;
 
        if(last_is_control && ready_control_p)
        begin
                if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
                begin
                        rx_error_c = 1'b1;
                end
        end
        else if(last_is_data && ready_control_p)
        begin
                if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)
                begin
                        rx_error_c = 1'b1;
                end
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                is_control <= 1'b0;
                control_bit_found <= 1'b0;
                counter_neg[5:0]  <= 6'd1;
        end
        else
        begin
 
                control_bit_found <= rx_din;
 
                case(counter_neg)
                6'd1:
                begin
                        counter_neg[5:0]  <=  6'd2;
                end
                6'd2:
                begin
                        if(control_bit_found == 1'b1)
                        begin
                                is_control  <= 1'b1;
                        end
                        else
                        begin
                                is_control  <= 1'b0;
                        end
 
                        counter_neg[5:0] <= 6'd4;
                end
                6'd4:
                begin
                        if(is_control == 1'b1)
                        begin
                                counter_neg[5:0] <= 6'd2;
                                is_control <= 1'b0;
                        end
                        else
                        begin
                                counter_neg[5:0] <= 6'd8;
                        end
                end
                6'd8:
                begin
                        counter_neg[5:0] <= 6'd16;
                end
                6'd16:
                begin
                        counter_neg[5:0] <= 6'd32;
                end
                6'd32:
                begin
                        is_control <= 1'b0;
                        counter_neg[5:0] <= 6'd2;
                end
                default:
                begin
                        is_control <= is_control;
                        counter_neg[5:0] <= counter_neg[5:0];
                end
                endcase
 
        end
end
 
always@(*)
begin
 
        next_state_data_process = state_data_process;
 
        case(state_data_process)
        2'd0:
        begin
                if(ready_control_p_r || ready_data_p_r)
                begin
                        next_state_data_process = 2'd1;
                end
                else
                begin
                        next_state_data_process = 2'd0;
                end
        end
        2'd1:
        begin
                next_state_data_process = 2'd0;
        end
        default:
        begin
                next_state_data_process = 2'd0;
        end
        endcase
end
 
 
always@(posedge negedge_clk or negedge rx_resetn )
begin
 
        if(!rx_resetn)
        begin
                control_l_r      <= 4'd0;
                control          <= 4'd0;
                data             <=  10'd0;
                //data_l_r         <=  10'd0;
 
                last_is_control  <=  1'b0;
                last_is_data     <=  1'b0;
                last_is_timec    <=  1'b0;
 
                //last_was_control <= 1'b0;
                //last_was_data    <= 1'b0;
                //last_was_timec   <= 1'b0;
 
                rx_data_flag     <=  9'd0;
                rx_data_take     <=  1'b0;
 
                timecode         <=  10'd0;
                rx_tick_out      <=  1'b0;
 
                state_data_process <= 2'd0;
        end
        else
        begin
 
                state_data_process <= next_state_data_process;
 
                case(state_data_process)
                2'd0:
                begin
 
                        if(ready_control_p_r)
                        begin
                                control          <= control_p_r;
                                control_l_r      <= control;
 
                                last_is_control          <= 1'b1;
                                last_is_data             <= 1'b0;
                                last_is_timec            <= 1'b0;
                                //last_was_control       <= last_is_control;
                                //last_was_data          <= last_is_data ;
                                //last_was_timec         <= last_is_timec;
 
                                rx_data_take <= 1'b0;
                                rx_tick_out  <= 1'b0;
 
                        end
                        else if(ready_data_p_r)
                        begin
                                if(control[2:0] != 3'd7)
                                begin
                                        data            <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
                                        //data_l_r      <= data; 
                                        last_is_control         <=1'b0;
                                        last_is_data            <=1'b1;
                                        last_is_timec           <=1'b0;
                                        //last_was_control      <= last_is_control;
                                        //last_was_data         <= last_is_data ;
                                        //last_was_timec                <= last_is_timec;
                                end
                                else if(control[2:0] == 3'd7)
                                begin
                                        last_is_control         <= 1'b0;
                                        last_is_data            <= 1'b0;
                                        last_is_timec           <= 1'b1;
                                        //last_was_control      <= last_is_control;
                                        //last_was_data         <= last_is_data ;
                                        //last_was_timec        <= last_is_timec;
                                end
 
                                rx_data_take <= 1'b0;
                                rx_tick_out  <= 1'b0;
                        end
                        else
                        begin
                                timecode        <= timecode;
                        end
 
                end
                2'd1:
                begin
 
                        if(last_is_timec == 1'b1)
                        begin
                                timecode     <= dta_timec;
                                rx_tick_out  <= 1'b1;
                        end
                        else if(last_is_data == 1'b1)
                        begin
                                rx_data_flag    <= {data[8],data[7],data[6],data[5],data[4],data[3],data[2],data[1],data[0]};
                                rx_data_take <= 1'b1;
                        end
                        else if(last_is_control == 1'b1)
                        begin
                                if(control[2:0] == 3'd6)
                                begin
                                        rx_data_flag <= 9'd257;
                                        rx_data_take <= 1'b1;
                                end
                                else if(control[2:0] == 3'd5)
                                begin
                                        rx_data_flag <= 9'd256;
                                        rx_data_take <= 1'b1;
                                end
                                else
                                begin
                                        rx_data_take    <= rx_data_take;
                                        rx_tick_out     <= rx_tick_out;
                                end
 
                        end
                        else
                        begin
 
                                rx_data_flag    <= rx_data_flag;
                                rx_data_take    <= rx_data_take;
 
                                timecode        <= timecode;
                                rx_tick_out     <= rx_tick_out;
                        end
 
                end
                default:
                begin
                                rx_data_flag    <= rx_data_flag;
                                rx_data_take    <= rx_data_take;
 
                                timecode        <= timecode;
                                rx_tick_out     <= rx_tick_out;
                end
                endcase
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module RX_SPW (`
37			`input rx_din,`
38			`input rx_sin,`
39
40			`input rx_resetn,`
41
42	37	redbear	`output rx_error,`
43	5	redbear
44	33	redbear	`output reg rx_got_bit,`
45	25	redbear	`output reg rx_got_null,`
46			`output reg rx_got_nchar,`
47			`output reg rx_got_time_code,`
48	23	redbear	`output reg rx_got_fct,`
49	25	redbear	`output reg rx_got_fct_fsm,`
50	5	redbear
51	19	redbear	`output reg [8:0] rx_data_flag,`
52			`output reg rx_buffer_write,`
53	5	redbear
54	25	redbear	`output [7:0] rx_time_out,`
55	19	redbear	`output reg rx_tick_out`
56	5	redbear	`);`
57
58
59	33	redbear	`reg [5:0] counter_neg;`
60	25	redbear	`reg control_bit_found;`
61	33	redbear	`reg data_bit_found;`
62	5	redbear
63			`wire posedge_clk;`
64			`wire negedge_clk;`
65
66	37	redbear	`reg [1:0] state_data_process;`
67			`reg [1:0] next_state_data_process;`
68
69	14	redbear	`reg bit_c_0;//N`
70			`reg bit_c_1;//P`
71			`reg bit_c_2;//N`
72			`reg bit_c_3;//P`
73	5	redbear
74	14	redbear	`reg bit_d_0;//N`
75			`reg bit_d_1;//P`
76			`reg bit_d_2;//N`
77			`reg bit_d_3;//P`
78			`reg bit_d_4;//N`
79			`reg bit_d_5;//P`
80			`reg bit_d_6;//N`
81			`reg bit_d_7;//P`
82			`reg bit_d_8;//N`
83			`reg bit_d_9;//P`
84	5	redbear
85	14	redbear	`reg is_control;`
86	37	redbear	`reg parity_received;`
87	5	redbear
88	14	redbear	`reg last_is_control;`
89			`reg last_is_data;`
90			`reg last_is_timec;`
91	5	redbear
92	37	redbear	`//reg last_was_control;`
93			`//reg last_was_data;`
94			`//reg last_was_timec;`
95	5	redbear
96	14	redbear	`reg [3:0] control;`
97	23	redbear	`reg [3:0] control_r;`
98	33	redbear	`reg [3:0] control_p_r;`
99	14	redbear	`reg [9:0] data;`
100			`reg [9:0] timecode;`
101	5	redbear
102	14	redbear	`reg [3:0] control_l_r;`
103	37	redbear	`//reg [9:0] data_l_r;`
104	5	redbear
105	23	redbear	`reg [9:0] dta_timec;`
106	33	redbear	`reg [9:0] dta_timec_p;`
107	23	redbear
108	19	redbear	`reg rx_data_take;`
109	25	redbear	`reg rx_data_take_0;`
110	19	redbear
111	37	redbear	`reg rx_got_fct_take;`
112			`reg rx_got_fct_take_0;`
113			`reg rx_got_fct_take_1;`
114			`reg rx_got_fct_take_2;`
115			`reg rx_got_fct_take_3;`
116
117	33	redbear	`reg ready_control;`
118			`reg ready_data;`
119	23	redbear
120	33	redbear	`reg ready_control_p;`
121			`reg ready_data_p;`
122
123			`reg ready_control_p_r;`
124			`reg ready_data_p_r;`
125
126	37	redbear	`reg parity_rec_c;`
127			`reg parity_rec_d;`
128
129			`reg rx_error_c;`
130			`reg rx_error_d;`
131
132	33	redbear	`reg posedge_p;`
133	25	redbear
134	14	redbear	`//CLOCK RECOVERY`
135	33	redbear	`assign posedge_clk = posedge_p;`
136			`assign negedge_clk = !posedge_p;`
137	5	redbear
138	25	redbear	`assign rx_time_out = timecode[7:0];`
139	5	redbear
140	37	redbear	`assign rx_error = rx_error_c \| rx_error_d;`
141
142	33	redbear	`always@(*)`
143			`begin`
144	5	redbear
145	33	redbear	`rx_got_bit = 1'b0;`
146
147			`if(rx_din \| rx_sin)`
148			`begin`
149			`rx_got_bit = 1'b1;`
150			`end`
151			`end`
152
153			`always@(*)`
154			`begin`
155			`ready_control = 1'b0;`
156			`ready_data = 1'b0;`
157
158			`if(counter_neg[5:0] == 6'd4 && !posedge_p)`
159			`begin`
160			`ready_control = 1'b1;`
161			`end`
162			`else if(counter_neg[5:0] == 6'd32 && !posedge_p)`
163			`begin`
164			`ready_data = 1'b1;`
165			`end`
166			`end`
167
168
169			`always@(*)`
170			`begin`
171			`ready_control_p = 1'b0;`
172			`ready_data_p = 1'b0;`
173
174			`if(counter_neg[5:0] == 6'd4 && posedge_p)`
175			`begin`
176			`ready_control_p = 1'b1;`
177			`end`
178			`else if(counter_neg[5:0] == 6'd32 && posedge_p)`
179			`begin`
180			`ready_data_p = 1'b1;`
181			`end`
182			`end`
183
184			`always@(*)`
185			`begin`
186			`posedge_p = 1'b0;`
187
188	34	redbear	`if(rx_din ^ rx_sin)`
189	33	redbear	`begin`
190			`posedge_p = 1'b1;`
191			`end`
192			`else`
193			`begin`
194			`posedge_p = 1'b0;`
195			`end`
196			`end`
197
198	14	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
199	5	redbear	`begin`
200	14	redbear
201			`if(!rx_resetn)`
202	5	redbear	`begin`
203	25	redbear	`bit_d_1 <= 1'b0;`
204			`bit_d_3 <= 1'b0;`
205			`bit_d_5 <= 1'b0;`
206			`bit_d_7 <= 1'b0;`
207			`bit_d_9 <= 1'b0;`
208	5	redbear	`end`
209			`else`
210			`begin`
211	25	redbear	`bit_d_1 <= rx_din;`
212			`bit_d_3 <= bit_d_1;`
213			`bit_d_5 <= bit_d_3;`
214			`bit_d_7 <= bit_d_5;`
215			`bit_d_9 <= bit_d_7;`
216	5	redbear	`end`
217	14	redbear
218	5	redbear	`end`
219
220	14	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
221	5	redbear	`begin`
222	14	redbear
223			`if(!rx_resetn)`
224	5	redbear	`begin`
225	14	redbear	`bit_d_0 <= 1'b0;`
226			`bit_d_2 <= 1'b0;`
227			`bit_d_4 <= 1'b0;`
228			`bit_d_6 <= 1'b0;`
229			`bit_d_8 <= 1'b0;`
230	25	redbear
231	5	redbear	`end`
232			`else`
233			`begin`
234	14	redbear	`bit_d_0 <= rx_din;`
235			`bit_d_2 <= bit_d_0;`
236			`bit_d_4 <= bit_d_2;`
237			`bit_d_6 <= bit_d_4;`
238			`bit_d_8 <= bit_d_6;`
239	23	redbear	`end`
240			`end`
241	14	redbear
242	25	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
243	23	redbear	`begin`
244	25	redbear
245			`if(!rx_resetn)`
246	23	redbear	`begin`
247	25	redbear	`bit_c_1 <= 1'b0;`
248			`bit_c_3 <= 1'b0;`
249	23	redbear	`end`
250	25	redbear	`else`
251			`begin`
252			`bit_c_1 <= rx_din;`
253			`bit_c_3 <= bit_c_1;`
254			`end`
255
256	23	redbear	`end`
257
258	25	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
259	23	redbear	`begin`
260
261	25	redbear	`if(!rx_resetn)`
262	23	redbear	`begin`
263	25	redbear	`bit_c_0 <= 1'b0;`
264			`bit_c_2 <= 1'b0;`
265	23	redbear	`end`
266	25	redbear	`else`
267	23	redbear	`begin`
268	25	redbear	`bit_c_0 <= rx_din;`
269			`bit_c_2 <= bit_c_0;`
270	23	redbear	`end`
271			`end`
272
273			`always@(posedge negedge_clk or negedge rx_resetn)`
274			`begin`
275
276			`if(!rx_resetn)`
277			`begin`
278	37	redbear	`rx_got_fct <= 1'b0;`
279			`rx_got_fct_take <= 1'b0;`
280			`rx_got_fct_take_0 <= 1'b0;`
281			`rx_got_fct_take_1 <= 1'b0;`
282			`rx_got_fct_take_2 <= 1'b0;`
283			`rx_got_fct_take_3 <= 1'b0;`
284	23	redbear	`end`
285			`else`
286	33	redbear	`begin`
287			`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))`
288	5	redbear	`begin`
289	37	redbear	`rx_got_fct_take <= 1'b1;`
290			`rx_got_fct_take_0 <= rx_got_fct_take;`
291			`rx_got_fct_take_1 <= rx_got_fct_take_0;`
292			`rx_got_fct_take_2 <= rx_got_fct_take_1;`
293			`rx_got_fct_take_3 <= rx_got_fct_take_2;`
294			`rx_got_fct <= rx_got_fct_take \| rx_got_fct_take_0 \| rx_got_fct_take_1 \| rx_got_fct_take_2 \| rx_got_fct_take_3;`
295	5	redbear	`end`
296			`else`
297			`begin`
298	37	redbear	`rx_got_fct_take <= 1'b0;`
299			`rx_got_fct_take_0 <= rx_got_fct_take;`
300			`rx_got_fct_take_1 <= rx_got_fct_take_0;`
301			`rx_got_fct_take_2 <= rx_got_fct_take_1;`
302			`rx_got_fct_take_3 <= rx_got_fct_take_2;`
303			`rx_got_fct <= rx_got_fct_take \| rx_got_fct_take_0 \| rx_got_fct_take_1 \| rx_got_fct_take_2 \| rx_got_fct_take_3;`
304	5	redbear	`end`
305	25	redbear	`end`
306			`end`
307
308			`always@(posedge negedge_clk or negedge rx_resetn)`
309			`begin`
310
311			`if(!rx_resetn)`
312			`begin`
313			`rx_got_null <= 1'b0;`
314			`rx_got_nchar <= 1'b0;`
315			`rx_got_time_code <= 1'b0;`
316			`end`
317			`else`
318			`begin`
319	33	redbear	`if(last_is_data == 1'b1 )`
320	5	redbear	`begin`
321	25	redbear	`rx_got_nchar <= 1'b1;`
322	5	redbear	`end`
323	33	redbear	`else if(last_is_timec == 1'b1)`
324	5	redbear	`begin`
325	25	redbear	`rx_got_time_code <= 1'b1;`
326	5	redbear	`end`
327	33	redbear	`else if(last_is_control == 1'b1)`
328	5	redbear	`begin`
329	25	redbear	`rx_got_null <= 1'b1;`
330	5	redbear	`end`
331	25	redbear	`else`
332			`begin`
333	33	redbear	`rx_got_null <= 1'b0;`
334			`rx_got_nchar <= 1'b0;`
335			`rx_got_time_code <= 1'b0;`
336	25	redbear	`end`
337	5	redbear	`end`
338			`end`
339
340	25	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
341	5	redbear	`begin`
342	25	redbear	`if(!rx_resetn)`
343			`begin`
344	33	redbear	`rx_got_fct_fsm <= 1'b0;`
345	25	redbear	`rx_buffer_write <= 1'b0;`
346			`rx_data_take_0 <= 1'b0;`
347	33	redbear	`ready_control_p_r <= 1'b0;`
348			`ready_data_p_r <= 1'b0;`
349
350	25	redbear	`end`
351			`else`
352			`begin`
353			`rx_data_take_0 <= rx_data_take;`
354			`rx_buffer_write <= rx_data_take_0;`
355	5	redbear
356	33	redbear
357			`if(ready_control \|\| ready_control_p)`
358			`begin`
359			`if(is_control)`
360			`ready_control_p_r <= 1'b1;`
361	37	redbear	`else`
362			`ready_control_p_r <= 1'b0;`
363	33	redbear	`end`
364			`else`
365			`begin`
366			`ready_control_p_r <= 1'b0;`
367			`end`
368
369			`if(ready_data \|\| ready_data_p)`
370			`begin`
371			`if(!is_control)`
372			`ready_data_p_r <= 1'b1;`
373	37	redbear	`else`
374			`ready_data_p_r <= 1'b0;`
375	33	redbear	`end`
376			`else`
377			`begin`
378			`ready_data_p_r <= 1'b0;`
379			`end`
380
381			`if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)`
382	25	redbear	`rx_got_fct_fsm <= 1'b1;`
383			`else`
384			`rx_got_fct_fsm <= rx_got_fct_fsm;`
385			`end`
386			`end`
387
388			`always@(posedge ready_control or negedge rx_resetn )`
389			`begin`
390	14	redbear	`if(!rx_resetn)`
391	5	redbear	`begin`
392	25	redbear	`control_r <= 4'd0;`
393	37	redbear	`parity_rec_c <= 1'b0;`
394	25	redbear	`end`
395			`else`
396			`begin`
397	37	redbear	`control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`
398			`parity_rec_c <= bit_c_3;`
399	25	redbear	`end`
400			`end`
401	23	redbear
402	33	redbear	`always@(posedge ready_control_p or negedge rx_resetn )`
403			`begin`
404			`if(!rx_resetn)`
405			`begin`
406			`control_p_r <= 4'd0;`
407	37	redbear
408	33	redbear	`end`
409			`else`
410			`begin`
411	37	redbear	`control_p_r <= control_r;`
412	33	redbear	`end`
413			`end`
414	5	redbear
415	33	redbear
416
417	25	redbear	`always@(posedge ready_data or negedge rx_resetn )`
418			`begin`
419			`if(!rx_resetn)`
420			`begin`
421			`dta_timec <= 10'd0;`
422	37	redbear	`parity_rec_d <= 1'b0;`
423	25	redbear	`end`
424			`else`
425			`begin`
426	37	redbear	`dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
427			`parity_rec_d <= bit_d_9;`
428	25	redbear	`end`
429			`end`
430	5	redbear
431	33	redbear
432			`always@(posedge ready_data_p or negedge rx_resetn )`
433			`begin`
434			`if(!rx_resetn)`
435			`begin`
436			`dta_timec_p <= 10'd0;`
437			`end`
438			`else`
439			`begin`
440	37	redbear	`dta_timec_p <= dta_timec;`
441	33	redbear	`end`
442			`end`
443
444	37	redbear	`always@(*)`
445			`begin`
446
447			`rx_error_d = 1'b0;`
448
449			`if(last_is_control && ready_data_p)`
450			`begin`
451			`if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)`
452			`begin`
453			`rx_error_d = 1'b1;`
454			`end`
455			`end`
456			`else if(last_is_data && ready_data_p)`
457			`begin`
458			`if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)`
459			`begin`
460			`rx_error_d = 1'b1;`
461			`end`
462			`end`
463			`end`
464
465			`always@(*)`
466			`begin`
467
468			`rx_error_c = 1'b0;`
469
470			`if(last_is_control && ready_control_p)`
471			`begin`
472			`if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)`
473			`begin`
474			`rx_error_c = 1'b1;`
475			`end`
476			`end`
477			`else if(last_is_data && ready_control_p)`
478			`begin`
479			`if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)`
480			`begin`
481			`rx_error_c = 1'b1;`
482			`end`
483			`end`
484			`end`
485
486	33	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
487			`begin`
488
489			`if(!rx_resetn)`
490			`begin`
491			`is_control <= 1'b0;`
492			`control_bit_found <= 1'b0;`
493			`counter_neg[5:0] <= 6'd1;`
494			`end`
495			`else`
496			`begin`
497
498			`control_bit_found <= rx_din;`
499
500			`case(counter_neg)`

Browse

Tools

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Blame information for rev 37