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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [spw_ulight_con_top_x.v] - Blame information for rev 38

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1 34 redbear 
//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
33 33 redbear 
module spw_ulight_con_top_x(
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                                input ppll_100_MHZ,
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                                input ppllclk,
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                                input reset_spw_n_b,
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                                input top_sin,
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                                input top_din,
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                                input top_auto_start,
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                                input top_link_start,
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                                input top_link_disable,
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                                input top_tx_write,
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                                input [8:0] top_tx_data,
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                                input top_tx_tick,
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                                input [7:0] top_tx_time,
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                                input read_rx_fifo_en,
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                                output [8:0] datarx_flag,
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                                output tick_out,
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                                output [7:0] time_out,
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                                output top_dout,
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                                output top_sout,
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                                output f_full,
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                                output f_empty,
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                                output f_full_rx,
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                                output f_empty_rx,
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                                output top_tx_ready_tick,
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                                output [5:0]top_fsm,
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                                output [5:0]counter_fifo_tx,
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                                output [5:0]counter_fifo_rx
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                                //output [13:0] data_info
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                        );
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        wire [8:0] datarx_flag_axi;
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        wire [8:0] datarx_flag_w;
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        wire buffer_write_w;
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        wire [7:0] time_out_axi;
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        wire [13:0] monitor_x_axi;
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        wire [13:0] data_x;
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        wire rx_buffer_write_mon_x;
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        wire credit_error_rx_w,top_send_fct_now_w;
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        wire top_tx_write_w,top_tx_ready_w;
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        wire [8:0] top_tx_data_w;
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        wire tx_reset_n;
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92 37 redbear 
        assign tx_reset_n = (!reset_spw_n_b)?1'b0:1'b1;
93 33 redbear 
 
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        //assign time_out = time_out_w;
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        assign datarx_flag = datarx_flag_axi;
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        //assign data_info = data_x;
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        top_spw_ultra_light SPW(
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                                        .pclk(ppll_100_MHZ),
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                                        .ppllclk(ppllclk),
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                                        .resetn(reset_spw_n_b),
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                                        .top_sin(top_sin),
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                                        .top_din(top_din),
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                                        .top_auto_start(top_auto_start),
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                                        .top_link_start(top_link_start),
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                                        .top_link_disable(top_link_disable),
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                                        .top_tx_write(top_tx_write_w),
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                                        .top_tx_data(top_tx_data_w),
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                                        .top_tx_tick(top_tx_tick),
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                                        .top_tx_time(top_tx_time),
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                                        .credit_error_rx(credit_error_rx_w),
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                                        .top_send_fct_now(top_send_fct_now_w),
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                                        .datarx_flag(datarx_flag_w),
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                                        .buffer_write(buffer_write_w),
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                                        .time_out(time_out),
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                                        .tick_out(tick_out),
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                                        .top_dout(top_dout),
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                                        .top_sout(top_sout),
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                                        .top_tx_ready(top_tx_ready_w),
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                                        .top_tx_ready_tick(top_tx_ready_tick),
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                                        .top_fsm(top_fsm)
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                                );
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                        fifo_rx  rx_data(
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                                         .clock(ppll_100_MHZ),
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                                         .reset(tx_reset_n),
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                                         .wr_en(buffer_write_w),
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                                         .rd_en(read_rx_fifo_en),
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                                         .data_in(datarx_flag_w),
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                                         .f_full(f_full_rx),
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                                         .f_empty(f_empty_rx),
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                                         .open_slot_fct(top_send_fct_now_w),
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                                         .overflow_credit_error(credit_error_rx_w),
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                                         .data_out(datarx_flag_axi),
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                                         .counter(counter_fifo_rx)
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                                         );
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                        fifo_tx tx_data(
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                                         .clock(ppll_100_MHZ),
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                                         .reset(tx_reset_n),
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                                         .wr_en(top_tx_write),
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                                         .rd_en(top_tx_ready_w),
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                                         .data_in(top_tx_data),
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                                         .f_full(f_full),
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                                         .f_empty(f_empty),
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                                         .write_tx(top_tx_write_w),
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                                         .data_out(top_tx_data_w),
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                                         .counter(counter_fifo_tx)
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                                         );
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endmodule

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