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[/] [spacewiresystemc/] [trunk/] [testbench/] [module_tb.v] - Blame information for rev 40

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`timescale 1ns/1ns
`default_nettype none
 
module module_tb;
 
        reg CLK_SIM;
        reg CLK_SYS_RX;
 
        `ifdef VERILOG_A
 
                /*SPWTCR*/
                wire CLOCK;
                reg CLK;
                wire RESETn;
                wire LINK_START;
                wire LINK_DISABLE;
                wire AUTOSTART;
                wire [2:0] CURRENTSTATE;
                wire [10:0] FLAGS;
                wire [8:0] DATA_I;
                wire WR_DATA;
                wire TX_FULL;
                wire [8:0] DATA_O;
                wire RD_DATA;
                wire RX_EMPTY;
                wire TICK_OUT;
                wire [7:0] TIME_OUT;
                wire TICK_IN;
                wire [7:0] TIME_IN;
                wire [6:0] TX_CLK_DIV;
                wire SPILL_ENABLE;
                wire Din;
                wire Sin;
                wire Dout;
                wire Sout;
 
                wire [3:0] SPW_SC_FSM;
                wire [3:0] SPW_SC_FSM_OUT;
                wire RX_CLOCK_RECOVERY_SC;
                wire TX_CLOCK_RECOVERY_VLOG;
                wire TX_CLOCK_OUT;
                wire TX_CLOCK_OUT_SC;
 
                integer i;
                integer time_clk_ns;
 
                assign SPILL_ENABLE = 1'b1;
 
                initial
                 begin
                        $dumpfile("module_tb.vcd");
                        $dumpvars(0,module_tb);
                        $global_init;
                        i=0;
                        time_clk_ns = 500;
                 end
 
                assign RX_CLOCK_RECOVERY_SC = Din ^ Sin;
                assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT;
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
 
                assign TX_CLOCK_RECOVERY_VLOG = Dout ^ Sout;
 
                assign CLOCK = CLK;
 
                initial CLK = 1'b0;
                always #(10) CLK = ~CLK;
 
                SPW_TOP DUT_TCR (
                                .CLOCK(CLOCK),
                                .RESETn(RESETn),
                                .LINK_START(LINK_START),
                                .LINK_DISABLE(LINK_DISABLE),
                                .AUTOSTART(AUTOSTART),
                                .CURRENTSTATE(CURRENTSTATE),
                                .FLAGS(FLAGS),
                                .DATA_I(DATA_I),
                                .WR_DATA(WR_DATA),
                                .TX_FULL(TX_FULL),
                                .DATA_O(DATA_O),
                                .RD_DATA(RD_DATA),
                                .RX_EMPTY(RX_EMPTY),
                                .TICK_OUT(TICK_OUT),
                                .TIME_OUT(TIME_OUT),
                                .TICK_IN(TICK_IN),
                                .TIME_IN(TIME_IN),
                                .TX_CLK_DIV(TX_CLK_DIV),
                                .SPILL_ENABLE(SPILL_ENABLE),
                                .Din(Din),
                                .Sin(Sin),
                                .Dout(Dout),
                                .Sout(Sout)
                        );
 
                        always@(posedge CLK)
                                $global_reset;
 
                        always@(posedge CLK)
                                $write_tx_spw;
 
                        always@(posedge CLK)
                                $receive_rx_spw;
                        //
                        always@(posedge CLK)
                                $run_sim;
 
                        //FLAG USED TO FINISH SIMULATION PROGRAM 
                        always@(posedge CLK)
                        begin
                                wait(i == 1);
                                $finish();
                        end
        `endif
 
        `ifdef VERILOG_B
                assign TOP_SIN = TOP_SOUT;
                assign TOP_DIN = TOP_DOUT;
 
 
                integer time_clk_ns;
 
                reg PCLK;
                reg PCLK_FIFO;
                reg PPLLCLK;
 
                wire RESETN;
 
                wire TOP_SIN;
                wire TOP_DIN;
 
                wire AUTO_START;
                wire LINK_START;
                wire LINK_DISABLE;
 
                wire TOP_TX_WRITE;
                wire [8:0] TOP_TX_DATA;
 
                wire TOP_TX_TICK;
                wire [7:0] TOP_TX_TIME;
 
                wire CREDIT_ERROR_RX;
                wire TOP_SEND_FCT_NOW;
 
                wire [8:0] DATARX_FLAG;
                wire BUFFER_READ;
 
                wire [7:0] TIME_OUT;
                wire TICK_OUT;
 
                wire TOP_DOUT;
                wire TOP_SOUT;
 
                wire TOP_TX_READY;
                wire TOP_TX_READY_TICK;
 
                wire [5:0] TOP_FSM;
                wire [5:0] COUNTER_FIFO_RX;
                wire [5:0] COUNTER_FIFO_TX;
 
                wire TX_CLOCK_RECOVERY_VLOG;
                wire [3:0] SPW_SC_FSM;
                wire [3:0] SPW_SC_FSM_OUT;
 
                wire [31:0] counter;
                wire [3:0] global_counter_actual;
                wire [13:0] data_took_is;
                wire din_out;
                wire sin_out;
 
                wire F_FULL,F_EMPTY,F_FULL_RX,F_EMPTY_RX;
 
                assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
 
                integer i;
 
                initial
                begin
                        $dumpfile("module_tb.vcd");
                        $dumpvars(0,module_tb);
                        $global_init;
                        i=0;
                        time_clk_ns = 500;
                 end
 
                initial PCLK = 1'b0;
                always #(5) PCLK = ~PCLK;
 
                initial PCLK_FIFO = 1'b0;
                always #(10) PCLK_FIFO = ~PCLK_FIFO;
 
                initial PPLLCLK = 1'b0;
                always #(time_clk_ns/2) PPLLCLK = ~PPLLCLK;
 
                initial CLK_SIM = 1'b0;
                always #(1) CLK_SIM = ~CLK_SIM;
 
                initial CLK_SYS_RX = 1'b0;
                always #(4) CLK_SYS_RX = ~CLK_SYS_RX;
 
                spw_ulight_con_top_x DUT_ULIGHT(
                                        .ppll_100_MHZ(PCLK),
                                        .ppllclk(PPLLCLK),
                                        .reset_spw_n_b(RESETN),
 
                                        .top_sin(TOP_SIN),
                                        .top_din(TOP_DIN),
 
                                        .top_auto_start(AUTO_START),
                                        .top_link_start(LINK_START),
                                        .top_link_disable(LINK_DISABLE),
 
                                        .top_tx_write(TOP_TX_WRITE),
                                        .top_tx_data(TOP_TX_DATA),
 
                                        .top_tx_tick(TOP_TX_TICK),
                                        .top_tx_time(TOP_TX_TIME),
 
                                        .datarx_flag(DATARX_FLAG),
                                        .read_rx_fifo_en(BUFFER_READ),
 
                                        .time_out(TIME_OUT),
                                        .tick_out(TICK_OUT),
 
                                        .top_dout(TOP_DOUT),
                                        .top_sout(TOP_SOUT),
 
                                        .f_full(F_FULL),
                                        .f_empty(F_EMPTY),
                                        .f_full_rx(F_FULL_RX),
                                        .f_empty_rx(F_EMPTY_RX),
                                        .top_tx_ready_tick(TOP_TX_READY_TICK),
 
                                        .top_fsm(TOP_FSM),
                                        .counter_fifo_tx(COUNTER_FIFO_TX),
                                        .counter_fifo_rx(COUNTER_FIFO_RX)
                                      );
 
 
 
        //
        always@(posedge PCLK_FIFO)
                $write_tx_fsm_spw_ultra_light;
        //
        always@(posedge PCLK_FIFO)
                $write_tx_data_spw_ultra_light;
 
        always@(posedge PCLK_FIFO)
                $write_tx_time_code_spw_ultra_light;
        //
        always@(posedge PCLK_FIFO)
                $receive_rx_data_spw_ultra_light;
 
        always@(posedge TICK_OUT)
                $receive_rx_time_code_spw_ultra_light;
 
        //
        always@(posedge PCLK , negedge PCLK)
                $global_reset;
 
        //
        always@(posedge CLK_SIM)
                $run_sim;
 
        //FLAG USED TO FINISH SIMULATION PROGRAM 
        always@(posedge CLK_SIM)
        begin
                wait(i == 1);
                $finish();
        end
 
        `endif
 
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`timescale 1ns/1ns
2			`default_nettype none
3
4			`module module_tb;`
5
6			`reg CLK_SIM;`
7	40	redbear	`reg CLK_SYS_RX;`
8	5	redbear
9			`ifdef VERILOG_A
10
11			`/SPWTCR/`
12			`wire CLOCK;`
13			`reg CLK;`
14			`wire RESETn;`
15			`wire LINK_START;`
16			`wire LINK_DISABLE;`
17			`wire AUTOSTART;`
18			`wire [2:0] CURRENTSTATE;`
19			`wire [10:0] FLAGS;`
20			`wire [8:0] DATA_I;`
21			`wire WR_DATA;`
22			`wire TX_FULL;`
23			`wire [8:0] DATA_O;`
24			`wire RD_DATA;`
25			`wire RX_EMPTY;`
26			`wire TICK_OUT;`
27			`wire [7:0] TIME_OUT;`
28			`wire TICK_IN;`
29			`wire [7:0] TIME_IN;`
30			`wire [6:0] TX_CLK_DIV;`
31			`wire SPILL_ENABLE;`
32			`wire Din;`
33			`wire Sin;`
34			`wire Dout;`
35			`wire Sout;`
36
37			`wire [3:0] SPW_SC_FSM;`
38			`wire [3:0] SPW_SC_FSM_OUT;`
39			`wire RX_CLOCK_RECOVERY_SC;`
40			`wire TX_CLOCK_RECOVERY_VLOG;`
41			`wire TX_CLOCK_OUT;`
42			`wire TX_CLOCK_OUT_SC;`
43
44	40	redbear	`integer i;`
45			`integer time_clk_ns;`
46
47			`assign SPILL_ENABLE = 1'b1;`
48
49			`initial`
50			`begin`
51			`$dumpfile("module_tb.vcd");`
52			`$dumpvars(0,module_tb);`
53			`$global_init;`
54			`i=0;`
55			`time_clk_ns = 500;`
56			`end`
57
58	5	redbear	`assign RX_CLOCK_RECOVERY_SC = Din ^ Sin;`
59			`assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT;`
60			`assign SPW_SC_FSM_OUT = SPW_SC_FSM;`
61
62			`assign TX_CLOCK_RECOVERY_VLOG = Dout ^ Sout;`
63
64			`assign CLOCK = CLK;`
65
66			`initial CLK = 1'b0;`
67			`always #(10) CLK = ~CLK;`
68
69	40	redbear	`SPW_TOP DUT_TCR (`
70	5	redbear	`.CLOCK(CLOCK),`
71			`.RESETn(RESETn),`
72			`.LINK_START(LINK_START),`
73			`.LINK_DISABLE(LINK_DISABLE),`
74			`.AUTOSTART(AUTOSTART),`
75			`.CURRENTSTATE(CURRENTSTATE),`
76			`.FLAGS(FLAGS),`
77			`.DATA_I(DATA_I),`
78			`.WR_DATA(WR_DATA),`
79			`.TX_FULL(TX_FULL),`
80			`.DATA_O(DATA_O),`
81			`.RD_DATA(RD_DATA),`
82			`.RX_EMPTY(RX_EMPTY),`
83			`.TICK_OUT(TICK_OUT),`
84			`.TIME_OUT(TIME_OUT),`
85			`.TICK_IN(TICK_IN),`
86			`.TIME_IN(TIME_IN),`
87			`.TX_CLK_DIV(TX_CLK_DIV),`
88			`.SPILL_ENABLE(SPILL_ENABLE),`
89			`.Din(Din),`
90			`.Sin(Sin),`
91			`.Dout(Dout),`
92			`.Sout(Sout)`
93			`);`
94
95	40	redbear	`always@(posedge CLK)`
96	5	redbear	`$global_reset;`
97
98			`always@(posedge CLK)`
99			`$write_tx_spw;`
100
101			`always@(posedge CLK)`
102			`$receive_rx_spw;`
103	40	redbear	`//`
104			`always@(posedge CLK)`
105			`$run_sim;`
106	5	redbear
107			`//FLAG USED TO FINISH SIMULATION PROGRAM`
108			`always@(posedge CLK)`
109			`begin`
110			`wait(i == 1);`
111			`$finish();`
112			`end`
113			`endif
114
115			`ifdef VERILOG_B
116	40	redbear	`assign TOP_SIN = TOP_SOUT;`
117			`assign TOP_DIN = TOP_DOUT;`
118
119	5	redbear
120			`integer time_clk_ns;`
121
122			`reg PCLK;`
123	40	redbear	`reg PCLK_FIFO;`
124	5	redbear	`reg PPLLCLK;`
125
126			`wire RESETN;`
127
128			`wire TOP_SIN;`
129			`wire TOP_DIN;`
130
131			`wire AUTO_START;`
132			`wire LINK_START;`
133			`wire LINK_DISABLE;`
134
135			`wire TOP_TX_WRITE;`
136			`wire [8:0] TOP_TX_DATA;`
137
138			`wire TOP_TX_TICK;`
139			`wire [7:0] TOP_TX_TIME;`
140
141			`wire CREDIT_ERROR_RX;`
142			`wire TOP_SEND_FCT_NOW;`
143
144			`wire [8:0] DATARX_FLAG;`
145	40	redbear	`wire BUFFER_READ;`
146	5	redbear
147			`wire [7:0] TIME_OUT;`
148			`wire TICK_OUT;`
149
150			`wire TOP_DOUT;`
151			`wire TOP_SOUT;`
152
153			`wire TOP_TX_READY;`
154			`wire TOP_TX_READY_TICK;`
155
156			`wire [5:0] TOP_FSM;`
157	40	redbear	`wire [5:0] COUNTER_FIFO_RX;`
158			`wire [5:0] COUNTER_FIFO_TX;`
159	5	redbear
160	7	redbear	`wire TX_CLOCK_RECOVERY_VLOG;`
161			`wire [3:0] SPW_SC_FSM;`
162			`wire [3:0] SPW_SC_FSM_OUT;`
163
164	40	redbear	`wire [31:0] counter;`
165			`wire [3:0] global_counter_actual;`
166			`wire [13:0] data_took_is;`
167			`wire din_out;`
168			`wire sin_out;`
169
170			`wire F_FULL,F_EMPTY,F_FULL_RX,F_EMPTY_RX;`
171
172	7	redbear	`assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;`
173			`assign SPW_SC_FSM_OUT = SPW_SC_FSM;`
174
175	5	redbear	`integer i;`
176
177			`initial`
178	40	redbear	`begin`
179	5	redbear	`$dumpfile("module_tb.vcd");`
180			`$dumpvars(0,module_tb);`
181			`$global_init;`
182			`i=0;`
183	12	redbear	`time_clk_ns = 500;`
184	5	redbear	`end`
185
186			`initial PCLK = 1'b0;`
187			`always #(5) PCLK = ~PCLK;`
188
189	40	redbear	`initial PCLK_FIFO = 1'b0;`
190			`always #(10) PCLK_FIFO = ~PCLK_FIFO;`
191
192	5	redbear	`initial PPLLCLK = 1'b0;`
193	12	redbear	`always #(time_clk_ns/2) PPLLCLK = ~PPLLCLK;`
194	5	redbear
195			`initial CLK_SIM = 1'b0;`
196			`always #(1) CLK_SIM = ~CLK_SIM;`
197
198	40	redbear	`initial CLK_SYS_RX = 1'b0;`
199			`always #(4) CLK_SYS_RX = ~CLK_SYS_RX;`
200	5	redbear
201	40	redbear	`spw_ulight_con_top_x DUT_ULIGHT(`
202			`.ppll_100_MHZ(PCLK),`
203	5	redbear	`.ppllclk(PPLLCLK),`
204	40	redbear	`.reset_spw_n_b(RESETN),`
205	5	redbear
206			`.top_sin(TOP_SIN),`
207			`.top_din(TOP_DIN),`
208
209			`.top_auto_start(AUTO_START),`
210			`.top_link_start(LINK_START),`
211			`.top_link_disable(LINK_DISABLE),`
212
213			`.top_tx_write(TOP_TX_WRITE),`
214			`.top_tx_data(TOP_TX_DATA),`
215
216			`.top_tx_tick(TOP_TX_TICK),`
217			`.top_tx_time(TOP_TX_TIME),`
218
219			`.datarx_flag(DATARX_FLAG),`
220	40	redbear	`.read_rx_fifo_en(BUFFER_READ),`
221	5	redbear
222			`.time_out(TIME_OUT),`
223			`.tick_out(TICK_OUT),`
224
225			`.top_dout(TOP_DOUT),`
226			`.top_sout(TOP_SOUT),`
227
228	40	redbear	`.f_full(F_FULL),`
229			`.f_empty(F_EMPTY),`
230			`.f_full_rx(F_FULL_RX),`
231			`.f_empty_rx(F_EMPTY_RX),`
232	5	redbear	`.top_tx_ready_tick(TOP_TX_READY_TICK),`
233
234	40	redbear	`.top_fsm(TOP_FSM),`
235			`.counter_fifo_tx(COUNTER_FIFO_TX),`
236			`.counter_fifo_rx(COUNTER_FIFO_RX)`
237	5	redbear	`);`
238
239	40	redbear
240
241	7	redbear	`//`
242	40	redbear	`always@(posedge PCLK_FIFO)`
243	7	redbear	`$write_tx_fsm_spw_ultra_light;`
244			`//`
245	40	redbear	`always@(posedge PCLK_FIFO)`
246	7	redbear	`$write_tx_data_spw_ultra_light;`
247	5	redbear
248	40	redbear	`always@(posedge PCLK_FIFO)`
249	7	redbear	`$write_tx_time_code_spw_ultra_light;`
250			`//`
251	40	redbear	`always@(posedge PCLK_FIFO)`
252	7	redbear	`$receive_rx_data_spw_ultra_light;`
253	5	redbear
254	7	redbear	`always@(posedge TICK_OUT)`
255			`$receive_rx_time_code_spw_ultra_light;`
256	5	redbear
257	7	redbear	`//`
258			`always@(posedge PCLK , negedge PCLK)`
259			`$global_reset;`
260
261			`//`
262			`always@(posedge CLK_SIM)`
263			`$run_sim;`
264	5	redbear
265			`//FLAG USED TO FINISH SIMULATION PROGRAM`
266			`always@(posedge CLK_SIM)`
267			`begin`
268			`wait(i == 1);`
269			`$finish();`
270			`end`
271
272	40	redbear	`endif
273	5	redbear
274	40	redbear
275	5	redbear	`endmodule`

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[/] [spacewiresystemc/] [trunk/] [testbench/] [module_tb.v] - Blame information for rev 40