OpenCores
URL https://opencores.org/ocsvn/sparc64soc/sparc64soc/trunk

Subversion Repositories sparc64soc

[/] [sparc64soc/] [trunk/] [NOR-flash/] [WBFLASH.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dmitryr 
`timescale 1ns / 1ps
2 
//////////////////////////////////////////////////////////////////////////////////
3 
// Company:  (C) Athree, 2009
4 
// Engineer: Dmitry Rozhdestvenskiy
5 
// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru
6 
//
7 
// Design Name:    Wishbone NOR flash controller
8 
// Module Name:    wbflash
9 
// Project Name:   SPARC SoC single-core
10 
//
11 
// LICENSE:
12 
// This is a Free Hardware Design; you can redistribute it and/or
13 
// modify it under the terms of the GNU General Public License
14 
// version 2 as published by the Free Software Foundation.
15 
// The above named program is distributed in the hope that it will
16 
// be useful, but WITHOUT ANY WARRANTY; without even the implied
17 
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
18 
// See the GNU General Public License for more details.
19 
//
20 
//////////////////////////////////////////////////////////////////////////////////
21 
module WBFLASH(
22 
    input             wb_clk_i,
23 
    input             wb_rst_i,
24 
 
25 
    input      [63:0] wb_dat_i,
26 
    output     [63:0] wb_dat_o,
27 
    input      [63:0] wb_adr_i,
28 
    input      [ 7:0] wb_sel_i,
29 
    input             wb_we_i,
30 
    input             wb_cyc_i,
31 
    input             wb_stb_i,
32 
    output reg        wb_ack_o,
33 
    output            wb_err_o,
34 
    output            wb_rty_o,
35 
    input             wb_cab_i,
36 
 
37 
    input      [63:0] wb1_dat_i,
38 
    output     [63:0] wb1_dat_o,
39 
    input      [63:0] wb1_adr_i,
40 
    input      [ 7:0] wb1_sel_i,
41 
    input             wb1_we_i,
42 
    input             wb1_cyc_i,
43 
    input             wb1_stb_i,
44 
    output reg        wb1_ack_o,
45 
    output            wb1_err_o,
46 
    output            wb1_rty_o,
47 
    input             wb1_cab_i,
48 
 
49 
    output reg [24:0] flash_addr,
50 
    input      [15:0] flash_data,
51 
    output            flash_oen,
52 
    output            flash_wen,
53 
    output            flash_cen,
54 
    input      [ 1:0] flash_rev
55 
     //output            flash_ldn
56 
);
57 
 
58 
assign wb_err_o=0;
59 
assign wb_rty_o=0;
60 
 
61 
reg  [1:0] wordcnt;
62 
reg  [2:0] cyclecnt;
63 
reg [63:0] wb_dat;
64 
reg [63:0] wb1_dat;
65 
reg [63:0] wb_dat_inv;
66 
reg [63:0] cache_addr;
67 
reg [63:0] cache_addr1;
68 
 
69 
always @(posedge wb_clk_i or posedge wb_rst_i)
70 
   if(wb_rst_i)
71 
      begin
72 
         cache_addr<=64'b0;
73 
         cache_addr1<=64'b0;
74 
      end
75 
   else
76 
      if((!wb_cyc_i || !wb_stb_i) && (!wb1_cyc_i || !wb1_stb_i))
77 
         begin
78 
            wordcnt<=2'b00;
79 
            cyclecnt<=3'b000;
80 
            wb_ack_o<=0;
81 
            wb1_ack_o<=0;
82 
         end
83 
      else
84 
         if(wb_stb_i)
85 
            if(wb_adr_i==cache_addr)
86 
               wb_ack_o<=1;
87 
            else
88 
               if(cyclecnt!=3'b111)
89 
                  cyclecnt<=cyclecnt+1;
90 
               else
91 
                  begin
92 
                     cyclecnt<=0;
93 
                     case(wordcnt)
94 
                        2'b00:wb_dat[63:48]<={flash_data[7:0],flash_data[15:8]};
95 
                        2'b01:wb_dat[47:32]<={flash_data[7:0],flash_data[15:8]};
96 
                        2'b10:wb_dat[31:16]<={flash_data[7:0],flash_data[15:8]};
97 
                        2'b11:wb_dat[15: 0]<={flash_data[7:0],flash_data[15:8]};
98 
                     endcase
99 
                     if(wordcnt!=2'b11)
100 
                        wordcnt<=wordcnt+1;
101 
                     else
102 
                        begin
103 
                           wb_ack_o<=1;
104 
                           cache_addr<=wb_adr_i;
105 
                        end
106 
                  end
107 
         else
108 
            if(wb1_adr_i==cache_addr1)
109 
               wb1_ack_o<=1;
110 
            else
111 
               if(cyclecnt!=3'b111)
112 
                  cyclecnt<=cyclecnt+1;
113 
               else
114 
                   begin
115 
                      cyclecnt<=0;
116 
                      case(wordcnt)
117 
                         2'b00:wb1_dat[63:48]<={flash_data[7:0],flash_data[15:8]};
118 
                         2'b01:wb1_dat[47:32]<={flash_data[7:0],flash_data[15:8]};
119 
                         2'b10:wb1_dat[31:16]<={flash_data[7:0],flash_data[15:8]};
120 
                         2'b11:wb1_dat[15: 0]<={flash_data[7:0],flash_data[15:8]};
121 
                      endcase
122 
                      if(wordcnt!=2'b11)
123 
                         wordcnt<=wordcnt+1;
124 
                      else
125 
                         begin
126 
                            wb1_ack_o<=1;
127 
                            cache_addr1<=wb1_adr_i;
128 
                         end
129 
                   end
130 
 
131 
assign wb_dat_o=wb_dat;
132 
assign wb1_dat_o=wb1_dat;
133 
 
134 
wire [1:0] flash_rev_d;
135 
 
136 
assign flash_rev_d=wb_rst_i ? flash_rev:flash_rev_d;
137 
 
138 
always @( * )
139 
   case({wb1_stb_i,flash_rev_d})
140 
      3'b000:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0000000;
141 
      3'b001:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0100000;
142 
      3'b010:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0200000;
143 
      3'b011:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0300000;
144 
      3'b100:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
145 
      3'b101:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
146 
      3'b110:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
147 
      3'b111:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
148 
   endcase
149 
 
150 
assign flash_oen=((wb_cyc_i && wb_stb_i) || (wb1_cyc_i && wb1_stb_i) ? 0:1);
151 
assign flash_wen=1;
152 
assign flash_cen=0;
153 
 
154 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.