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[/] [sparc64soc/] [trunk/] [NOR-flash/] [WBFLASH.v] - Blame information for rev 7

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Line No. Rev Author Line
1 2 dmitryr 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:  (C) Athree, 2009
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// Engineer: Dmitry Rozhdestvenskiy
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// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru
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//
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// Design Name:    Wishbone NOR flash controller
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// Module Name:    wbflash
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// Project Name:   SPARC SoC single-core
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//
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// LICENSE:
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// This is a Free Hardware Design; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License
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// version 2 as published by the Free Software Foundation.
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// The above named program is distributed in the hope that it will
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// be useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the GNU General Public License for more details.
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//
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//////////////////////////////////////////////////////////////////////////////////
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module WBFLASH(
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    input             wb_clk_i,
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    input             wb_rst_i,
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    input      [63:0] wb_dat_i,
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    output     [63:0] wb_dat_o,
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    input      [63:0] wb_adr_i,
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    input      [ 7:0] wb_sel_i,
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    input             wb_we_i,
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    input             wb_cyc_i,
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    input             wb_stb_i,
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    output reg        wb_ack_o,
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    output            wb_err_o,
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    output            wb_rty_o,
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    input             wb_cab_i,
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    input      [63:0] wb1_dat_i,
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    output     [63:0] wb1_dat_o,
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    input      [63:0] wb1_adr_i,
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    input      [ 7:0] wb1_sel_i,
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    input             wb1_we_i,
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    input             wb1_cyc_i,
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    input             wb1_stb_i,
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    output reg        wb1_ack_o,
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    output            wb1_err_o,
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    output            wb1_rty_o,
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    input             wb1_cab_i,
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    output reg [24:0] flash_addr,
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    input      [15:0] flash_data,
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    output            flash_oen,
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    output            flash_wen,
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    output            flash_cen,
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    input      [ 1:0] flash_rev
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     //output            flash_ldn
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);
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assign wb_err_o=0;
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assign wb_rty_o=0;
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reg  [1:0] wordcnt;
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reg  [2:0] cyclecnt;
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reg [63:0] wb_dat;
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reg [63:0] wb1_dat;
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reg [63:0] wb_dat_inv;
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reg [63:0] cache_addr;
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reg [63:0] cache_addr1;
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always @(posedge wb_clk_i or posedge wb_rst_i)
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   if(wb_rst_i)
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      begin
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         cache_addr<=64'b0;
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         cache_addr1<=64'b0;
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      end
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   else
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      if((!wb_cyc_i || !wb_stb_i) && (!wb1_cyc_i || !wb1_stb_i))
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         begin
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            wordcnt<=2'b00;
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            cyclecnt<=3'b000;
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            wb_ack_o<=0;
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            wb1_ack_o<=0;
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         end
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      else
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         if(wb_stb_i)
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            if(wb_adr_i==cache_addr)
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               wb_ack_o<=1;
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            else
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               if(cyclecnt!=3'b111)
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                  cyclecnt<=cyclecnt+1;
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               else
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                  begin
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                     cyclecnt<=0;
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                     case(wordcnt)
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                        2'b00:wb_dat[63:48]<={flash_data[7:0],flash_data[15:8]};
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                        2'b01:wb_dat[47:32]<={flash_data[7:0],flash_data[15:8]};
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                        2'b10:wb_dat[31:16]<={flash_data[7:0],flash_data[15:8]};
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                        2'b11:wb_dat[15: 0]<={flash_data[7:0],flash_data[15:8]};
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                     endcase
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                     if(wordcnt!=2'b11)
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                        wordcnt<=wordcnt+1;
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                     else
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                        begin
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                           wb_ack_o<=1;
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                           cache_addr<=wb_adr_i;
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                        end
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                  end
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         else
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            if(wb1_adr_i==cache_addr1)
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               wb1_ack_o<=1;
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            else
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               if(cyclecnt!=3'b111)
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                  cyclecnt<=cyclecnt+1;
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               else
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                   begin
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                      cyclecnt<=0;
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                      case(wordcnt)
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                         2'b00:wb1_dat[63:48]<={flash_data[7:0],flash_data[15:8]};
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                         2'b01:wb1_dat[47:32]<={flash_data[7:0],flash_data[15:8]};
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                         2'b10:wb1_dat[31:16]<={flash_data[7:0],flash_data[15:8]};
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                         2'b11:wb1_dat[15: 0]<={flash_data[7:0],flash_data[15:8]};
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                      endcase
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                      if(wordcnt!=2'b11)
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                         wordcnt<=wordcnt+1;
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                      else
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                         begin
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                            wb1_ack_o<=1;
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                            cache_addr1<=wb1_adr_i;
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                         end
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                   end
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assign wb_dat_o=wb_dat;
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assign wb1_dat_o=wb1_dat;
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wire [1:0] flash_rev_d;
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assign flash_rev_d=wb_rst_i ? flash_rev:flash_rev_d;
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always @( * )
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   case({wb1_stb_i,flash_rev_d})
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      3'b000:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0000000;
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      3'b001:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0100000;
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      3'b010:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0200000;
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      3'b011:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0300000;
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      3'b100:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
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      3'b101:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
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      3'b110:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
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      3'b111:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
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   endcase
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assign flash_oen=((wb_cyc_i && wb_stb_i) || (wb1_cyc_i && wb1_stb_i) ? 0:1);
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assign flash_wen=1;
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assign flash_cen=0;
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endmodule

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