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[/] [sparc64soc/] [trunk/] [OC-Ethernet/] [eth_macstatus.v] - Blame information for rev 5

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1 2 dmitryr
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_macstatus.v                                             ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/ethmac/                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is available in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.16  2005/02/21 10:42:11  igorm
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// Defer indication fixed.
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//
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// Revision 1.15  2003/01/30 13:28:19  tadejm
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// Defer indication changed.
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//
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// Revision 1.14  2002/11/22 01:57:06  mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.13  2002/11/13 22:30:58  tadejm
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// Late collision is reported only when not in the full duplex.
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// Sample is taken (for status) as soon as MRxDV is not valid (regardless
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// of the received byte cnt).
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//
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// Revision 1.12  2002/09/12 14:50:16  mohor
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// CarrierSenseLost bug fixed when operating in full duplex mode.
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//
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// Revision 1.11  2002/09/04 18:38:03  mohor
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// CarrierSenseLost status is not set when working in loopback mode.
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//
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// Revision 1.10  2002/07/25 18:17:46  mohor
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// InvalidSymbol generation changed.
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//
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// Revision 1.9  2002/04/22 13:51:44  mohor
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// Short frame and ReceivedLengthOK were not detected correctly.
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//
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// Revision 1.8  2002/02/18 10:40:17  mohor
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// Small fixes.
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//
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// Revision 1.7  2002/02/15 17:07:39  mohor
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// Status was not written correctly when frames were discarted because of
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// address mismatch.
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//
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// Revision 1.6  2002/02/11 09:18:21  mohor
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// Tx status is written back to the BD.
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//
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// Revision 1.5  2002/02/08 16:21:54  mohor
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// Rx status is written back to the BD.
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//
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// Revision 1.4  2002/01/23 10:28:16  mohor
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// Link in the header changed.
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//
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// Revision 1.3  2001/10/19 08:43:51  mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.2  2001/09/11 14:17:00  mohor
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// Few little NCSIM warnings fixed.
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//
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// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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//
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//
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//
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//
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`include "timescale.v"
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114
 
115
module eth_macstatus(
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                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
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                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
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                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
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                      InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
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                      r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
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                      LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
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                      RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
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                      StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
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                      r_FullD
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                    );
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127
 
128
 
129
parameter Tp = 1;
130
 
131
 
132
input         MRxClk;
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input         Reset;
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input         RxCrcError;
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input         MRxErr;
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input         MRxDV;
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138
input         RxStateSFD;
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input   [1:0] RxStateData;
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input         RxStatePreamble;
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input         RxStateIdle;
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input         Transmitting;
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input  [15:0] RxByteCnt;
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input         RxByteCntEq0;
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input         RxByteCntGreat2;
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input         RxByteCntMaxFrame;
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input   [3:0] MRxD;
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input         Collision;
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input   [5:0] CollValid;
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input         r_RecSmall;
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input  [15:0] r_MinFL;
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input  [15:0] r_MaxFL;
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input         r_HugEn;
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input         StartTxDone;
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input         StartTxAbort;
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input   [3:0] RetryCnt;
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input         MTxClk;
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input         MaxCollisionOccured;
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input         LateCollision;
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input         DeferIndication;
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input         TxStartFrm;
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input         StatePreamble;
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input   [1:0] StateData;
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input         CarrierSense;
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input         TxUsedData;
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input         Loopback;
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input         r_FullD;
168
 
169
 
170
output        ReceivedLengthOK;
171
output        ReceiveEnd;
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output        ReceivedPacketGood;
173
output        InvalidSymbol;
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output        LatchedCrcError;
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output        RxLateCollision;
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output        ShortFrame;
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output        DribbleNibble;
178
output        ReceivedPacketTooBig;
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output        LoadRxStatus;
180
output  [3:0] RetryCntLatched;
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output        RetryLimit;
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output        LateCollLatched;
183
output        DeferLatched;
184
input         RstDeferLatched;
185
output        CarrierSenseLost;
186
output        LatchedMRxErr;
187
 
188
 
189
reg           ReceiveEnd;
190
 
191
reg           LatchedCrcError;
192
reg           LatchedMRxErr;
193
reg           LoadRxStatus;
194
reg           InvalidSymbol;
195
reg     [3:0] RetryCntLatched;
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reg           RetryLimit;
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reg           LateCollLatched;
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reg           DeferLatched;
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reg           CarrierSenseLost;
200
 
201
wire          TakeSample;
202
wire          SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps 
203
 
204
// Crc error
205
always @ (posedge MRxClk or posedge Reset)
206
begin
207
  if(Reset)
208
    LatchedCrcError <=#Tp 1'b0;
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  else
210
  if(RxStateSFD)
211
    LatchedCrcError <=#Tp 1'b0;
212
  else
213
  if(RxStateData[0])
214
    LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
215
end
216
 
217
 
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// LatchedMRxErr
219
always @ (posedge MRxClk or posedge Reset)
220
begin
221
  if(Reset)
222
    LatchedMRxErr <=#Tp 1'b0;
223
  else
224
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
225
    LatchedMRxErr <=#Tp 1'b1;
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  else
227
    LatchedMRxErr <=#Tp 1'b0;
228
end
229
 
230
 
231
// ReceivedPacketGood
232
assign ReceivedPacketGood = ~LatchedCrcError;
233
 
234
 
235
// ReceivedLengthOK
236
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
237
 
238
 
239
 
240
 
241
 
242
// Time to take a sample
243
//assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
244
assign TakeSample = (|RxStateData)   & (~MRxDV)                    |
245
                      RxStateData[0] &   MRxDV & RxByteCntMaxFrame;
246
 
247
 
248
// LoadRxStatus
249
always @ (posedge MRxClk or posedge Reset)
250
begin
251
  if(Reset)
252
    LoadRxStatus <=#Tp 1'b0;
253
  else
254
    LoadRxStatus <=#Tp TakeSample;
255
end
256
 
257
 
258
 
259
// ReceiveEnd
260
always @ (posedge MRxClk or posedge Reset)
261
begin
262
  if(Reset)
263
    ReceiveEnd  <=#Tp 1'b0;
264
  else
265
    ReceiveEnd  <=#Tp LoadRxStatus;
266
end
267
 
268
 
269
// Invalid Symbol received during 100Mbps mode
270
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
271
 
272
 
273
// InvalidSymbol
274
always @ (posedge MRxClk or posedge Reset)
275
begin
276
  if(Reset)
277
    InvalidSymbol <=#Tp 1'b0;
278
  else
279
  if(LoadRxStatus & ~SetInvalidSymbol)
280
    InvalidSymbol <=#Tp 1'b0;
281
  else
282
  if(SetInvalidSymbol)
283
    InvalidSymbol <=#Tp 1'b1;
284
end
285
 
286
 
287
// Late Collision
288
 
289
reg RxLateCollision;
290
reg RxColWindow;
291
// Collision Window
292
always @ (posedge MRxClk or posedge Reset)
293
begin
294
  if(Reset)
295
    RxLateCollision <=#Tp 1'b0;
296
  else
297
  if(LoadRxStatus)
298
    RxLateCollision <=#Tp 1'b0;
299
  else
300
  if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
301
    RxLateCollision <=#Tp 1'b1;
302
end
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304
// Collision Window
305
always @ (posedge MRxClk or posedge Reset)
306
begin
307
  if(Reset)
308
    RxColWindow <=#Tp 1'b1;
309
  else
310
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
311
    RxColWindow <=#Tp 1'b0;
312
  else
313
  if(RxStateIdle)
314
    RxColWindow <=#Tp 1'b1;
315
end
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317
 
318
// ShortFrame
319
reg ShortFrame;
320
always @ (posedge MRxClk or posedge Reset)
321
begin
322
  if(Reset)
323
    ShortFrame <=#Tp 1'b0;
324
  else
325
  if(LoadRxStatus)
326
    ShortFrame <=#Tp 1'b0;
327
  else
328
  if(TakeSample)
329
    ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
330
end
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333
// DribbleNibble
334
reg DribbleNibble;
335
always @ (posedge MRxClk or posedge Reset)
336
begin
337
  if(Reset)
338
    DribbleNibble <=#Tp 1'b0;
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  else
340
  if(RxStateSFD)
341
    DribbleNibble <=#Tp 1'b0;
342
  else
343
  if(~MRxDV & RxStateData[1])
344
    DribbleNibble <=#Tp 1'b1;
345
end
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347
 
348
reg ReceivedPacketTooBig;
349
always @ (posedge MRxClk or posedge Reset)
350
begin
351
  if(Reset)
352
    ReceivedPacketTooBig <=#Tp 1'b0;
353
  else
354
  if(LoadRxStatus)
355
    ReceivedPacketTooBig <=#Tp 1'b0;
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  else
357
  if(TakeSample)
358
    ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
359
end
360
 
361
 
362
 
363
// Latched Retry counter for tx status
364
always @ (posedge MTxClk or posedge Reset)
365
begin
366
  if(Reset)
367
    RetryCntLatched <=#Tp 4'h0;
368
  else
369
  if(StartTxDone | StartTxAbort)
370
    RetryCntLatched <=#Tp RetryCnt;
371
end
372
 
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374
// Latched Retransmission limit
375
always @ (posedge MTxClk or posedge Reset)
376
begin
377
  if(Reset)
378
    RetryLimit <=#Tp 1'h0;
379
  else
380
  if(StartTxDone | StartTxAbort)
381
    RetryLimit <=#Tp MaxCollisionOccured;
382
end
383
 
384
 
385
// Latched Late Collision
386
always @ (posedge MTxClk or posedge Reset)
387
begin
388
  if(Reset)
389
    LateCollLatched <=#Tp 1'b0;
390
  else
391
  if(StartTxDone | StartTxAbort)
392
    LateCollLatched <=#Tp LateCollision;
393
end
394
 
395
 
396
 
397
// Latched Defer state
398
always @ (posedge MTxClk or posedge Reset)
399
begin
400
  if(Reset)
401
    DeferLatched <=#Tp 1'b0;
402
  else
403
  if(DeferIndication)
404
    DeferLatched <=#Tp 1'b1;
405
  else
406
  if(RstDeferLatched)
407
    DeferLatched <=#Tp 1'b0;
408
end
409
 
410
 
411
// CarrierSenseLost
412
always @ (posedge MTxClk or posedge Reset)
413
begin
414
  if(Reset)
415
    CarrierSenseLost <=#Tp 1'b0;
416
  else
417
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
418
    CarrierSenseLost <=#Tp 1'b1;
419
  else
420
  if(TxStartFrm)
421
    CarrierSenseLost <=#Tp 1'b0;
422
end
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endmodule

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