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// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_exu_alulogic.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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//
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// Module Name: sparc_exu_alulogic
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// Description: This block implements and, or, xor, xnor, nand, nor
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// and pass_rs2_data. And, or, Xor and pass are muxed together
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// and then xored with an inversion signal to create
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// xnor, nand and nor. Both inputs are buffered before being
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// used and the rs2_data signal is buffered again before going
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// to the mux.
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*/
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module sparc_exu_alulogic (/*AUTOARG*/
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// Outputs
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logic_out,
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// Inputs
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rs1_data, rs2_data, isand, isor, isxor, pass_rs2_data, inv_logic,
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ifu_exu_sethi_inst_e
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);
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input [63:0] rs1_data; // 1st input operand
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input [63:0] rs2_data; // 2nd input operand
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input isand;
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input isor;
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input isxor;
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input pass_rs2_data;
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input inv_logic;
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input ifu_exu_sethi_inst_e; // zero out top half of rs2 on mov
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output [63:0] logic_out; // output of logic block
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wire [63:0] rs1_data_bf1; // buffered rs1_data
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wire [63:0] rs2_data_bf1; // buffered rs2_data
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wire [63:0] mov_data;
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wire [63:0] result_and; // rs1_data & rs2_data
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wire [63:0] result_or; // rs1_data | rs2_data
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wire [63:0] result_xor; // rs1_data ^ rs2_data
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wire [63:0] rs2_xor_invert; // output of mux between various results
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// mux between various results
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mux4ds #(64) logic_mux(.dout(logic_out[63:0]),
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.in0(result_and[63:0]),
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.in1(result_or[63:0]),
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.in2(result_xor[63:0]),
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.in3(mov_data[63:0]),
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.sel0(isand),
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.sel1(isor),
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.sel2(isxor),
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.sel3(pass_rs2_data));
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// buffer inputs
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dp_buffer #(64) rs1_data_buf(.dout(rs1_data_bf1[63:0]), .in(rs1_data[63:0]));
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dp_buffer #(64) rs2_data_buf(.dout(rs2_data_bf1[63:0]), .in(rs2_data[63:0]));
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// zero out top of rs2 for sethi_inst
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assign mov_data[63:32] = rs2_data_bf1[63:32] & {32{~ifu_exu_sethi_inst_e}};
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dp_buffer #(32) rs2_data_buf2(.dout(mov_data[31:0]), .in(rs2_data_bf1[31:0]));
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// invert input2 for andn, orn, xnor
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assign rs2_xor_invert[63:0] = rs2_data_bf1[63:0] ^ {64{inv_logic}};
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// do boolean ops
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assign result_and = rs1_data_bf1 & rs2_xor_invert;
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assign result_or = rs1_data_bf1 | rs2_xor_invert;
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assign result_xor = rs1_data_bf1 ^ rs2_xor_invert;
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endmodule
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