OpenCores
URL https://opencores.org/ocsvn/sparc64soc/sparc64soc/trunk

Subversion Repositories sparc64soc

[/] [sparc64soc/] [trunk/] [T1-CPU/] [exu/] [sparc_exu_byp_eccgen.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dmitryr
// ========== Copyright Header Begin ==========================================
2
// 
3
// OpenSPARC T1 Processor File: sparc_exu_byp_eccgen.v
4
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6
// 
7
// The above named program is free software; you can redistribute it and/or
8
// modify it under the terms of the GNU General Public
9
// License version 2 as published by the Free Software Foundation.
10
// 
11
// The above named program is distributed in the hope that it will be 
12
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
// General Public License for more details.
15
// 
16
// You should have received a copy of the GNU General Public
17
// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19
// 
20
// ========== Copyright Header End ============================================
21
////////////////////////////////////////////////////////////////////////////////
22
//  Module Name: zzecc_exu_byp_eccgen2
23
//      Description: This block generates the 8 bit ecc for a 64 bit input
24
//                              It is split over 2 cycles to accomodate the timing requirements of 
25
//                              the other blocks.
26
 
27
module sparc_exu_byp_eccgen ( p, d, msk, clk, se);
28
   input [63:0] d;
29
   input [7:0]  msk;
30
   input        clk;
31
   input        se;
32
   output [7:0] p;
33
 
34
   wire [7:0]   p0_g;
35
   wire [7:0]   p0_w;
36
   wire [7:0]   p1_g;
37
   wire [7:0]   p1_w;
38
   wire [7:0]   p2_g;
39
   wire [7:0]   p2_w;
40
   wire [7:0]   p3_g;
41
   wire [7:0]   p3_w;
42
   wire [3:0]   p4_g;
43
   wire [3:0]   p4_w;
44
   wire [1:0]   p5_g;
45
   wire [1:0]   p5_w;
46
   wire [1:0]   p6_g;
47
   wire [1:0]   p6_w;
48
   wire [7:0]   p7_g;
49
   wire [7:0]   p7_w;
50
   wire         msk_w5;
51
   wire         msk_w4;
52
 
53
   // Flops to store intermediate results
54
  dff_s Imsk_5_  ( .q(msk_w5),  .din(msk[5]),  .clk(clk), .se(se), .si(), .so());
55
  dff_s Imsk_4_  ( .q(msk_w4),  .din(msk[4]),  .clk(clk), .se(se), .si(), .so());
56
  dff_s Ip0ff_7_ ( .q(p0_w[7]), .din(p0_g[7]), .clk(clk), .se(se), .si(), .so());
57
  dff_s Ip0ff_6_ ( .q(p0_w[6]), .din(p0_g[6]), .clk(clk), .se(se), .si(), .so());
58
  dff_s Ip0ff_5_ ( .q(p0_w[5]), .din(p0_g[5]), .clk(clk), .se(se), .si(), .so());
59
  dff_s Ip0ff_4_ ( .q(p0_w[4]), .din(p0_g[4]), .clk(clk), .se(se), .si(), .so());
60
  dff_s Ip0ff_3_ ( .q(p0_w[3]), .din(p0_g[3]), .clk(clk), .se(se), .si(), .so());
61
  dff_s Ip0ff_2_ ( .q(p0_w[2]), .din(p0_g[2]), .clk(clk), .se(se), .si(), .so());
62
  dff_s Ip0ff_1_ ( .q(p0_w[1]), .din(p0_g[1]), .clk(clk), .se(se), .si(), .so());
63
  dff_s Ip0ff_0_ ( .q(p0_w[0]), .din(p0_g[0]), .clk(clk), .se(se), .si(), .so());
64
  dff_s Ip1ff_7_ ( .q(p1_w[7]), .din(p1_g[7]), .clk(clk), .se(se), .si(), .so());
65
  dff_s Ip1ff_6_ ( .q(p1_w[6]), .din(p1_g[6]), .clk(clk), .se(se), .si(), .so());
66
  dff_s Ip1ff_5_ ( .q(p1_w[5]), .din(p1_g[5]), .clk(clk), .se(se), .si(), .so());
67
  dff_s Ip1ff_4_ ( .q(p1_w[4]), .din(p1_g[4]), .clk(clk), .se(se), .si(), .so());
68
  dff_s Ip1ff_3_ ( .q(p1_w[3]), .din(p1_g[3]), .clk(clk), .se(se), .si(), .so());
69
  dff_s Ip1ff_2_ ( .q(p1_w[2]), .din(p1_g[2]), .clk(clk), .se(se), .si(), .so());
70
  dff_s Ip1ff_1_ ( .q(p1_w[1]), .din(p1_g[1]), .clk(clk), .se(se), .si(), .so());
71
  dff_s Ip1ff_0_ ( .q(p1_w[0]), .din(p1_g[0]), .clk(clk), .se(se), .si(), .so());
72
  dff_s Ip2ff_7_ ( .q(p2_w[7]), .din(p2_g[7]), .clk(clk), .se(se), .si(), .so());
73
  dff_s Ip2ff_6_ ( .q(p2_w[6]), .din(p2_g[6]), .clk(clk), .se(se), .si(), .so());
74
  dff_s Ip2ff_5_ ( .q(p2_w[5]), .din(p2_g[5]), .clk(clk), .se(se), .si(), .so());
75
  dff_s Ip2ff_4_ ( .q(p2_w[4]), .din(p2_g[4]), .clk(clk), .se(se), .si(), .so());
76
  dff_s Ip2ff_3_ ( .q(p2_w[3]), .din(p2_g[3]), .clk(clk), .se(se), .si(), .so());
77
  dff_s Ip2ff_2_ ( .q(p2_w[2]), .din(p2_g[2]), .clk(clk), .se(se), .si(), .so());
78
  dff_s Ip2ff_1_ ( .q(p2_w[1]), .din(p2_g[1]), .clk(clk), .se(se), .si(), .so());
79
  dff_s Ip2ff_0_ ( .q(p2_w[0]), .din(p2_g[0]), .clk(clk), .se(se), .si(), .so());
80
  dff_s Ip3ff_7_ ( .q(p3_w[7]), .din(p3_g[7]), .clk(clk), .se(se), .si(), .so());
81
  dff_s Ip3ff_6_ ( .q(p3_w[6]), .din(p3_g[6]), .clk(clk), .se(se), .si(), .so());
82
  dff_s Ip3ff_5_ ( .q(p3_w[5]), .din(p3_g[5]), .clk(clk), .se(se), .si(), .so());
83
  dff_s Ip3ff_4_ ( .q(p3_w[4]), .din(p3_g[4]), .clk(clk), .se(se), .si(), .so());
84
  dff_s Ip3ff_3_ ( .q(p3_w[3]), .din(p3_g[3]), .clk(clk), .se(se), .si(), .so());
85
  dff_s Ip3ff_2_ ( .q(p3_w[2]), .din(p3_g[2]), .clk(clk), .se(se), .si(), .so());
86
  dff_s Ip3ff_1_ ( .q(p3_w[1]), .din(p3_g[1]), .clk(clk), .se(se), .si(), .so());
87
  dff_s Ip3ff_0_ ( .q(p3_w[0]), .din(p3_g[0]), .clk(clk), .se(se), .si(), .so());
88
  dff_s Ip4ff_3_ ( .q(p4_w[3]), .din(p4_g[3]), .clk(clk), .se(se), .si(), .so());
89
  dff_s Ip4ff_2_ ( .q(p4_w[2]), .din(p4_g[2]), .clk(clk), .se(se), .si(), .so());
90
  dff_s Ip4ff_1_ ( .q(p4_w[1]), .din(p4_g[1]), .clk(clk), .se(se), .si(), .so());
91
  dff_s Ip4ff_0_ ( .q(p4_w[0]), .din(p4_g[0]), .clk(clk), .se(se), .si(), .so());
92
  dff_s Ip5ff_1_ ( .q(p5_w[1]), .din(p5_g[1]), .clk(clk), .se(se), .si(), .so());
93
  dff_s Ip5ff_0_ ( .q(p5_w[0]), .din(p5_g[0]), .clk(clk), .se(se), .si(), .so());
94
  dff_s Ip6ff_1_ ( .q(p6_w[1]), .din(p6_g[1]), .clk(clk), .se(se), .si(), .so());
95
  dff_s Ip6ff_0_ ( .q(p6_w[0]), .din(p6_g[0]), .clk(clk), .se(se), .si(), .so());
96
  dff_s Ip7ff_7_ ( .q(p7_w[7]), .din(p7_g[7]), .clk(clk), .se(se), .si(), .so());
97
  dff_s Ip7ff_6_ ( .q(p7_w[6]), .din(p7_g[6]), .clk(clk), .se(se), .si(), .so());
98
  dff_s Ip7ff_5_ ( .q(p7_w[5]), .din(p7_g[5]), .clk(clk), .se(se), .si(), .so());
99
  dff_s Ip7ff_4_ ( .q(p7_w[4]), .din(p7_g[4]), .clk(clk), .se(se), .si(), .so());
100
  dff_s Ip7ff_3_ ( .q(p7_w[3]), .din(p7_g[3]), .clk(clk), .se(se), .si(), .so());
101
  dff_s Ip7ff_2_ ( .q(p7_w[2]), .din(p7_g[2]), .clk(clk), .se(se), .si(), .so());
102
  dff_s Ip7ff_1_ ( .q(p7_w[1]), .din(p7_g[1]), .clk(clk), .se(se), .si(), .so());
103
  dff_s Ip7ff_0_ ( .q(p7_w[0]), .din(p7_g[0]), .clk(clk), .se(se), .si(), .so());
104
 
105
 
106
   // p[0]
107
   assign p[0] = p0_w[0] ^ p0_w[1] ^ p0_w[2] ^ p0_w[3] ^ p0_w[4] ^ p0_w[5] ^ p0_w[6] ^ p0_w[7];
108
   assign p0_g[0] = d[0]  ^ d[1]  ^ d[3]  ^ d[4];
109
   assign p0_g[1] = d[6]  ^ d[8]  ^ d[10] ^ d[11];
110
   assign p0_g[2] = d[13] ^ d[15] ^ d[17] ^ d[19];
111
   assign p0_g[3] = d[21] ^ d[23] ^ d[25] ^ d[26];
112
   assign p0_g[4] = d[28] ^ d[30] ^ d[32] ^ d[34];
113
   assign p0_g[5] = d[36] ^ d[38] ^ d[40] ^ d[42];
114
   assign p0_g[6] = d[44] ^ d[46] ^ d[48] ^ d[50];
115
   assign p0_g[7] = d[52] ^ d[54] ^ d[56] ^ d[57] ^ d[59] ^ d[61] ^ d[63] ^ msk[0];
116
 
117
   // p[1]
118
   assign p[1] = p1_w[0] ^ p1_w[1] ^ p1_w[2] ^ p1_w[3] ^ p1_w[4] ^ p1_w[5] ^ p1_w[6] ^ p1_w[7];
119
   assign p1_g[0] = d[0]  ^ d[2]  ^ d[3]  ^ d[5];
120
   assign p1_g[1] = d[6]  ^ d[9]  ^ d[10] ^ d[12];
121
   assign p1_g[2] = d[13] ^ d[16] ^ d[17] ^ d[20];
122
   assign p1_g[3] = d[21] ^ d[24] ^ d[25] ^ d[27];
123
   assign p1_g[4] = d[28] ^ d[31] ^ d[32] ^ d[35];
124
   assign p1_g[5] = d[36] ^ d[39] ^ d[40] ^ d[43];
125
   assign p1_g[6] = d[44] ^ d[47] ^ d[48] ^ d[51];
126
   assign p1_g[7] = d[52] ^ d[55] ^ d[56] ^ d[58] ^ d[59] ^ d[62] ^ d[63] ^ msk[1];
127
 
128
   // p[2]
129
   assign p[2] = p2_w[0] ^ p2_w[1] ^ p2_w[2] ^ p2_w[3] ^ p2_w[4] ^ p2_w[5] ^ p2_w[6] ^ p2_w[7];
130
   assign p2_g[0] = d[1]  ^ d[2]  ^ d[3]  ^ d[7];
131
   assign p2_g[1] = d[8]  ^ d[9]  ^ d[10] ^ d[14];
132
   assign p2_g[2] = d[15] ^ d[16] ^ d[17] ^ d[22];
133
   assign p2_g[3] = d[23] ^ d[24] ^ d[25] ^ d[29];
134
   assign p2_g[4] = d[30] ^ d[31] ^ d[32] ^ d[37];
135
   assign p2_g[5] = d[38] ^ d[39] ^ d[40] ^ d[45];
136
   assign p2_g[6] = d[46] ^ d[47] ^ d[48] ^ d[53];
137
   assign p2_g[7] = d[54] ^ d[55] ^ d[56] ^ d[60] ^ d[61] ^ d[62] ^ d[63] ^ msk[2];
138
 
139
   // p[3]
140
   assign p[3] =  p3_w[0] ^ p3_w[1] ^ p3_w[2] ^ p3_w[3] ^ p3_w[4] ^ p3_w[5] ^ p3_w[6] ^ p3_w[7];
141
   assign p3_g[0] = d[4]  ^ d[5]  ^ d[6]  ^ d[7];
142
   assign p3_g[1] = d[8]  ^ d[9]  ^ d[10] ^ d[18];
143
   assign p3_g[2] = d[19] ^ d[20] ^ d[21] ^ d[22];
144
   assign p3_g[3] = d[23] ^ d[24] ^ d[25] ^ d[33];
145
   assign p3_g[4] = d[34] ^ d[35] ^ d[36] ^ d[37];
146
   assign p3_g[5] = d[38] ^ d[39] ^ d[40] ^ d[49];
147
   assign p3_g[6] = d[50] ^ d[51] ^ d[52] ^ d[53];
148
   assign p3_g[7] = d[54] ^ d[55] ^ d[56] ^ msk[3];
149
 
150
   // p[4]
151
   assign p[4] =  p4_w[0] ^ p4_w[1] ^ p4_w[2] ^ p4_w[3] ^ msk_w4;
152
 
153
   assign p4_g[0] = d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[16] ^ d[17] ^ d[18];
154
   assign p4_g[1] = d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[41];
155
   assign p4_g[2] = d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49];
156
   assign p4_g[3] = d[50] ^ d[51] ^ d[52] ^ d[53] ^ d[54] ^ d[55] ^ d[56];
157
 
158
   // p[5]
159
   assign p[5] =  p5_w[0] ^ p5_w[1] ^ p4_w[2] ^ p4_w[3] ^ msk_w5;
160
   assign p5_g[0] = d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31] ^ d[32] ^ d[33];
161
   assign p5_g[1] = d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38] ^ d[39] ^ d[40] ^ d[41];
162
/* -----\/----- EXCLUDED -----\/-----
163
   assign p5_g[2] = (d[42]  ^ d[43]  ^ d[44]  ^ d[45]  ^
164
                     d[46]  ^ d[47]  ^ d[48]  ^ d[49]);
165
   assign p5_g[3] = (d[50]  ^ d[51]  ^ d[52]  ^ d[53]  ^
166
                     d[54]  ^ d[55]  ^ d[56]);
167
 -----/\----- EXCLUDED -----/\----- */
168
 
169
   // p[6]
170
   assign p[6] =  p6_w[0] ^ p6_w[1];
171
   assign p6_g[0] = d[57] ^ d[58] ^ d[59] ^ d[60];
172
   assign p6_g[1] = d[61] ^ d[62] ^ d[63] ^ msk[6];
173
 
174
   // p[7]
175
   assign p[7] = p7_w[0] ^ p7_w[1] ^ p7_w[2] ^ p7_w[3] ^ p7_w[4] ^ p7_w[5] ^ p7_w[6] ^ p7_w[7];
176
   assign p7_g[0] = d[0]  ^ d[1]  ^ d[2]  ^ d[4];
177
   assign p7_g[1] = d[5]  ^ d[7]  ^ d[10] ^ d[11];
178
   assign p7_g[2] = d[12] ^ d[14] ^ d[17] ^ d[18];
179
   assign p7_g[3] = d[21] ^ d[23] ^ d[24] ^ d[26];
180
   assign p7_g[4] = d[27] ^ d[29] ^ d[32] ^ d[33];
181
   assign p7_g[5] = d[36] ^ d[38] ^ d[39] ^ d[41];
182
   assign p7_g[6] = d[44] ^ d[46] ^ d[47] ^ d[50];
183
   assign p7_g[7] = d[51] ^ d[53] ^ d[56] ^ d[57] ^ d[58] ^ d[60] ^ d[63] ^ msk[7];
184
 
185
endmodule // zzecc_exu_byp_eccgen3
186
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.