OpenCores
URL https://opencores.org/ocsvn/sparc64soc/sparc64soc/trunk

Subversion Repositories sparc64soc

[/] [sparc64soc/] [trunk/] [T1-CPU/] [exu/] [sparc_exu_ecl.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dmitryr 
// ========== Copyright Header Begin ==========================================
2 
//
3 
// OpenSPARC T1 Processor File: sparc_exu_ecl.v
4 
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5 
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6 
//
7 
// The above named program is free software; you can redistribute it and/or
8 
// modify it under the terms of the GNU General Public
9 
// License version 2 as published by the Free Software Foundation.
10 
//
11 
// The above named program is distributed in the hope that it will be
12 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 
// General Public License for more details.
15 
//
16 
// You should have received a copy of the GNU General Public
17 
// License along with this work; if not, write to the Free Software
18 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19 
//
20 
// ========== Copyright Header End ============================================
21 
////////////////////////////////////////////////////////////////////////
22 
/*
23 
//  Module Name: sparc_exu_ecl
24 
//      Description:  Implements all the control logic for the exu.
25 
//              This includes: bypass logic, ccr control and ccr bypassing,
26 
//                        w2 arbitration logic, mux selects for alu and shift.
27 
//                              Also implements the ccrs.
28 
*/
29 
 
30 
module sparc_exu_ecl
31 
(/*AUTOARG*/
32 
   // Outputs
33 
   exu_tlu_ccr3_w, exu_tlu_ccr2_w, exu_tlu_ccr1_w, exu_tlu_ccr0_w,
34 
   exu_mul_input_vld, exu_ifu_longop_done_g, exu_ifu_inj_ack,
35 
   exu_ifu_err_synd_7_m, exu_ifu_err_reg_m, exu_ifu_ecc_ue_m,
36 
   exu_ifu_ecc_ce_m, exu_ffu_wsr_inst_e, ecl_rml_wstate_wen_w,
37 
   ecl_rml_otherwin_wen_w, ecl_rml_cwp_wen_e, ecl_rml_cleanwin_wen_w,
38 
   ecl_rml_cansave_wen_w, ecl_rml_canrestore_wen_w,
39 
   ecl_ecc_sel_rs3_m_l, ecl_ecc_sel_rs2_m_l, ecl_ecc_sel_rs1_m_l,
40 
   ecl_ecc_log_rs3_m, ecl_ecc_log_rs2_m, ecl_ecc_log_rs1_m,
41 
   ecl_div_yreg_wen_w, ecl_div_yreg_wen_l, ecl_div_yreg_wen_g,
42 
   ecl_div_yreg_shift_g, ecl_div_xinmask, ecl_div_upper33_zero,
43 
   ecl_div_upper33_one, ecl_div_upper32_zero, ecl_div_subtract_l,
44 
   ecl_div_sel_u32, ecl_div_sel_pos32, ecl_div_sel_neg32,
45 
   ecl_div_sel_adder, ecl_div_sel_64b, ecl_div_newq,
46 
   ecl_div_mul_sext_rs2_e, ecl_div_mul_sext_rs1_e,
47 
   ecl_div_mul_keep_data, ecl_div_mul_get_new_data,
48 
   ecl_div_mul_get_32bit_data, ecl_div_last_cycle, ecl_div_keepx,
49 
   ecl_div_keep_d, ecl_div_dividend_sign, ecl_div_cin,
50 
   ecl_div_almostlast_cycle, ecl_byp_sel_restore_m,
51 
   ecl_byp_sel_restore_g, ecl_byp_sel_pipe_m, ecl_byp_sel_muldiv_g,
52 
   ecl_byp_sel_load_m, ecl_byp_sel_load_g, ecl_byp_eclpr_e,
53 
   ecl_byp_ecc_mask_m_l, so, ecl_byp_sel_alu_e, ecl_byp_sel_eclpr_e,
54 
   ecl_byp_sel_yreg_e, ecl_byp_sel_ifusr_e, ecl_byp_sel_ffusr_m,
55 
   ecl_byp_sel_ifex_m, ecl_byp_sel_tlusr_m, exu_ifu_va_oor_m,
56 
   ecl_alu_out_sel_sum_e_l, ecl_alu_out_sel_rs3_e_l,
57 
   ecl_alu_out_sel_shift_e_l, ecl_alu_out_sel_logic_e_l,
58 
   ecl_alu_log_sel_and_e, ecl_alu_log_sel_or_e,
59 
   ecl_alu_log_sel_xor_e, ecl_alu_log_sel_move_e,
60 
   ecl_alu_sethi_inst_e, ecl_alu_cin_e, ecl_shft_lshift_e_l,
61 
   ecl_shft_op32_e, ecl_shft_shift4_e, ecl_shft_shift1_e,
62 
   ecl_shft_enshift_e_l, ecl_byp_restore_m, ecl_byp_rs1_mux2_sel_e,
63 
   ecl_byp_rs1_mux2_sel_rf, ecl_byp_rs1_mux2_sel_ld,
64 
   ecl_byp_rs1_mux2_sel_usemux1, ecl_byp_rs1_mux1_sel_m,
65 
   ecl_byp_rs1_mux1_sel_w, ecl_byp_rs1_mux1_sel_w2,
66 
   ecl_byp_rs1_mux1_sel_other, ecl_byp_rcc_mux2_sel_e,
67 
   ecl_byp_rcc_mux2_sel_rf, ecl_byp_rcc_mux2_sel_ld,
68 
   ecl_byp_rcc_mux2_sel_usemux1, ecl_byp_rcc_mux1_sel_m,
69 
   ecl_byp_rcc_mux1_sel_w, ecl_byp_rcc_mux1_sel_w2,
70 
   ecl_byp_rcc_mux1_sel_other, ecl_byp_rs2_mux2_sel_e,
71 
   ecl_byp_rs2_mux2_sel_rf, ecl_byp_rs2_mux2_sel_ld,
72 
   ecl_byp_rs2_mux2_sel_usemux1, ecl_byp_rs2_mux1_sel_m,
73 
   ecl_byp_rs2_mux1_sel_w, ecl_byp_rs2_mux1_sel_w2,
74 
   ecl_byp_rs2_mux1_sel_other, ecl_byp_rs3_mux2_sel_e,
75 
   ecl_byp_rs3_mux2_sel_rf, ecl_byp_rs3_mux2_sel_ld,
76 
   ecl_byp_rs3_mux2_sel_usemux1, ecl_byp_rs3_mux1_sel_m,
77 
   ecl_byp_rs3_mux1_sel_w, ecl_byp_rs3_mux1_sel_w2,
78 
   ecl_byp_rs3_mux1_sel_other, ecl_byp_rs3h_mux2_sel_e,
79 
   ecl_byp_rs3h_mux2_sel_rf, ecl_byp_rs3h_mux2_sel_ld,
80 
   ecl_byp_rs3h_mux2_sel_usemux1, ecl_byp_rs3h_mux1_sel_m,
81 
   ecl_byp_rs3h_mux1_sel_w, ecl_byp_rs3h_mux1_sel_w2,
82 
   ecl_byp_rs3h_mux1_sel_other, ecl_byp_rs1_longmux_sel_g2,
83 
   ecl_byp_rs1_longmux_sel_w2, ecl_byp_rs1_longmux_sel_ldxa,
84 
   ecl_byp_rs2_longmux_sel_g2, ecl_byp_rs2_longmux_sel_w2,
85 
   ecl_byp_rs2_longmux_sel_ldxa, ecl_byp_rs3_longmux_sel_g2,
86 
   ecl_byp_rs3_longmux_sel_w2, ecl_byp_rs3_longmux_sel_ldxa,
87 
   ecl_byp_rs3h_longmux_sel_g2, ecl_byp_rs3h_longmux_sel_w2,
88 
   ecl_byp_rs3h_longmux_sel_ldxa, ecl_byp_std_e_l, ecl_byp_ldxa_g,
89 
   ecl_byp_3lsb_m, ecl_ecc_rs1_use_rf_e, ecl_ecc_rs2_use_rf_e,
90 
   ecl_ecc_rs3_use_rf_e, ecl_irf_rd_m, ecl_irf_tid_m, ecl_irf_wen_w,
91 
   ecl_irf_wen_w2, ecl_irf_rd_g, ecl_irf_tid_g, ecl_div_thr_e,
92 
   ecl_rml_thr_m, ecl_rml_thr_w, ecl_rml_xor_data_e,
93 
   ecl_div_ld_inputs, ecl_div_sel_div, ecl_div_div64, exu_ifu_cc_d,
94 
   ecl_shft_extendbit_e, ecl_shft_extend32bit_e_l,
95 
   ecl_div_zero_rs2_e, ecl_div_muls_rs1_31_e_l,
96 
   ecl_div_yreg_data_31_g, exu_tlu_va_oor_m, exu_tlu_va_oor_jl_ret_m,
97 
   ecl_rml_kill_e, ecl_rml_kill_w, ecl_byp_sel_ecc_m,
98 
   exu_tlu_ttype_m, exu_tlu_ttype_vld_m, exu_tlu_ue_trap_m,
99 
   exu_tlu_misalign_addr_jmpl_rtn_m, exu_lsu_priority_trap_m,
100 
   ecl_div_mul_wen, ecl_div_muls, ecl_rml_early_flush_w,
101 
   ecl_rml_inst_vld_w, ecl_alu_casa_e,
102 
   // Inputs
103 
   tlu_exu_cwpccr_update_m, tlu_exu_ccr_m, sehold, rst_tri_en,
104 
   rml_ecl_wstate_d, rml_ecl_swap_done, rml_ecl_rmlop_done_e,
105 
   rml_ecl_otherwin_d, rml_ecl_kill_m, rml_ecl_gl_e, rml_ecl_cwp_d,
106 
   rml_ecl_cleanwin_d, rml_ecl_cansave_d, rml_ecl_canrestore_d,
107 
   mul_exu_ack, lsu_exu_ldst_miss_g2, ifu_tlu_wsr_inst_d,
108 
   ifu_tlu_sraddr_d, ifu_exu_return_d, ifu_exu_muldivop_d,
109 
   ifu_exu_inst_vld_w, ifu_exu_inst_vld_e, ifu_exu_inj_irferr,
110 
   ifu_exu_ecc_mask, ifu_exu_disable_ce_e, ecc_ecl_rs3_ue,
111 
   ecc_ecl_rs3_ce, ecc_ecl_rs2_ue, ecc_ecl_rs2_ce, ecc_ecl_rs1_ue,
112 
   ecc_ecl_rs1_ce, div_ecl_xin_msb_l, div_ecl_x_msb,
113 
   div_ecl_upper32_equal, div_ecl_low32_nonzero,
114 
   div_ecl_gencc_in_msb_l, div_ecl_gencc_in_31, div_ecl_dividend_msb,
115 
   div_ecl_detect_zero_low, div_ecl_detect_zero_high, div_ecl_d_msb,
116 
   div_ecl_d_62, div_ecl_cout64, div_ecl_cout32,
117 
   div_ecl_adder_out_31, byp_ecl_wrccr_data_w, rclk, se, si, grst_l,
118 
   arst_l, ifu_exu_dbrinst_d, ifu_exu_aluop_d, ifu_exu_shiftop_d,
119 
   ifu_exu_invert_d, ifu_exu_usecin_d, ifu_exu_enshift_d,
120 
   byp_ecl_rs2_3_0_e, byp_ecl_rs1_2_0_e, byp_ecl_rd_data_3lsb_m,
121 
   ifu_exu_use_rsr_e_l, ifu_exu_rd_exusr_e, ifu_exu_rd_ifusr_e,
122 
   ifu_exu_rd_ffusr_e, ifu_exu_rs1_vld_d, ifu_exu_rs2_vld_d,
123 
   ifu_exu_rs3e_vld_d, ifu_exu_rs3o_vld_d, ifu_exu_dontmv_regz0_e,
124 
   ifu_exu_dontmv_regz1_e, ifu_exu_rd_d, ifu_exu_tid_s2,
125 
   ifu_exu_kill_e, ifu_exu_wen_d, ifu_exu_ialign_d, exu_ifu_regz_e,
126 
   alu_ecl_add_n64_e, alu_ecl_add_n32_e, alu_ecl_log_n64_e,
127 
   alu_ecl_log_n32_e, alu_ecl_zhigh_e, alu_ecl_zlow_e,
128 
   ifu_exu_setcc_d, lsu_exu_dfill_vld_g, lsu_exu_rd_m, lsu_exu_thr_m,
129 
   lsu_exu_ldxa_m, byp_ecl_rs1_31_e, byp_ecl_rs2_31_e,
130 
   byp_ecl_rs1_63_e, alu_ecl_cout64_e_l, alu_ecl_cout32_e,
131 
   alu_ecl_adder_out_63_e, alu_ecl_adder_out_31_e,
132 
   alu_ecl_adderin2_63_e, alu_ecl_adderin2_31_e, ifu_exu_rs1_s,
133 
   ifu_exu_rs2_s, ifu_exu_rs3_s, ifu_exu_tagop_d, ifu_exu_tv_d,
134 
   ifu_exu_muls_d, div_ecl_yreg_0_l, alu_ecl_mem_addr_invalid_e_l,
135 
   ifu_exu_range_check_jlret_d, ifu_exu_range_check_other_d,
136 
   ifu_exu_addr_mask_d, ifu_exu_save_d, ifu_exu_restore_d,
137 
   ifu_exu_casa_d, rml_ecl_clean_window_e, rml_ecl_fill_e,
138 
   rml_ecl_other_e, rml_ecl_wtype_e, ifu_exu_tcc_e,
139 
   alu_ecl_adder_out_7_0_e, ifu_exu_useimm_d, ifu_exu_nceen_e,
140 
   ifu_tlu_flush_m, ifu_exu_ttype_vld_m, tlu_exu_priv_trap_m,
141 
   tlu_exu_pic_onebelow_m, tlu_exu_pic_twobelow_m,
142 
   lsu_exu_flush_pipe_w, ifu_exu_sethi_inst_d,
143 
   lsu_exu_st_dtlb_perr_g
144 
   );
145 
 
146 
/*AUTOINPUT*/
147 
// Beginning of automatic inputs (from unused autoinst inputs)
148 
input [7:0]             byp_ecl_wrccr_data_w;   // To ccr of sparc_exu_eclccr.v
149 
input                   div_ecl_adder_out_31;   // To divcntl of sparc_exu_ecl_divcntl.v
150 
input                   div_ecl_cout32;         // To divcntl of sparc_exu_ecl_divcntl.v
151 
input                   div_ecl_cout64;         // To divcntl of sparc_exu_ecl_divcntl.v
152 
input                   div_ecl_d_62;           // To divcntl of sparc_exu_ecl_divcntl.v
153 
input                   div_ecl_d_msb;          // To divcntl of sparc_exu_ecl_divcntl.v
154 
input                   div_ecl_detect_zero_high;// To divcntl of sparc_exu_ecl_divcntl.v, ...
155 
input                   div_ecl_detect_zero_low;// To divcntl of sparc_exu_ecl_divcntl.v, ...
156 
input                   div_ecl_dividend_msb;   // To divcntl of sparc_exu_ecl_divcntl.v
157 
input                   div_ecl_gencc_in_31;    // To divcntl of sparc_exu_ecl_divcntl.v
158 
input                   div_ecl_gencc_in_msb_l; // To divcntl of sparc_exu_ecl_divcntl.v
159 
input                   div_ecl_low32_nonzero;  // To divcntl of sparc_exu_ecl_divcntl.v
160 
input                   div_ecl_upper32_equal;  // To divcntl of sparc_exu_ecl_divcntl.v
161 
input                   div_ecl_x_msb;          // To divcntl of sparc_exu_ecl_divcntl.v
162 
input                   div_ecl_xin_msb_l;      // To divcntl of sparc_exu_ecl_divcntl.v
163 
input                   ecc_ecl_rs1_ce;         // To eccctl of sparc_exu_ecl_eccctl.v
164 
input                   ecc_ecl_rs1_ue;         // To eccctl of sparc_exu_ecl_eccctl.v
165 
input                   ecc_ecl_rs2_ce;         // To eccctl of sparc_exu_ecl_eccctl.v
166 
input                   ecc_ecl_rs2_ue;         // To eccctl of sparc_exu_ecl_eccctl.v
167 
input                   ecc_ecl_rs3_ce;         // To eccctl of sparc_exu_ecl_eccctl.v
168 
input                   ecc_ecl_rs3_ue;         // To eccctl of sparc_exu_ecl_eccctl.v
169 
input                   ifu_exu_disable_ce_e;   // To eccctl of sparc_exu_ecl_eccctl.v
170 
input [7:0]             ifu_exu_ecc_mask;       // To eccctl of sparc_exu_ecl_eccctl.v
171 
input                   ifu_exu_inj_irferr;     // To eccctl of sparc_exu_ecl_eccctl.v
172 
input                   ifu_exu_inst_vld_e;     // To writeback of sparc_exu_ecl_wb.v, ...
173 
input                   ifu_exu_inst_vld_w;     // To ccr of sparc_exu_eclccr.v, ...
174 
input [4:0]             ifu_exu_muldivop_d;     // To mdqctl of sparc_exu_ecl_mdqctl.v
175 
input                   ifu_exu_return_d;       // To writeback of sparc_exu_ecl_wb.v
176 
input [6:0]             ifu_tlu_sraddr_d;       // To writeback of sparc_exu_ecl_wb.v
177 
input                   ifu_tlu_wsr_inst_d;     // To writeback of sparc_exu_ecl_wb.v
178 
input                   lsu_exu_ldst_miss_g2;   // To writeback of sparc_exu_ecl_wb.v
179 
input                   mul_exu_ack;            // To mdqctl of sparc_exu_ecl_mdqctl.v
180 
input [2:0]             rml_ecl_canrestore_d;   // To writeback of sparc_exu_ecl_wb.v
181 
input [2:0]             rml_ecl_cansave_d;      // To writeback of sparc_exu_ecl_wb.v
182 
input [2:0]             rml_ecl_cleanwin_d;     // To writeback of sparc_exu_ecl_wb.v
183 
input [2:0]             rml_ecl_cwp_d;          // To writeback of sparc_exu_ecl_wb.v, ...
184 
input [1:0]             rml_ecl_gl_e;           // To eccctl of sparc_exu_ecl_eccctl.v
185 
input                   rml_ecl_kill_m;         // To writeback of sparc_exu_ecl_wb.v
186 
input [2:0]             rml_ecl_otherwin_d;     // To writeback of sparc_exu_ecl_wb.v
187 
input                   rml_ecl_rmlop_done_e;   // To writeback of sparc_exu_ecl_wb.v
188 
input [3:0]             rml_ecl_swap_done;      // To writeback of sparc_exu_ecl_wb.v
189 
input [5:0]             rml_ecl_wstate_d;       // To writeback of sparc_exu_ecl_wb.v
190 
input                   rst_tri_en;             // To eccctl of sparc_exu_ecl_eccctl.v
191 
input                   sehold;                 // To writeback of sparc_exu_ecl_wb.v, ...
192 
input [7:0]             tlu_exu_ccr_m;          // To ccr of sparc_exu_eclccr.v
193 
input                   tlu_exu_cwpccr_update_m;// To ccr of sparc_exu_eclccr.v
194 
// End of automatics
195 
   input                                rclk;
196 
   input        se;
197 
   input        si;
198 
   input        grst_l;
199 
   input        arst_l;
200 
   input        ifu_exu_dbrinst_d;// rs1 bypass should use pc
201 
   input [2:0]  ifu_exu_aluop_d;// partially decoded op for exu operation
202 
   input [2:0]  ifu_exu_shiftop_d;
203 
   input        ifu_exu_invert_d;       // invert logic output
204 
   input        ifu_exu_usecin_d;        // use cin for add ops
205 
   input        ifu_exu_enshift_d;     // enable shifter
206 
   input [3:0]  byp_ecl_rs2_3_0_e;
207 
   input [2:0]  byp_ecl_rs1_2_0_e;
208 
   input [2:0]  byp_ecl_rd_data_3lsb_m;
209 
   input        ifu_exu_use_rsr_e_l;      // e stage instruction uses sr
210 
   input        ifu_exu_rd_exusr_e;
211 
   input        ifu_exu_rd_ifusr_e;
212 
   input        ifu_exu_rd_ffusr_e;
213 
   input        ifu_exu_rs1_vld_d;
214 
   input        ifu_exu_rs2_vld_d;
215 
   input        ifu_exu_rs3e_vld_d;
216 
   input        ifu_exu_rs3o_vld_d;
217 
   input        ifu_exu_dontmv_regz0_e;// a move instruction got killed
218 
   input        ifu_exu_dontmv_regz1_e;
219 
   input [4:0]  ifu_exu_rd_d;           // destination register
220 
   input [1:0]  ifu_exu_tid_s2;          // thread of inst in s stage
221 
   input        ifu_exu_kill_e;         // kill instruction in e-stage
222 
   input        ifu_exu_wen_d;  // instruction in d-stage writes to regfile
223 
   input        ifu_exu_ialign_d;// instruction is alignaddress
224 
   input        exu_ifu_regz_e;
225 
   input        alu_ecl_add_n64_e;
226 
   input        alu_ecl_add_n32_e;
227 
   input        alu_ecl_log_n64_e;
228 
   input        alu_ecl_log_n32_e;
229 
   input        alu_ecl_zhigh_e;
230 
   input        alu_ecl_zlow_e;
231 
   input        ifu_exu_setcc_d;
232 
   input        lsu_exu_dfill_vld_g; // load data is valid
233 
   input [4:0]  lsu_exu_rd_m;  // load destination register
234 
   input [1:0]  lsu_exu_thr_m; // load thread
235 
   input        lsu_exu_ldxa_m;
236 
   input  byp_ecl_rs1_31_e;
237 
   input  byp_ecl_rs2_31_e;
238 
   input  byp_ecl_rs1_63_e;
239 
   input       alu_ecl_cout64_e_l;
240 
   input       alu_ecl_cout32_e;
241 
   input       alu_ecl_adder_out_63_e;
242 
   input       alu_ecl_adder_out_31_e;
243 
   input       alu_ecl_adderin2_63_e;
244 
   input       alu_ecl_adderin2_31_e;
245 
   input [4:0]  ifu_exu_rs1_s;  // source addresses
246 
   input [4:0]  ifu_exu_rs2_s;
247 
   input [4:0]  ifu_exu_rs3_s;
248 
   input        ifu_exu_tagop_d;// add or sub sets icc.v with tagged overflow
249 
   input        ifu_exu_tv_d;   // 32 bit overflow causes exception
250 
   input  ifu_exu_muls_d;
251 
   input  [3:0] div_ecl_yreg_0_l;
252 
   input  alu_ecl_mem_addr_invalid_e_l;
253 
   input  ifu_exu_range_check_jlret_d;
254 
   input  ifu_exu_range_check_other_d;
255 
   input  ifu_exu_addr_mask_d;
256 
   input      ifu_exu_save_d;
257 
   input      ifu_exu_restore_d;
258 
   input      ifu_exu_casa_d;
259 
   input  rml_ecl_clean_window_e;
260 
   input  rml_ecl_fill_e;
261 
   input  rml_ecl_other_e;
262 
   input  [2:0] rml_ecl_wtype_e;
263 
   input        ifu_exu_tcc_e;
264 
   input [7:0]  alu_ecl_adder_out_7_0_e;
265 
   input       ifu_exu_useimm_d;
266 
   input       ifu_exu_nceen_e;
267 
   input       ifu_tlu_flush_m;
268 
   input       ifu_exu_ttype_vld_m;
269 
   input        tlu_exu_priv_trap_m;
270 
   input        tlu_exu_pic_onebelow_m;
271 
   input        tlu_exu_pic_twobelow_m;
272 
   input       lsu_exu_flush_pipe_w;
273 
   input       ifu_exu_sethi_inst_d;
274 
   input       lsu_exu_st_dtlb_perr_g;
275 
 
276 
   /*AUTOOUTPUT*/
277 
   // Beginning of automatic outputs (from unused autoinst outputs)
278 
   output [7:0]         ecl_byp_ecc_mask_m_l;   // From eccctl of sparc_exu_ecl_eccctl.v
279 
   output [7:0]         ecl_byp_eclpr_e;        // From writeback of sparc_exu_ecl_wb.v
280 
   output               ecl_byp_sel_load_g;     // From writeback of sparc_exu_ecl_wb.v
281 
   output               ecl_byp_sel_load_m;     // From writeback of sparc_exu_ecl_wb.v
282 
   output               ecl_byp_sel_muldiv_g;   // From writeback of sparc_exu_ecl_wb.v
283 
   output               ecl_byp_sel_pipe_m;     // From writeback of sparc_exu_ecl_wb.v
284 
   output               ecl_byp_sel_restore_g;  // From writeback of sparc_exu_ecl_wb.v
285 
   output               ecl_byp_sel_restore_m;  // From writeback of sparc_exu_ecl_wb.v
286 
   output               ecl_div_almostlast_cycle;// From divcntl of sparc_exu_ecl_divcntl.v
287 
   output               ecl_div_cin;            // From divcntl of sparc_exu_ecl_divcntl.v
288 
   output               ecl_div_dividend_sign;  // From divcntl of sparc_exu_ecl_divcntl.v
289 
   output               ecl_div_keep_d;         // From divcntl of sparc_exu_ecl_divcntl.v
290 
   output               ecl_div_keepx;          // From divcntl of sparc_exu_ecl_divcntl.v
291 
   output               ecl_div_last_cycle;     // From divcntl of sparc_exu_ecl_divcntl.v
292 
   output               ecl_div_mul_get_32bit_data;// From mdqctl of sparc_exu_ecl_mdqctl.v
293 
   output               ecl_div_mul_get_new_data;// From mdqctl of sparc_exu_ecl_mdqctl.v
294 
   output               ecl_div_mul_keep_data;  // From mdqctl of sparc_exu_ecl_mdqctl.v
295 
   output               ecl_div_mul_sext_rs1_e; // From mdqctl of sparc_exu_ecl_mdqctl.v
296 
   output               ecl_div_mul_sext_rs2_e; // From mdqctl of sparc_exu_ecl_mdqctl.v
297 
   output               ecl_div_newq;           // From divcntl of sparc_exu_ecl_divcntl.v
298 
   output               ecl_div_sel_64b;        // From divcntl of sparc_exu_ecl_divcntl.v
299 
   output               ecl_div_sel_adder;      // From divcntl of sparc_exu_ecl_divcntl.v
300 
   output               ecl_div_sel_neg32;      // From divcntl of sparc_exu_ecl_divcntl.v
301 
   output               ecl_div_sel_pos32;      // From divcntl of sparc_exu_ecl_divcntl.v
302 
   output               ecl_div_sel_u32;        // From divcntl of sparc_exu_ecl_divcntl.v
303 
   output               ecl_div_subtract_l;     // From divcntl of sparc_exu_ecl_divcntl.v
304 
   output               ecl_div_upper32_zero;   // From divcntl of sparc_exu_ecl_divcntl.v
305 
   output               ecl_div_upper33_one;    // From divcntl of sparc_exu_ecl_divcntl.v
306 
   output               ecl_div_upper33_zero;   // From divcntl of sparc_exu_ecl_divcntl.v
307 
   output               ecl_div_xinmask;        // From divcntl of sparc_exu_ecl_divcntl.v
308 
   output [3:0]         ecl_div_yreg_shift_g;   // From writeback of sparc_exu_ecl_wb.v
309 
   output [3:0]         ecl_div_yreg_wen_g;     // From writeback of sparc_exu_ecl_wb.v
310 
   output [3:0]         ecl_div_yreg_wen_l;     // From writeback of sparc_exu_ecl_wb.v
311 
   output [3:0]         ecl_div_yreg_wen_w;     // From writeback of sparc_exu_ecl_wb.v
312 
   output               ecl_ecc_log_rs1_m;      // From eccctl of sparc_exu_ecl_eccctl.v
313 
   output               ecl_ecc_log_rs2_m;      // From eccctl of sparc_exu_ecl_eccctl.v
314 
   output               ecl_ecc_log_rs3_m;      // From eccctl of sparc_exu_ecl_eccctl.v
315 
   output               ecl_ecc_sel_rs1_m_l;    // From eccctl of sparc_exu_ecl_eccctl.v
316 
   output               ecl_ecc_sel_rs2_m_l;    // From eccctl of sparc_exu_ecl_eccctl.v
317 
   output               ecl_ecc_sel_rs3_m_l;    // From eccctl of sparc_exu_ecl_eccctl.v
318 
   output               ecl_rml_canrestore_wen_w;// From writeback of sparc_exu_ecl_wb.v
319 
   output               ecl_rml_cansave_wen_w;  // From writeback of sparc_exu_ecl_wb.v
320 
   output               ecl_rml_cleanwin_wen_w; // From writeback of sparc_exu_ecl_wb.v
321 
   output               ecl_rml_cwp_wen_e;      // From writeback of sparc_exu_ecl_wb.v
322 
   output               ecl_rml_otherwin_wen_w; // From writeback of sparc_exu_ecl_wb.v
323 
   output               ecl_rml_wstate_wen_w;   // From writeback of sparc_exu_ecl_wb.v
324 
   output               exu_ffu_wsr_inst_e;     // From writeback of sparc_exu_ecl_wb.v
325 
   output               exu_ifu_ecc_ce_m;       // From eccctl of sparc_exu_ecl_eccctl.v
326 
   output               exu_ifu_ecc_ue_m;       // From eccctl of sparc_exu_ecl_eccctl.v
327 
   output [7:0]         exu_ifu_err_reg_m;      // From eccctl of sparc_exu_ecl_eccctl.v
328 
   output               exu_ifu_err_synd_7_m;   // From eccctl of sparc_exu_ecl_eccctl.v
329 
   output               exu_ifu_inj_ack;        // From eccctl of sparc_exu_ecl_eccctl.v
330 
   output [3:0]         exu_ifu_longop_done_g;  // From writeback of sparc_exu_ecl_wb.v
331 
   output               exu_mul_input_vld;      // From mdqctl of sparc_exu_ecl_mdqctl.v
332 
   output [7:0]         exu_tlu_ccr0_w;         // From ccr of sparc_exu_eclccr.v
333 
   output [7:0]         exu_tlu_ccr1_w;         // From ccr of sparc_exu_eclccr.v
334 
   output [7:0]         exu_tlu_ccr2_w;         // From ccr of sparc_exu_eclccr.v
335 
   output [7:0]         exu_tlu_ccr3_w;         // From ccr of sparc_exu_eclccr.v
336 
   // End of automatics
337 
   output               so;
338 
   output               ecl_byp_sel_alu_e;
339 
   output               ecl_byp_sel_eclpr_e;
340 
   output               ecl_byp_sel_yreg_e;
341 
   output               ecl_byp_sel_ifusr_e;
342 
   output               ecl_byp_sel_ffusr_m;
343 
   output               ecl_byp_sel_ifex_m;
344 
   output               ecl_byp_sel_tlusr_m;
345 
   output   exu_ifu_va_oor_m;
346 
   output ecl_alu_out_sel_sum_e_l;
347 
   output ecl_alu_out_sel_rs3_e_l;
348 
   output ecl_alu_out_sel_shift_e_l;
349 
   output ecl_alu_out_sel_logic_e_l;
350 
   output ecl_alu_log_sel_and_e;
351 
   output ecl_alu_log_sel_or_e;
352 
   output ecl_alu_log_sel_xor_e;
353 
   output ecl_alu_log_sel_move_e;
354 
   output ecl_alu_sethi_inst_e;
355 
   output ecl_alu_cin_e;    // cin for add/sub operations
356 
   output  ecl_shft_lshift_e_l;  // if 0 do left shift.  else right shift
357 
   output  ecl_shft_op32_e;      // indicates 32 bit operation so upper 32 = 0
358 
   //output [3:0] ecl_shft_shift16_e;// [48, 32, 16, 0] shift
359 
   output [3:0] ecl_shft_shift4_e;// [12, 8, 4, 0] shift
360 
   output [3:0] ecl_shft_shift1_e;// [3, 2, 1, 0] shift
361 
   output        ecl_shft_enshift_e_l;// enables inputs to shifter
362 
   output        ecl_byp_restore_m;
363 
   output ecl_byp_rs1_mux2_sel_e;// select lines for bypass muxes for rs1
364 
   output ecl_byp_rs1_mux2_sel_rf;
365 
   output ecl_byp_rs1_mux2_sel_ld;
366 
   output ecl_byp_rs1_mux2_sel_usemux1;
367 
   output ecl_byp_rs1_mux1_sel_m;
368 
   output ecl_byp_rs1_mux1_sel_w;
369 
   output ecl_byp_rs1_mux1_sel_w2;
370 
   output ecl_byp_rs1_mux1_sel_other;
371 
   output ecl_byp_rcc_mux2_sel_e;// select lines for bypass muxes for rcc
372 
   output ecl_byp_rcc_mux2_sel_rf;
373 
   output ecl_byp_rcc_mux2_sel_ld;
374 
   output ecl_byp_rcc_mux2_sel_usemux1;
375 
   output ecl_byp_rcc_mux1_sel_m;
376 
   output ecl_byp_rcc_mux1_sel_w;
377 
   output ecl_byp_rcc_mux1_sel_w2;
378 
   output ecl_byp_rcc_mux1_sel_other;
379 
   output ecl_byp_rs2_mux2_sel_e;// select lines for bypass muxes for rs2
380 
   output ecl_byp_rs2_mux2_sel_rf;
381 
   output ecl_byp_rs2_mux2_sel_ld;
382 
   output ecl_byp_rs2_mux2_sel_usemux1;
383 
   output ecl_byp_rs2_mux1_sel_m;
384 
   output ecl_byp_rs2_mux1_sel_w;
385 
   output ecl_byp_rs2_mux1_sel_w2;
386 
   output ecl_byp_rs2_mux1_sel_other;
387 
   output ecl_byp_rs3_mux2_sel_e; // select lines for bypass muxes for rs3
388 
   output ecl_byp_rs3_mux2_sel_rf;
389 
   output ecl_byp_rs3_mux2_sel_ld;
390 
   output ecl_byp_rs3_mux2_sel_usemux1;
391 
   output ecl_byp_rs3_mux1_sel_m;
392 
   output ecl_byp_rs3_mux1_sel_w;
393 
   output ecl_byp_rs3_mux1_sel_w2;
394 
   output ecl_byp_rs3_mux1_sel_other;
395 
   output ecl_byp_rs3h_mux2_sel_e; // select lines for bypass muxes for rs3 double
396 
   output ecl_byp_rs3h_mux2_sel_rf;
397 
   output ecl_byp_rs3h_mux2_sel_ld;
398 
   output ecl_byp_rs3h_mux2_sel_usemux1;
399 
   output ecl_byp_rs3h_mux1_sel_m;
400 
   output ecl_byp_rs3h_mux1_sel_w;
401 
   output ecl_byp_rs3h_mux1_sel_w2;
402 
   output ecl_byp_rs3h_mux1_sel_other;
403 
   output ecl_byp_rs1_longmux_sel_g2;
404 
   output ecl_byp_rs1_longmux_sel_w2;
405 
   output ecl_byp_rs1_longmux_sel_ldxa;
406 
   output ecl_byp_rs2_longmux_sel_g2;
407 
   output ecl_byp_rs2_longmux_sel_w2;
408 
   output ecl_byp_rs2_longmux_sel_ldxa;
409 
   output ecl_byp_rs3_longmux_sel_g2;
410 
   output ecl_byp_rs3_longmux_sel_w2;
411 
   output ecl_byp_rs3_longmux_sel_ldxa;
412 
   output ecl_byp_rs3h_longmux_sel_g2;
413 
   output ecl_byp_rs3h_longmux_sel_w2;
414 
   output ecl_byp_rs3h_longmux_sel_ldxa;
415 
   output ecl_byp_std_e_l;
416 
   output ecl_byp_ldxa_g;       // use the ldxa return data
417 
   output [2:0] ecl_byp_3lsb_m;
418 
   output                ecl_ecc_rs1_use_rf_e;
419 
   output                ecl_ecc_rs2_use_rf_e;
420 
   output                ecl_ecc_rs3_use_rf_e;
421 
   output  [4:0] ecl_irf_rd_m;
422 
   output  [1:0] ecl_irf_tid_m;
423 
   output        ecl_irf_wen_w;
424 
   output        ecl_irf_wen_w2;// write enable for w2
425 
   output  [4:0] ecl_irf_rd_g; // w2 destination register
426 
   output [1:0]  ecl_irf_tid_g;     // thread of inst in long w stage
427 
   output [3:0]  ecl_div_thr_e;
428 
   output [3:0] ecl_rml_thr_m;
429 
   output [3:0] ecl_rml_thr_w;
430 
   output [2:0] ecl_rml_xor_data_e;
431 
   output        ecl_div_ld_inputs;
432 
   output        ecl_div_sel_div;
433 
   output        ecl_div_div64;
434 
   output [7:0]  exu_ifu_cc_d;
435 
   output ecl_shft_extendbit_e;     // bit that gets appended on right shifts
436 
   output ecl_shft_extend32bit_e_l;   // bit that gets appended on 32 bit right shfts
437 
   output         ecl_div_zero_rs2_e;// used on muls ops
438 
   output         ecl_div_muls_rs1_31_e_l;
439 
   output         ecl_div_yreg_data_31_g;
440 
   output         exu_tlu_va_oor_m;
441 
   output         exu_tlu_va_oor_jl_ret_m;
442 
   output        ecl_rml_kill_e;
443 
   output        ecl_rml_kill_w;
444 
   output        ecl_byp_sel_ecc_m;
445 
   output [8:0] exu_tlu_ttype_m;
446 
   output       exu_tlu_ttype_vld_m;
447 
   output       exu_tlu_ue_trap_m;
448 
   output   exu_tlu_misalign_addr_jmpl_rtn_m;
449 
   output   exu_lsu_priority_trap_m;
450 
   output   ecl_div_mul_wen;
451 
   output   ecl_div_muls;
452 
   output   ecl_rml_early_flush_w;
453 
   output   ecl_rml_inst_vld_w;
454 
   output   ecl_alu_casa_e;
455 
 
456 
 
457 
   /*AUTOWIRE*/
458 
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
459 
   wire                 bypass_m;               // From writeback of sparc_exu_ecl_wb.v
460 
   wire                 bypass_w;               // From writeback of sparc_exu_ecl_wb.v
461 
   wire [7:0]           divcntl_ccr_cc_w2;      // From divcntl of sparc_exu_ecl_divcntl.v
462 
   wire                 divcntl_wb_req_g;       // From divcntl of sparc_exu_ecl_divcntl.v
463 
   wire [4:0]           eccctl_wb_rd_m;         // From eccctl of sparc_exu_ecl_eccctl.v
464 
   wire                 ecl_div_signed_div;     // From mdqctl of sparc_exu_ecl_mdqctl.v
465 
   wire                 mdqctl_divcntl_input_vld;// From mdqctl of sparc_exu_ecl_mdqctl.v
466 
   wire                 mdqctl_divcntl_muldone; // From mdqctl of sparc_exu_ecl_mdqctl.v
467 
   wire                 mdqctl_divcntl_reset_div;// From mdqctl of sparc_exu_ecl_mdqctl.v
468 
   wire [4:0]           mdqctl_wb_divrd_g;      // From mdqctl of sparc_exu_ecl_mdqctl.v
469 
   wire                 mdqctl_wb_divsetcc_g;   // From mdqctl of sparc_exu_ecl_mdqctl.v
470 
   wire [1:0]           mdqctl_wb_divthr_g;     // From mdqctl of sparc_exu_ecl_mdqctl.v
471 
   wire [4:0]           mdqctl_wb_mulrd_g;      // From mdqctl of sparc_exu_ecl_mdqctl.v
472 
   wire                 mdqctl_wb_mulsetcc_g;   // From mdqctl of sparc_exu_ecl_mdqctl.v
473 
   wire [1:0]           mdqctl_wb_multhr_g;     // From mdqctl of sparc_exu_ecl_mdqctl.v
474 
   wire                 mdqctl_wb_yreg_shift_g; // From mdqctl of sparc_exu_ecl_mdqctl.v
475 
   wire                 mdqctl_wb_yreg_wen_g;   // From mdqctl of sparc_exu_ecl_mdqctl.v
476 
   wire [4:0]           wb_byplog_rd_g2;        // From writeback of sparc_exu_ecl_wb.v
477 
   wire [4:0]           wb_byplog_rd_w2;        // From writeback of sparc_exu_ecl_wb.v
478 
   wire [1:0]           wb_byplog_tid_w2;       // From writeback of sparc_exu_ecl_wb.v
479 
   wire                 wb_byplog_wen_g2;       // From writeback of sparc_exu_ecl_wb.v
480 
   wire                 wb_byplog_wen_w2;       // From writeback of sparc_exu_ecl_wb.v
481 
   wire                 wb_ccr_setcc_g;         // From writeback of sparc_exu_ecl_wb.v
482 
   wire                 wb_ccr_wrccr_w;         // From writeback of sparc_exu_ecl_wb.v
483 
   wire                 wb_divcntl_ack_g;       // From writeback of sparc_exu_ecl_wb.v
484 
   wire                 wb_e;                   // From writeback of sparc_exu_ecl_wb.v
485 
   wire                 wb_eccctl_spec_wen_next;// From writeback of sparc_exu_ecl_wb.v
486 
   // End of automatics
487 
   wire                 clk;
488 
   wire                 reset;
489 
   wire                 ecl_reset_l;
490 
   wire                ecl_byp_rs1_mux2_sel_rf;// To eccctl of sparc_exu_ecl_eccctl.v
491 
   wire                ecl_byp_rs2_mux2_sel_rf;// To eccctl of sparc_exu_ecl_eccctl.v
492 
   wire                ecl_byp_rs3_mux2_sel_rf;// To eccctl of sparc_exu_ecl_eccctl.v
493 
   wire                ldxa_g;
494 
   wire                ecl_byp_ldxa_g;
495 
   wire                rs1_vld_e;
496 
   wire                rs2_vld_e;
497 
   wire                std_d;
498 
   wire                std_e;
499 
   wire                rs3_vld_d;
500 
   wire                rs3_vld_e;
501 
   wire                cancel_rs3_ecc_e;
502 
   wire [4:0]  ifu_exu_rs1_d;  // source addresses
503 
   wire [4:0]  ifu_exu_rs2_d;
504 
   wire [4:0]  ifu_exu_rs3_d;
505 
   wire [2:0]   ifu_exu_aluop_e;
506 
   wire [2:0]   shiftop_d;
507 
   wire [2:0]   shiftop_e;
508 
   wire         enshift_e;
509 
   wire         sel_sum_d;
510 
   wire         sel_sum_e;
511 
   wire         sub_e;        // Do subtraction for add ops
512 
   wire         shft_sext_e;     // sign extend for R shift.  must be 0 for left
513 
   wire         is_logic_e;       // opcode is for logic op
514 
   wire         dont_move_e;
515 
   wire         sethi_e;
516 
   wire [4:0]   rd_e;
517 
   wire  [4:0] rd_m;
518 
   wire  [4:0] ecl_irf_rd_w;
519 
   wire [1:0]  tid_d;
520 
   wire [3:0] thr_d;
521 
   wire [1:0]  tid_e;
522 
   wire  [1:0] tid_m;
523 
   wire [1:0]  tid_w;
524 
   wire [1:0]  tid_w1;
525 
   wire  [1:0] ecl_irf_tid_w;
526 
   wire [3:0]  thr_m;
527 
   wire [3:0]  ecl_rml_thr_w;
528 
   wire        ecl_irf_wen_w;
529 
   wire          extend64bit;   // bit that gets appended on 64 bit right shfts
530 
   wire         c_used_d;       // actual c_in calculated in d_stage
531 
   wire [1:0]  adder_xcc;
532 
   wire [1:0]  adder_icc;
533 
   wire        cc_e_3;          // cc_e for muls
534 
   wire        cc_e_1;
535 
   wire [3:0]  alu_xcc_e; // 64 bit ccs NZVC
536 
   wire [3:0]  alu_icc_e; // 32 bit ccs NZVC
537 
   wire        ialign_e;
538 
   wire        ialign_m;
539 
   wire        ifu_exu_tv_e;
540 
   wire        ifu_exu_tagop_e;
541 
   wire        tag_overflow;    // tag overflow has occured
542 
   wire     tag_overflow_trap_e;
543 
   wire           ifu_exu_range_check_jlret_e;
544 
   wire           ifu_exu_range_check_other_e;
545 
   wire           addr_mask_e;
546 
   wire           valid_range_check_jlret_e;
547 
   wire           ifu_exu_range_check_jlret_m;
548 
   wire           ifu_exu_range_check_other_m;
549 
   wire           alu_ecl_mem_addr_invalid_m_l;
550 
   wire           misalign_addr_e;
551 
   wire           muls_rs1_31_m_l;
552 
   wire           rs2_data_31_m;
553 
   wire       save_e;
554 
   wire       restore_e;
555 
   wire [4:0] real_rd_e;
556 
   wire       ifu_tlu_flush_w;
557 
   wire          flush_w;
558 
   wire          flush_w1;
559 
   wire          part_early_flush_m;
560 
   wire          part_early_flush_w;
561 
   wire          pic_trap_m;
562 
   wire          inst_vld_w1;
563 
   wire          tlu_priv_trap_w;
564 
   wire          early_flush_w;
565 
   wire          thr_match_ew;
566 
   wire          thr_match_mw1;
567 
   wire          thr_match_mw;
568 
   wire          thr_match_sd;
569 
   wire          thr_match_de;
570 
   wire          thr_match_se;
571 
   wire          thr_match_dm;
572 
   wire          ld_thr_match_sm;
573 
   wire          ld_thr_match_dg;
574 
   wire          ld_thr_match_sg;
575 
   wire          ld_thr_match_dg2;
576 
   wire              ecl_exu_kill_m;
577 
   wire              kill_rml_m;
578 
   wire          kill_rml_w;
579 
   wire [3:0]    perr_store_next;
580 
   wire [3:0]    perr_store;
581 
   wire [3:0]    perr_kill;
582 
   wire [4:0]    ld_rd_g;
583 
   wire [1:0]    ld_tid_g;
584 
 
585 
   wire          read_yreg_e;
586 
   wire          read_ffusr_e;
587 
   wire          read_tlusr_e;
588 
   wire          read_ffusr_m;
589 
   wire          read_tlusr_m;
590 
 
591 
   // trap logic
592 
   wire          ue_trap_m;
593 
   wire [8:0]    early1_ttype_e;
594 
   wire [8:0]    early2_ttype_e;
595 
   wire [8:0]    early_ttype_m;
596 
   wire          early_ttype_vld_e;
597 
   wire          early_ttype_vld_m;
598 
   wire          pick_not_aligned;
599 
   wire          pick_tcc;
600 
   wire          pick_normal_ttype;
601 
   wire          fill_trap_e;
602 
   wire          fill_trap_m;
603 
   wire       next_yreg_data_31;
604 
   wire       muls_e;
605 
   wire       zero_rs2_d;
606 
   wire       div_e;
607 
   wire       div_zero_m;
608 
 
609 
 
610 
   wire [4:0]  ifu_exu_rs1_e;
611 
   wire [4:0]  ifu_exu_rs1_m;
612 
   wire [4:0]  ifu_exu_rs2_e;
613 
   wire [4:0]  ifu_exu_rs2_m;
614 
   wire [4:0]  ifu_exu_rs3_e;
615 
   wire [4:0]  ifu_exu_rs3_m;
616 
   wire [3:0]  div_ecl_yreg_0;
617 
   wire   div_ecl_yreg_0_d;
618 
 
619 
   assign clk = rclk;
620 
   // Reset flop
621 
    dffrl_async rstff(.din (grst_l),
622 
                        .q   (ecl_reset_l),
623 
                        .clk (clk),
624 
                        .rst_l (arst_l), .se(se), .si(), .so());
625 
   assign reset = ~ecl_reset_l;
626 
 
627 
   // Pipeline flops for irf control signals
628 
   dff_s #(5) dff_rs1_s2d(.din(ifu_exu_rs1_s[4:0]), .clk(clk), .q(ifu_exu_rs1_d[4:0]), .se(se),
629 
                      .si(),.so());
630 
   dff_s #(5) dff_rs2_s2d(.din(ifu_exu_rs2_s[4:0]), .clk(clk), .q(ifu_exu_rs2_d[4:0]), .se(se),
631 
                      .si(),.so());
632 
   dff_s #(5) dff_rs3_s2d(.din(ifu_exu_rs3_s[4:0]), .clk(clk), .q(ifu_exu_rs3_d[4:0]), .se(se),
633 
                      .si(),.so());
634 
   dff_s #(5) dff_rs1_d2e(.din(ifu_exu_rs1_d[4:0]), .clk(clk), .q(ifu_exu_rs1_e[4:0]), .se(se),
635 
                      .si(),.so());
636 
   dff_s #(5) dff_rs2_d2e(.din(ifu_exu_rs2_d[4:0]), .clk(clk), .q(ifu_exu_rs2_e[4:0]), .se(se),
637 
                      .si(),.so());
638 
   dff_s #(5) dff_rs3_d2e(.din(ifu_exu_rs3_d[4:0]), .clk(clk), .q(ifu_exu_rs3_e[4:0]), .se(se),
639 
                      .si(),.so());
640 
   dff_s #(5) dff_rs1_e2m(.din(ifu_exu_rs1_e[4:0]), .clk(clk), .q(ifu_exu_rs1_m[4:0]), .se(se),
641 
                      .si(),.so());
642 
   dff_s #(5) dff_rs2_e2m(.din(ifu_exu_rs2_e[4:0]), .clk(clk), .q(ifu_exu_rs2_m[4:0]), .se(se),
643 
                      .si(),.so());
644 
   dff_s #(5) dff_rs3_e2m(.din(ifu_exu_rs3_e[4:0]), .clk(clk), .q(ifu_exu_rs3_m[4:0]), .se(se),
645 
                      .si(),.so());
646 
   dff_s #(5) dff_ld_rd_m2g(.din(lsu_exu_rd_m[4:0]), .clk(clk), .q(ld_rd_g[4:0]), .se(se), .si(), .so());
647 
   dff_s #(2) dff_ld_tid_m2g(.din(lsu_exu_thr_m[1:0]), .clk(clk), .q(ld_tid_g[1:0]), .se(se), .si(), .so());
648 
 
649 
   // Pipeline flops for control signals
650 
   dff_s #(3) dff_aluop_d2e(.din(ifu_exu_aluop_d[2:0]), .clk(clk), .q(ifu_exu_aluop_e[2:0]),
651 
                        .se(se), .si(), .so());
652 
   dff_s #(3) dff_shiftop_d2e(.din(shiftop_d[2:0]), .clk(clk),
653 
                          .q(shiftop_e[2:0]), .se(se),
654 
                          .si(), .so());
655 
   dff_s dff_enshift_d2e(.din(ifu_exu_enshift_d), .clk(clk), .q(enshift_e),
656 
                       .se(se), .si(), .so());
657 
   dff_s dff_sel_sum_d2e(.din(sel_sum_d), .clk(clk), .q(sel_sum_e),
658 
                       .se(se), .si(), .so());
659 
   dff_s dff_tv_d2e(.din(ifu_exu_tv_d), .clk(clk), .q(ifu_exu_tv_e),
660 
                  .se(se), .si(), .so());
661 
   dff_s dff_tagop_d2e(.din(ifu_exu_tagop_d), .clk(clk), .q(ifu_exu_tagop_e),
662 
                  .se(se), .si(), .so());
663 
   dff_s dff_ialign_d2e(.din(ifu_exu_ialign_d), .clk(clk), .q(ialign_e),
664 
                      .se(se), .si(), .so());
665 
   dff_s dff_ialign_e2m(.din(ialign_e), .clk(clk), .q(ialign_m),
666 
                      .se(se), .si(), .so());
667 
   dff_s ldxa_dff(.din(lsu_exu_ldxa_m), .clk(clk), .q(ldxa_g), .se(se), .si(), .so());
668 
   dff_s sethi_d2e(.din(ifu_exu_sethi_inst_d), .clk(clk), .q(sethi_e), .se(se), .si(), .so());
669 
   dff_s rs1_vld_d2e(.din(ifu_exu_rs1_vld_d), .clk(clk), .q(rs1_vld_e), .se(se), .si(), .so());
670 
   dff_s rs2_vld_d2e(.din(ifu_exu_rs2_vld_d), .clk(clk), .q(rs2_vld_e), .se(se), .si(), .so());
671 
   assign rs3_vld_d = ifu_exu_rs3e_vld_d | ifu_exu_rs3o_vld_d;
672 
   dff_s rs3_vld_d2e(.din(rs3_vld_d), .q(rs3_vld_e), .clk(clk), .se(se), .si(), .so());
673 
   dff_s casa_d2e(.din(ifu_exu_casa_d), .q(ecl_alu_casa_e), .clk(clk), .se(se), .si(), .so());
674 
 
675 
   ///////////////////////////////
676 
   // ALU Control
677 
   ///////////////////////////////
678 
   // Decode opcode for ALU
679 
   // aluop: [move, log1, log0]
680 
   // ADD = 00, AND = 01, OR = 10, XOR = 11
681 
   // log_sel: [and, or, xor, pass]
682 
   // out_sel: [sum, logic, shift]
683 
   assign ecl_alu_log_sel_and_e =
684 
          (~ifu_exu_aluop_e[2] & ~ifu_exu_aluop_e[1] & ifu_exu_aluop_e[0]);
685 
   assign ecl_alu_log_sel_or_e = (~ifu_exu_aluop_e[2] & ifu_exu_aluop_e[1]
686 
                                     & ~ifu_exu_aluop_e[0]);
687 
   assign ecl_alu_log_sel_xor_e = (~ifu_exu_aluop_e[2] & ifu_exu_aluop_e[1]
688 
                                      & ifu_exu_aluop_e[0]);
689 
   assign ecl_alu_log_sel_move_e =
690 
          (ifu_exu_aluop_e[2] | ~(ifu_exu_aluop_e[1] | ifu_exu_aluop_e[0]));
691 
 
692 
   assign is_logic_e = ifu_exu_aluop_e[2] | ifu_exu_aluop_e[1] |
693 
          ifu_exu_aluop_e[0];
694 
 
695 
   assign ecl_alu_sethi_inst_e = sethi_e;// | ifu_exu_sethi_inst_e;
696 
 
697 
   assign dont_move_e = (exu_ifu_regz_e)? ifu_exu_dontmv_regz1_e:ifu_exu_dontmv_regz0_e;
698 
 
699 
   assign sel_sum_d = ~(ifu_exu_enshift_d | ifu_exu_aluop_d[2] |ifu_exu_aluop_d[1] |ifu_exu_aluop_d[0]);
700 
   assign ecl_alu_out_sel_sum_e_l = ~sel_sum_e;
701 
   assign ecl_alu_out_sel_shift_e_l = ~(~is_logic_e & ~sel_sum_e);
702 
   assign ecl_alu_out_sel_logic_e_l = ~(is_logic_e & ~dont_move_e & ~sel_sum_e);
703 
   assign ecl_alu_out_sel_rs3_e_l = ~(is_logic_e & dont_move_e & ~sel_sum_e);// dontmove includes is_logic
704 
 
705 
   assign ecl_byp_sel_alu_e = ifu_exu_use_rsr_e_l;
706 
   assign ecl_byp_sel_ifusr_e = ~ifu_exu_use_rsr_e_l & ifu_exu_rd_ifusr_e;
707 
   assign ecl_byp_sel_yreg_e = ~ifu_exu_use_rsr_e_l & ~ifu_exu_rd_ifusr_e & read_yreg_e;
708 
   assign ecl_byp_sel_eclpr_e = ~ifu_exu_use_rsr_e_l & ~ifu_exu_rd_ifusr_e & ~read_yreg_e;
709 
 
710 
   assign read_ffusr_e = ~ifu_exu_use_rsr_e_l & ifu_exu_rd_ffusr_e;
711 
   assign read_tlusr_e = ~ifu_exu_use_rsr_e_l & ~ifu_exu_rd_ffusr_e & ~ifu_exu_rd_ifusr_e & ~ifu_exu_rd_exusr_e;
712 
   assign ecl_byp_sel_ffusr_m = read_ffusr_m;
713 
   assign ecl_byp_sel_tlusr_m = read_tlusr_m & ~read_ffusr_m;
714 
   assign ecl_byp_sel_ifex_m = ~read_tlusr_m & ~read_ffusr_m;
715 
 
716 
   dff_s #(2) rsr_e2m(.din({read_ffusr_e, read_tlusr_e}), .clk(clk),
717 
                    .q({read_ffusr_m, read_tlusr_m}), .se(se), .si(), .so());
718 
 
719 
   // ecc checking on rs3 will be cancelled if mov happens
720 
   assign cancel_rs3_ecc_e = ~dont_move_e & is_logic_e;
721 
 
722 
   // compute xor for write to cwp
723 
   assign ecl_rml_xor_data_e = byp_ecl_rs1_2_0_e[2:0] ^ byp_ecl_rs2_3_0_e[2:0];
724 
   // Logic for muls control signals
725 
   // icc.v ^ icc.n
726 
   assign         ecl_div_muls_rs1_31_e_l = ~(cc_e_3 ^ cc_e_1);
727 
   assign div_ecl_yreg_0[3:0] = ~div_ecl_yreg_0_l[3:0];
728 
   mux4ds yreg0_mux(.dout(div_ecl_yreg_0_d),
729 
                    .in0(div_ecl_yreg_0[0]),
730 
                    .in1(div_ecl_yreg_0[1]),
731 
                    .in2(div_ecl_yreg_0[2]),
732 
                    .in3(div_ecl_yreg_0[3]),
733 
                    .sel0(thr_d[0]),
734 
                    .sel1(thr_d[1]),
735 
                    .sel2(thr_d[2]),
736 
                    .sel3(thr_d[3]));
737 
 
738 
   assign zero_rs2_d = ifu_exu_muls_d & ~div_ecl_yreg_0_d;
739 
 
740 
   assign next_yreg_data_31 = (muls_e)? byp_ecl_rs1_2_0_e[0]:ecl_div_yreg_data_31_g;
741 
   dff_s dff_rs1_b0_m2w(.din(next_yreg_data_31), .clk(clk), .q(ecl_div_yreg_data_31_g),
742 
                .se(se), .si(), .so());
743 
 
744 
   // Logic for carryin and subtract
745 
   assign      c_used_d = ~(ifu_exu_invert_d ^ ~(exu_ifu_cc_d[0] & ifu_exu_usecin_d));
746 
   // Pipeline flops
747 
   dff_s sub_dff(.din(ifu_exu_invert_d), .clk(clk), .q(sub_e), .se(se),
748 
               .si(), .so());
749 
   dff_s c_used_dff(.din(c_used_d), .clk(clk), .q(ecl_alu_cin_e), .se(se),
750 
                 .si(), .so());
751 
   dff_s dff_muls_d2e(.din(ifu_exu_muls_d), .clk(clk), .q(muls_e),
752 
                .se(se), .si(), .so());
753 
   dff_s zero_rs2_dff(.din(zero_rs2_d), .clk(clk), .q(ecl_div_zero_rs2_e),
754 
                    .se(se), .si(), .so());
755 
   dff_s #(2) cc_d2e(.din({exu_ifu_cc_d[3],exu_ifu_cc_d[1]}), .clk(clk), .q({cc_e_3,cc_e_1}),
756 
                   .se(se), .si(), .so());
757 
   dff_s mulsrs131_e2m(.din(ecl_div_muls_rs1_31_e_l), .clk(clk),
758 
                     .q(muls_rs1_31_m_l),
759 
                     .se(se), .si(), .so());
760 
   dff_s rs2_31_e2m(.din(byp_ecl_rs2_31_e), .clk(clk),
761 
                  .q(rs2_data_31_m), .se(se), .si(), .so());
762 
 
763 
   dff_s save_dff(.din(ifu_exu_save_d), .clk(clk), .q(save_e), .se(se),
764 
                .si(), .so());
765 
   dff_s restore_dff(.din(ifu_exu_restore_d), .clk(clk), .q(restore_e), .se(se),
766 
                .si(), .so());
767 
 
768 
   // Condition code generation
769 
   assign      adder_xcc[0] = (~alu_ecl_cout64_e_l ^ sub_e) & sel_sum_e;
770 
   assign      adder_icc[0] = (alu_ecl_cout32_e ^ sub_e) & sel_sum_e;
771 
/* -----\/----- EXCLUDED -----\/-----
772 
   assign adder_xcc[1] = ((byp_ecl_rs1_63_e & alu_ecl_adderin2_63_e &
773 
                             ~alu_ecl_adder_out_63_e) |
774 
                           (~byp_ecl_rs1_63_e & ~alu_ecl_adderin2_63_e &
775 
                             alu_ecl_adder_out_63_e));
776 
   assign adder_icc[1] = ((byp_ecl_rs1_31_e & alu_ecl_adderin2_31_e &
777 
                             ~alu_ecl_adder_out_31_e) |
778 
                           (~byp_ecl_rs1_31_e & ~alu_ecl_adderin2_31_e &
779 
                             alu_ecl_adder_out_31_e));
780 
 -----/\----- EXCLUDED -----/\----- */
781 
   assign adder_xcc[1] = (alu_ecl_adder_out_63_e) ? (~byp_ecl_rs1_63_e & ~alu_ecl_adderin2_63_e & sel_sum_e):
782 
                                                      (byp_ecl_rs1_63_e & alu_ecl_adderin2_63_e & sel_sum_e);
783 
   assign adder_icc[1] = (alu_ecl_adder_out_31_e) ? ((~byp_ecl_rs1_31_e & ~alu_ecl_adderin2_31_e | tag_overflow)
784 
                                                     & sel_sum_e):
785 
                                                      ((byp_ecl_rs1_31_e & alu_ecl_adderin2_31_e | tag_overflow)
786 
                                                       & sel_sum_e);
787 
   // Tagged overflow
788 
   assign tag_overflow = (byp_ecl_rs1_2_0_e[0] | byp_ecl_rs1_2_0_e[1] |
789 
                          byp_ecl_rs2_3_0_e[0] | byp_ecl_rs2_3_0_e[1]) & ifu_exu_tagop_e;
790 
 
791 
   // Set V C ccs assuming they are 0s for logic and shifting
792 
   assign alu_xcc_e[3] = (sel_sum_e)? alu_ecl_add_n64_e: alu_ecl_log_n64_e;
793 
   assign alu_xcc_e[2] = alu_ecl_zlow_e & alu_ecl_zhigh_e;
794 
   assign alu_xcc_e[1:0] = adder_xcc[1:0]; // includes sel_sum
795 
 
796 
   assign alu_icc_e[3] = (sel_sum_e)? alu_ecl_add_n32_e: alu_ecl_log_n32_e;
797 
   assign alu_icc_e[2] = alu_ecl_zlow_e;
798 
   assign alu_icc_e[1:0] = adder_icc[1:0]; // includes sel_sum
799 
 
800 
   // Tag overflow exception on TV instruction with icc.v
801 
   assign   tag_overflow_trap_e = ifu_exu_tv_e & adder_icc[1];
802 
 
803 
   // Mem address exception generation and flops
804 
   assign   misalign_addr_e = (alu_ecl_adder_out_7_0_e[1] | alu_ecl_adder_out_7_0_e[0]) & ifu_exu_range_check_jlret_e;
805 
   // jlret is used for misalign (E stage) and va hole (M stage).
806 
   // if address mask is on then the va hole is not checked
807 
   assign   valid_range_check_jlret_e = ifu_exu_range_check_jlret_e & ~addr_mask_e;
808 
   assign   exu_ifu_va_oor_m = ~alu_ecl_mem_addr_invalid_m_l;
809 
   assign exu_tlu_va_oor_m = (~alu_ecl_mem_addr_invalid_m_l &
810 
                              ifu_exu_range_check_other_m);
811 
   assign exu_tlu_va_oor_jl_ret_m = (~alu_ecl_mem_addr_invalid_m_l &
812 
                                     ifu_exu_range_check_jlret_m);
813 
   dff_s dff_addr_mask_d2e (.din(ifu_exu_addr_mask_d), .clk(clk), .q(addr_mask_e),
814 
                          .se(se), .si(), .so());
815 
   dff_s dff_mem_invalid_e2m(.din(alu_ecl_mem_addr_invalid_e_l), .clk(clk),
816 
                           .q(alu_ecl_mem_addr_invalid_m_l), .se(se),
817 
                           .si(), .so());
818 
   dff_s dff_misalign_addr_e2m(.din(misalign_addr_e), .clk(clk),
819 
                           .q(exu_tlu_misalign_addr_jmpl_rtn_m), .se(se),
820 
                           .si(), .so());
821 
   dff_s dff_range_check_jlret_d2e(.din(ifu_exu_range_check_jlret_d), .clk(clk),
822 
                            .q(ifu_exu_range_check_jlret_e), .se(se),
823 
                            .si(), .so());
824 
   dff_s dff_range_check_jlret_e2m(.din(valid_range_check_jlret_e), .clk(clk),
825 
                            .q(ifu_exu_range_check_jlret_m), .se(se),
826 
                            .si(), .so());
827 
   dff_s dff_range_check_other_d2e(.din(ifu_exu_range_check_other_d), .clk(clk),
828 
                            .q(ifu_exu_range_check_other_e), .se(se),
829 
                            .si(), .so());
830 
   dff_s dff_range_check_other_e2m(.din(ifu_exu_range_check_other_e), .clk(clk),
831 
                            .q(ifu_exu_range_check_other_m), .se(se),
832 
                            .si(), .so());
833 
 
834 
   // 3lsbs can be zeroes for ialign
835 
   assign ecl_byp_3lsb_m[2:0] = (ialign_m)? 3'b0: byp_ecl_rd_data_3lsb_m[2:0];
836 
 
837 
   /////////////////////////////
838 
   // Generate Shift control
839 
   /////////////////////////////
840 
   assign shiftop_d[2:0] = ifu_exu_shiftop_d[2:0] & {3{ifu_exu_enshift_d}};
841 
   // shiftop:
842 
   //   2 = 64bit shift
843 
   //   1 = Rshift (1), LShift (0)
844 
   //   0 = arithmetic shift
845 
   assign ecl_shft_lshift_e_l = shiftop_e[1];
846 
   assign shft_sext_e = shiftop_e[0];
847 
   assign ecl_shft_op32_e = ~shiftop_e[2];
848 
   assign ecl_shft_enshift_e_l = ~enshift_e;
849 
   // decide what sign extension for right shifts should be (in parallel w/
850 
   // masking operation)
851 
   assign ecl_shft_extend32bit_e_l = ~(ecl_shft_op32_e & byp_ecl_rs1_31_e
852 
                                   & shft_sext_e);
853 
   assign extend64bit = shft_sext_e & byp_ecl_rs1_63_e &
854 
          ~ecl_shft_op32_e;
855 
   assign ecl_shft_extendbit_e = (extend64bit | ~ecl_shft_extend32bit_e_l);
856 
 
857 
   // Get rid of top bit for 32 bit instructions
858 
   //assign mod_shiftby_e[5]  = shiftop_e[2] & byp_ecl_rs2_3_0_e[5];
859 
   // decode shiftby input into mux control signals
860 
   //assign ecl_shft_shift16_e[0] = (~mod_shiftby_e[5] & ~mod_shiftby_e[4]);
861 
   //assign ecl_shft_shift16_e[1] = (~mod_shiftby_e[5] & mod_shiftby_e[4]);
862 
   //assign ecl_shft_shift16_e[2] = (mod_shiftby_e[5] & ~mod_shiftby_e[4]);
863 
   //assign ecl_shft_shift16_e[3] = (mod_shiftby_e[5] & mod_shiftby_e[4]);
864 
 
865 
   assign ecl_shft_shift4_e[0] = (~byp_ecl_rs2_3_0_e[3] & ~byp_ecl_rs2_3_0_e[2]);
866 
   assign ecl_shft_shift4_e[1] = (~byp_ecl_rs2_3_0_e[3] & byp_ecl_rs2_3_0_e[2]);
867 
   assign ecl_shft_shift4_e[2] = (byp_ecl_rs2_3_0_e[3] & ~byp_ecl_rs2_3_0_e[2]);
868 
   assign ecl_shft_shift4_e[3] = (byp_ecl_rs2_3_0_e[3] & byp_ecl_rs2_3_0_e[2]);
869 
 
870 
   assign ecl_shft_shift1_e[0] = (~byp_ecl_rs2_3_0_e[1] & ~byp_ecl_rs2_3_0_e[0]);
871 
   assign ecl_shft_shift1_e[1] = (~byp_ecl_rs2_3_0_e[1] & byp_ecl_rs2_3_0_e[0]);
872 
   assign ecl_shft_shift1_e[2] = (byp_ecl_rs2_3_0_e[1] & ~byp_ecl_rs2_3_0_e[0]);
873 
   assign ecl_shft_shift1_e[3] = (byp_ecl_rs2_3_0_e[1] & byp_ecl_rs2_3_0_e[0]);
874 
 
875 
 
876 
   // pipeline flops for bypass data
877 
   dff_s #(5) dff_rd_d2e(.din(ifu_exu_rd_d[4:0]), .clk(clk), .q(rd_e[4:0]), .se(se),
878 
                     .si(), .so());
879 
   // account for switch of ins outs on save/restore
880 
   assign real_rd_e[4] = rd_e[4] ^ (rd_e[3] & (save_e | restore_e));
881 
   assign real_rd_e[3:0] = rd_e[3:0];
882 
   dff_s #(5) dff_rd_e2m(.din(real_rd_e[4:0]), .clk(clk), .q(rd_m[4:0]), .se(se),
883 
                     .si(), .so());
884 
   dff_s #(5) dff_rd_m2w(.din(ecl_irf_rd_m[4:0]), .clk(clk), .q(ecl_irf_rd_w[4:0]), .se(se),
885 
                     .si(), .so());
886 
   dff_s #(2) dff_thr_s2d(.din(ifu_exu_tid_s2[1:0]), .clk(clk), .q(tid_d[1:0]), .se(se),
887 
                      .si(), .so());
888 
   dff_s #(2) dff_tid_d2e(.din(tid_d[1:0]), .clk(clk), .q(tid_e[1:0]), .se(se),
889 
                      .si(), .so());
890 
   dff_s #(2) dff_thr_e2m(.din(tid_e[1:0]), .clk(clk), .q(tid_m[1:0]), .se(se),
891 
                      .si(), .so());
892 
   // Need the original thr and the one with ld thr muxed in
893 
   dff_s #(2) dff_tid_m2w(.din(tid_m[1:0]), .clk(clk), .q(tid_w[1:0]), .se(se),
894 
                      .si(), .so());
895 
   dff_s #(2) dff_tid_w2w1(.din(tid_w[1:0]), .clk(clk), .q(tid_w1[1:0]), .se(se),
896 
                      .si(), .so());
897 
   dff_s #(2) dff_irf_thr_m2w(.din(ecl_irf_tid_m[1:0]), .clk(clk), .q(ecl_irf_tid_w[1:0]), .se(se),
898 
                      .si(), .so());
899 
 
900 
   // Thread decode
901 
   // decode tid_d
902 
   assign        thr_d[0] = ~tid_d[1] & ~tid_d[0];
903 
   assign        thr_d[1] = ~tid_d[1] & tid_d[0];
904 
   assign        thr_d[2] = tid_d[1] & ~tid_d[0];
905 
   assign        thr_d[3] = tid_d[1] & tid_d[0];
906 
 
907 
   // decode thr_e
908 
   assign        ecl_div_thr_e[0] = ~tid_e[1] & ~tid_e[0];
909 
   assign        ecl_div_thr_e[1] = ~tid_e[1] & tid_e[0];
910 
   assign        ecl_div_thr_e[2] = tid_e[1] & ~tid_e[0];
911 
   assign        ecl_div_thr_e[3] = tid_e[1] & tid_e[0];
912 
 
913 
   // decode thr_m
914 
   assign        thr_m[0] = ~tid_m[1] & ~tid_m[0];
915 
   assign        thr_m[1] = ~tid_m[1] & tid_m[0];
916 
   assign        thr_m[2] = tid_m[1] & ~tid_m[0];
917 
   assign        thr_m[3] = tid_m[1] & tid_m[0];
918 
   assign        ecl_rml_thr_m[3:0] = thr_m[3:0];
919 
   // decode tid_w
920 
   assign        ecl_rml_thr_w[0] = ~tid_w[1] & ~tid_w[0];
921 
   assign        ecl_rml_thr_w[1] = ~tid_w[1] & tid_w[0];
922 
   assign        ecl_rml_thr_w[2] = tid_w[1] & ~tid_w[0];
923 
   assign        ecl_rml_thr_w[3] = tid_w[1] & tid_w[0];
924 
 
925 
   //////////////////////////////////////
926 
   // Kill logic
927 
   //////////////////////////////////////
928 
   // a parity error on a store should kill the next instruction on that thread
929 
   // perr_store_w sets the bit.  perr_kill_m says that the instruction in M should
930 
   // be killed.  However, it does not check inst_vld or flush so it might be killing
931 
   // an invalid instruction.  Therefore perr_store does not get cleared until W.  This
932 
   // might cause an extra perr_kill_m, but that is OK because subsequent instructions will
933 
   // be killed until the trap is taken.
934 
   wire [3:0]    perr_store_w;
935 
   wire [3:0]    perr_clear_w;
936 
   wire          perr_kill_m;
937 
   assign        perr_store_w[3] = tid_w[1] & tid_w[0] & lsu_exu_st_dtlb_perr_g;
938 
   assign        perr_store_w[2] = tid_w[1] & ~tid_w[0] & lsu_exu_st_dtlb_perr_g;
939 
   assign        perr_store_w[1] = ~tid_w[1] & tid_w[0] & lsu_exu_st_dtlb_perr_g;
940 
   assign        perr_store_w[0] = ~tid_w[1] & ~tid_w[0] & lsu_exu_st_dtlb_perr_g;
941 
   assign        perr_store_next[3] = perr_store_w[3] | perr_store[3] & ~perr_clear_w[3];
942 
   assign        perr_store_next[2] = perr_store_w[2] | perr_store[2] & ~perr_clear_w[2];
943 
   assign        perr_store_next[1] = perr_store_w[1] | perr_store[1] & ~perr_clear_w[1];
944 
   assign        perr_store_next[0] = perr_store_w[0] | perr_store[0] & ~perr_clear_w[0];
945 
   assign        perr_kill[3] = tid_m[1] & tid_m[0] & perr_store[3];
946 
   assign        perr_kill[2] = tid_m[1] & ~tid_m[0] & perr_store[2];
947 
   assign        perr_kill[1] = ~tid_m[1] & tid_m[0] & perr_store[1];
948 
   assign        perr_kill[0] = ~tid_m[1] & ~tid_m[0] & perr_store[0];
949 
   assign        perr_kill_m = |perr_kill[3:0] | lsu_exu_st_dtlb_perr_g & thr_match_mw;
950 
   assign        perr_clear_w[3] = tid_w[1] & tid_w[0] & perr_store[3] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
951 
   assign        perr_clear_w[2] = tid_w[1] & ~tid_w[0] & perr_store[2] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
952 
   assign        perr_clear_w[1] = ~tid_w[1] & tid_w[0] & perr_store[1] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
953 
   assign        perr_clear_w[0] = ~tid_w[1] & ~tid_w[0] & perr_store[0] & ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
954 
 
955 
   dffr_s #(4) perr_dff(.din(perr_store_next[3:0]), .clk(clk), .q(perr_store[3:0]), .si(), .so(), .se(se), .rst(reset));
956 
 
957 
   // calculate an early flush for killing writes in W
958 
   // the pic trap occurs if there are too many instructions on a given thread.
959 
   dff_s inst_vld_ww1(.din(ifu_exu_inst_vld_w), .clk(clk), .q(inst_vld_w1), .se(se), .si(), .so());
960 
   assign pic_trap_m = ((tlu_exu_pic_onebelow_m & (thr_match_mw & ifu_exu_inst_vld_w |
961 
                                                   thr_match_mw1 & inst_vld_w1)) |
962 
                        (tlu_exu_pic_twobelow_m & thr_match_mw & ifu_exu_inst_vld_w &
963 
                         thr_match_mw1 & inst_vld_w1));
964 
   assign        part_early_flush_m = (exu_tlu_ttype_vld_m | ifu_exu_ttype_vld_m | exu_tlu_va_oor_jl_ret_m |
965 
                                       perr_kill_m | pic_trap_m);
966 
   dff_s priv_trap_dff(.din(tlu_exu_priv_trap_m), .clk(clk), .q(tlu_priv_trap_w), .se(se), .si(), .so());
967 
   dff_s early_flush_dff(.din(part_early_flush_m), .clk(clk), .q(part_early_flush_w), .se(se), .si(), .so());
968 
   assign        early_flush_w = part_early_flush_w | tlu_priv_trap_w;
969 
   assign        ecl_rml_early_flush_w = early_flush_w;
970 
 
971 
   // buffer this off so it only sees one load from the ifu
972 
   assign        ecl_rml_inst_vld_w = ifu_exu_inst_vld_w & ~ifu_tlu_flush_w;
973 
 
974 
   dff_s flush_m2w(.din(ifu_tlu_flush_m), .clk(clk), .q(ifu_tlu_flush_w), .se(se), .si(), .so());
975 
   assign        flush_w = ifu_tlu_flush_w | lsu_exu_flush_pipe_w;
976 
   dff_s flush_w_dff(.din(flush_w), .clk(clk), .q(flush_w1), .se(se), .si(), .so());
977 
   // allow misalign address on returns to kill the cwp switch
978 
   // ttype[7] is a fill_trap so the return misalign should be ignored
979 
   // UE trap should kill window ops.  This check is needed here because the
980 
   // window traps will override the flush_W signals.
981 
   assign        kill_rml_m = (ue_trap_m | ifu_exu_ttype_vld_m | perr_kill_m | pic_trap_m |
982 
                               (exu_tlu_misalign_addr_jmpl_rtn_m & ~exu_tlu_ttype_m[7]));
983 
   dff_s kill_rml_mw(.din(kill_rml_m), .clk(clk) , .q(kill_rml_w), .se(se), .si(), .so());
984 
   // include tlu_priv_trap to cancel window traps
985 
   assign        ecl_rml_kill_w = tlu_priv_trap_w | kill_rml_w;
986 
 
987 
   // pass kill_e through to the rml
988 
   assign        ecl_rml_kill_e = ifu_exu_kill_e;
989 
 
990 
   assign        ecl_exu_kill_m = thr_match_mw1 & flush_w1;
991 
   assign thr_match_mw = ~((tid_w[1] ^ tid_m[1]) |
992 
                           (tid_w[0] ^ tid_m[0]));
993 
   assign thr_match_ew = ~((tid_e[1] ^ tid_w[1]) |
994 
                           (tid_e[0] ^ tid_w[0]));
995 
   dff_s thr_match_ew_dff(.din(thr_match_ew), .clk(clk), .q(thr_match_mw1), .se(se), .si(), .so());
996 
 
997 
   // ldxa needs to check inst_vld and prior flushes
998 
   assign ecl_byp_ldxa_g = ldxa_g & ifu_exu_inst_vld_w;
999 
 
1000 
   // controls for outputs to lsu
1001 
   assign std_d = ifu_exu_rs3e_vld_d & ifu_exu_rs3o_vld_d;
1002 
   dff_s std_d2e (.din(std_d), .q(std_e), .clk(clk), .se(se), .si(), .so());
1003 
   assign ecl_byp_std_e_l = ~std_e;
1004 
 
1005 
 
1006 
   //////////////////////////////////////
1007 
   // Trap output logic
1008 
   //-----------------------
1009 
   // In pipe traps (with priority order):
1010 
   // 029h: uncorrected ecc trap
1011 
   // 0C0h-0FFh: Fill trap
1012 
   // 024h: clean window trap
1013 
   // 034h: mem_address_not_aligned
1014 
   // 023h: Tag Overflow
1015 
   // 028h: Div by zero
1016 
   // 100h-17Fh: Trap instruction
1017 
   //////////////////////////////////////
1018 
   // ecc traps must be enabled
1019 
   assign fill_trap_e = rml_ecl_fill_e;
1020 
 
1021 
   assign early_ttype_vld_e = (rml_ecl_clean_window_e | rml_ecl_fill_e |
1022 
                                 tag_overflow_trap_e | ifu_exu_tcc_e |
1023 
                                 misalign_addr_e);
1024 
   // This ttype includes clean window, fill, tag overflow, tcc, misalign address, and div zero.
1025 
   // Note that this will be div_zero on any divide instruction.  The valid will only be asserted if
1026 
   // div_zero is detected though.
1027 
   assign early1_ttype_e[8] = 1'b0;
1028 
   assign early1_ttype_e[7] = fill_trap_e;
1029 
   assign early1_ttype_e[6] = fill_trap_e;
1030 
   assign early1_ttype_e[5] = (rml_ecl_fill_e & rml_ecl_other_e) |
1031 
                                (~rml_ecl_fill_e & (rml_ecl_clean_window_e | tag_overflow_trap_e | div_e));
1032 
   assign early1_ttype_e[4] = fill_trap_e & rml_ecl_wtype_e[2];
1033 
   assign early1_ttype_e[3] = (rml_ecl_fill_e & rml_ecl_wtype_e[1]) |
1034 
                           (~rml_ecl_fill_e & ~rml_ecl_clean_window_e & ~tag_overflow_trap_e & div_e);
1035 
   assign early1_ttype_e[2] = (fill_trap_e & rml_ecl_wtype_e[0]) |
1036 
                                 (~rml_ecl_fill_e & rml_ecl_clean_window_e);
1037 
   assign early1_ttype_e[1] = ~rml_ecl_fill_e & ~rml_ecl_clean_window_e & tag_overflow_trap_e;
1038 
   assign early1_ttype_e[0] = (~rml_ecl_fill_e & ~rml_ecl_clean_window_e & tag_overflow_trap_e);
1039 
 
1040 
   // mux together the ttypes
1041 
   // tcc only can be combined with an ue which is caught later so it isn't qualified by other traps
1042 
   assign pick_normal_ttype = ~pick_not_aligned & ~ifu_exu_tcc_e;
1043 
   assign pick_tcc = ifu_exu_tcc_e;
1044 
   assign pick_not_aligned = ~(rml_ecl_fill_e | rml_ecl_clean_window_e) & misalign_addr_e & ~ifu_exu_tcc_e;
1045 
 
1046 
   // the ue ttype is muxed in after the flop because it is so late
1047 
   mux3ds #(9) ttype_mux(.dout(early2_ttype_e[8:0]),
1048 
                         .in0(early1_ttype_e[8:0]),
1049 
                         .in1({1'b1, alu_ecl_adder_out_7_0_e[7:0]}),
1050 
                         .in2(9'h034),
1051 
                         .sel0(pick_normal_ttype),
1052 
                         .sel1(pick_tcc),
1053 
                         .sel2(pick_not_aligned));
1054 
   assign exu_tlu_ttype_m[8:0] = (ue_trap_m)? 9'h029: early_ttype_m[8:0];
1055 
   assign exu_tlu_ttype_vld_m = early_ttype_vld_m | ue_trap_m | div_zero_m;
1056 
   assign exu_tlu_ue_trap_m = ue_trap_m;
1057 
 
1058 
   dff_s ttype_vld_e2m(.din(early_ttype_vld_e), .clk(clk), .q(early_ttype_vld_m),
1059 
                     .se(se), .si(), .so());
1060 
   dff_s #(9) ttype_e2m(.din(early2_ttype_e[8:0]), .clk(clk), .q(early_ttype_m[8:0]),
1061 
                    .se(se), .si(), .so());
1062 
   // lsu needs to know about spill and ue traps for squashing sfsr writes
1063 
   dff_s fill_e2m(.din(fill_trap_e), .clk(clk), .q(fill_trap_m), .se(se), .si(), .so());
1064 
   assign exu_lsu_priority_trap_m = fill_trap_m | ue_trap_m;
1065 
 
1066 
   // Condition code Register
1067 
   sparc_exu_eclccr ccr(.wb_ccr_thr_g(ecl_irf_tid_g[1:0]),
1068 
                        .thrdec_d  (thr_d[3:0]),
1069 
                        .thr_w  (ecl_rml_thr_w[3:0]),
1070 
                       /*AUTOINST*/
1071 
                        // Outputs
1072 
                        .exu_ifu_cc_d   (exu_ifu_cc_d[7:0]),
1073 
                        .exu_tlu_ccr0_w (exu_tlu_ccr0_w[7:0]),
1074 
                        .exu_tlu_ccr1_w (exu_tlu_ccr1_w[7:0]),
1075 
                        .exu_tlu_ccr2_w (exu_tlu_ccr2_w[7:0]),
1076 
                        .exu_tlu_ccr3_w (exu_tlu_ccr3_w[7:0]),
1077 
                        // Inputs
1078 
                        .clk            (clk),
1079 
                        .se             (se),
1080 
                        .alu_xcc_e      (alu_xcc_e[3:0]),
1081 
                        .alu_icc_e      (alu_icc_e[3:0]),
1082 
                        .tid_d          (tid_d[1:0]),
1083 
                        .thr_match_dm   (thr_match_dm),
1084 
                        .thr_match_de   (thr_match_de),
1085 
                        .tid_w          (tid_w[1:0]),
1086 
                        .ifu_exu_kill_e (ifu_exu_kill_e),
1087 
                        .ifu_exu_setcc_d(ifu_exu_setcc_d),
1088 
                        .byp_ecl_wrccr_data_w(byp_ecl_wrccr_data_w[7:0]),
1089 
                        .wb_ccr_wrccr_w (wb_ccr_wrccr_w),
1090 
                        .wb_ccr_setcc_g (wb_ccr_setcc_g),
1091 
                        .divcntl_ccr_cc_w2(divcntl_ccr_cc_w2[7:0]),
1092 
                        .tlu_exu_cwpccr_update_m(tlu_exu_cwpccr_update_m),
1093 
                        .tlu_exu_ccr_m  (tlu_exu_ccr_m[7:0]),
1094 
                        .ifu_exu_inst_vld_w(ifu_exu_inst_vld_w),
1095 
                        .ifu_tlu_flush_w(ifu_tlu_flush_w),
1096 
                        .early_flush_w  (early_flush_w));
1097 
 
1098 
   // Writeback control logic
1099 
   sparc_exu_ecl_wb writeback(
1100 
                              .read_yreg_e(read_yreg_e),
1101 
                              /*AUTOINST*/
1102 
                              // Outputs
1103 
                              .wb_ccr_wrccr_w(wb_ccr_wrccr_w),
1104 
                              .ecl_rml_cwp_wen_e(ecl_rml_cwp_wen_e),
1105 
                              .ecl_rml_cansave_wen_w(ecl_rml_cansave_wen_w),
1106 
                              .ecl_rml_canrestore_wen_w(ecl_rml_canrestore_wen_w),
1107 
                              .ecl_rml_otherwin_wen_w(ecl_rml_otherwin_wen_w),
1108 
                              .ecl_rml_wstate_wen_w(ecl_rml_wstate_wen_w),
1109 
                              .ecl_rml_cleanwin_wen_w(ecl_rml_cleanwin_wen_w),
1110 
                              .ecl_byp_sel_load_m(ecl_byp_sel_load_m),
1111 
                              .ecl_byp_sel_restore_m(ecl_byp_sel_restore_m),
1112 
                              .ecl_byp_sel_pipe_m(ecl_byp_sel_pipe_m),
1113 
                              .ecl_byp_restore_m(ecl_byp_restore_m),
1114 
                              .ecl_irf_tid_m(ecl_irf_tid_m[1:0]),
1115 
                              .ecl_irf_rd_m(ecl_irf_rd_m[4:0]),
1116 
                              .ecl_irf_rd_g(ecl_irf_rd_g[4:0]),
1117 
                              .ecl_irf_wen_w2(ecl_irf_wen_w2),
1118 
                              .ecl_irf_tid_g(ecl_irf_tid_g[1:0]),
1119 
                              .wb_e     (wb_e),
1120 
                              .bypass_m (bypass_m),
1121 
                              .ecl_irf_wen_w(ecl_irf_wen_w),
1122 
                              .ecl_byp_sel_load_g(ecl_byp_sel_load_g),
1123 
                              .ecl_byp_sel_muldiv_g(ecl_byp_sel_muldiv_g),
1124 
                              .ecl_byp_sel_restore_g(ecl_byp_sel_restore_g),
1125 
                              .wb_divcntl_ack_g(wb_divcntl_ack_g),
1126 
                              .wb_ccr_setcc_g(wb_ccr_setcc_g),
1127 
                              .ecl_byp_eclpr_e(ecl_byp_eclpr_e[7:0]),
1128 
                              .exu_ifu_longop_done_g(exu_ifu_longop_done_g[3:0]),
1129 
                              .ecl_div_yreg_wen_w(ecl_div_yreg_wen_w[3:0]),
1130 
                              .ecl_div_yreg_wen_g(ecl_div_yreg_wen_g[3:0]),
1131 
                              .ecl_div_yreg_shift_g(ecl_div_yreg_shift_g[3:0]),
1132 
                              .ecl_div_yreg_wen_l(ecl_div_yreg_wen_l[3:0]),
1133 
                              .wb_eccctl_spec_wen_next(wb_eccctl_spec_wen_next),
1134 
                              .bypass_w (bypass_w),
1135 
                              .wb_byplog_rd_w2(wb_byplog_rd_w2[4:0]),
1136 
                              .wb_byplog_tid_w2(wb_byplog_tid_w2[1:0]),
1137 
                              .wb_byplog_wen_w2(wb_byplog_wen_w2),
1138 
                              .wb_byplog_rd_g2(wb_byplog_rd_g2[4:0]),
1139 
                              .wb_byplog_wen_g2(wb_byplog_wen_g2),
1140 
                              .exu_ffu_wsr_inst_e(exu_ffu_wsr_inst_e),
1141 
                              // Inputs
1142 
                              .clk      (clk),
1143 
                              .se       (se),
1144 
                              .reset    (reset),
1145 
                              .sehold   (sehold),
1146 
                              .ld_rd_g  (ld_rd_g[4:0]),
1147 
                              .ld_tid_g (ld_tid_g[1:0]),
1148 
                              .lsu_exu_dfill_vld_g(lsu_exu_dfill_vld_g),
1149 
                              .lsu_exu_ldst_miss_g2(lsu_exu_ldst_miss_g2),
1150 
                              .rd_m     (rd_m[4:0]),
1151 
                              .tid_m    (tid_m[1:0]),
1152 
                              .thr_m    (thr_m[3:0]),
1153 
                              .tid_w1   (tid_w1[1:0]),
1154 
                              .ifu_exu_wen_d(ifu_exu_wen_d),
1155 
                              .ifu_exu_kill_e(ifu_exu_kill_e),
1156 
                              .ecl_exu_kill_m(ecl_exu_kill_m),
1157 
                              .rml_ecl_kill_m(rml_ecl_kill_m),
1158 
                              .ifu_tlu_flush_w(ifu_tlu_flush_w),
1159 
                              .flush_w1 (flush_w1),
1160 
                              .divcntl_wb_req_g(divcntl_wb_req_g),
1161 
                              .mdqctl_wb_divrd_g(mdqctl_wb_divrd_g[4:0]),
1162 
                              .mdqctl_wb_divthr_g(mdqctl_wb_divthr_g[1:0]),
1163 
                              .mdqctl_wb_mulrd_g(mdqctl_wb_mulrd_g[4:0]),
1164 
                              .mdqctl_wb_multhr_g(mdqctl_wb_multhr_g[1:0]),
1165 
                              .mdqctl_wb_divsetcc_g(mdqctl_wb_divsetcc_g),
1166 
                              .mdqctl_wb_mulsetcc_g(mdqctl_wb_mulsetcc_g),
1167 
                              .ecl_div_sel_div(ecl_div_sel_div),
1168 
                              .ifu_tlu_wsr_inst_d(ifu_tlu_wsr_inst_d),
1169 
                              .ifu_tlu_sraddr_d(ifu_tlu_sraddr_d[6:0]),
1170 
                              .rml_ecl_cwp_d(rml_ecl_cwp_d[2:0]),
1171 
                              .rml_ecl_cansave_d(rml_ecl_cansave_d[2:0]),
1172 
                              .rml_ecl_canrestore_d(rml_ecl_canrestore_d[2:0]),
1173 
                              .rml_ecl_otherwin_d(rml_ecl_otherwin_d[2:0]),
1174 
                              .rml_ecl_wstate_d(rml_ecl_wstate_d[5:0]),
1175 
                              .rml_ecl_cleanwin_d(rml_ecl_cleanwin_d[2:0]),
1176 
                              .exu_ifu_cc_d(exu_ifu_cc_d[7:0]),
1177 
                              .rml_ecl_swap_done(rml_ecl_swap_done[3:0]),
1178 
                              .rml_ecl_rmlop_done_e(rml_ecl_rmlop_done_e),
1179 
                              .mdqctl_wb_yreg_wen_g(mdqctl_wb_yreg_wen_g),
1180 
                              .mdqctl_wb_yreg_shift_g(mdqctl_wb_yreg_shift_g),
1181 
                              .ecl_byp_sel_ecc_m(ecl_byp_sel_ecc_m),
1182 
                              .eccctl_wb_rd_m(eccctl_wb_rd_m[4:0]),
1183 
                              .ifu_exu_inst_vld_e(ifu_exu_inst_vld_e),
1184 
                              .ifu_exu_inst_vld_w(ifu_exu_inst_vld_w),
1185 
                              .ifu_exu_return_d(ifu_exu_return_d),
1186 
                              .restore_e(restore_e),
1187 
                              .rml_ecl_fill_e(rml_ecl_fill_e),
1188 
                              .early_flush_w(early_flush_w),
1189 
                              .ecl_byp_ldxa_g(ecl_byp_ldxa_g));
1190 
 
1191 
   ////////////////////////
1192 
   // ECC control logic
1193 
   ////////////////////////
1194 
   sparc_exu_ecl_eccctl eccctl(
1195 
                               .ue_trap_m(ue_trap_m),
1196 
                               /*AUTOINST*/
1197 
                               // Outputs
1198 
                               .ecl_ecc_sel_rs1_m_l(ecl_ecc_sel_rs1_m_l),
1199 
                               .ecl_ecc_sel_rs2_m_l(ecl_ecc_sel_rs2_m_l),
1200 
                               .ecl_ecc_sel_rs3_m_l(ecl_ecc_sel_rs3_m_l),
1201 
                               .ecl_ecc_log_rs1_m(ecl_ecc_log_rs1_m),
1202 
                               .ecl_ecc_log_rs2_m(ecl_ecc_log_rs2_m),
1203 
                               .ecl_ecc_log_rs3_m(ecl_ecc_log_rs3_m),
1204 
                               .ecl_byp_sel_ecc_m(ecl_byp_sel_ecc_m),
1205 
                               .ecl_ecc_rs1_use_rf_e(ecl_ecc_rs1_use_rf_e),
1206 
                               .ecl_ecc_rs2_use_rf_e(ecl_ecc_rs2_use_rf_e),
1207 
                               .ecl_ecc_rs3_use_rf_e(ecl_ecc_rs3_use_rf_e),
1208 
                               .eccctl_wb_rd_m(eccctl_wb_rd_m[4:0]),
1209 
                               .exu_ifu_ecc_ce_m(exu_ifu_ecc_ce_m),
1210 
                               .exu_ifu_ecc_ue_m(exu_ifu_ecc_ue_m),
1211 
                               .exu_ifu_err_reg_m(exu_ifu_err_reg_m[7:0]),
1212 
                               .ecl_byp_ecc_mask_m_l(ecl_byp_ecc_mask_m_l[7:0]),
1213 
                               .exu_ifu_inj_ack(exu_ifu_inj_ack),
1214 
                               .exu_ifu_err_synd_7_m(exu_ifu_err_synd_7_m),
1215 
                               // Inputs
1216 
                               .clk     (clk),
1217 
                               .se      (se),
1218 
                               .rst_tri_en(rst_tri_en),
1219 
                               .ecc_ecl_rs1_ce(ecc_ecl_rs1_ce),
1220 
                               .ecc_ecl_rs1_ue(ecc_ecl_rs1_ue),
1221 
                               .ecc_ecl_rs2_ce(ecc_ecl_rs2_ce),
1222 
                               .ecc_ecl_rs2_ue(ecc_ecl_rs2_ue),
1223 
                               .ecc_ecl_rs3_ce(ecc_ecl_rs3_ce),
1224 
                               .ecc_ecl_rs3_ue(ecc_ecl_rs3_ue),
1225 
                               .ecl_byp_rcc_mux2_sel_rf(ecl_byp_rcc_mux2_sel_rf),
1226 
                               .ecl_byp_rs2_mux2_sel_rf(ecl_byp_rs2_mux2_sel_rf),
1227 
                               .ecl_byp_rs3_mux2_sel_rf(ecl_byp_rs3_mux2_sel_rf),
1228 
                               .rs1_vld_e(rs1_vld_e),
1229 
                               .rs2_vld_e(rs2_vld_e),
1230 
                               .rs3_vld_e(rs3_vld_e),
1231 
                               .ifu_exu_rs1_m(ifu_exu_rs1_m[4:0]),
1232 
                               .ifu_exu_rs2_m(ifu_exu_rs2_m[4:0]),
1233 
                               .ifu_exu_rs3_m(ifu_exu_rs3_m[4:0]),
1234 
                               .rml_ecl_cwp_d(rml_ecl_cwp_d[2:0]),
1235 
                               .ifu_exu_ecc_mask(ifu_exu_ecc_mask[7:0]),
1236 
                               .ifu_exu_inj_irferr(ifu_exu_inj_irferr),
1237 
                               .ifu_exu_disable_ce_e(ifu_exu_disable_ce_e),
1238 
                               .wb_eccctl_spec_wen_next(wb_eccctl_spec_wen_next),
1239 
                               .ifu_exu_nceen_e(ifu_exu_nceen_e),
1240 
                               .ifu_exu_inst_vld_e(ifu_exu_inst_vld_e),
1241 
                               .rml_ecl_gl_e(rml_ecl_gl_e[1:0]),
1242 
                               .cancel_rs3_ecc_e(cancel_rs3_ecc_e));
1243 
   // Bypass logic
1244 
   // Precalculate some of the matching logic to help timing
1245 
   assign thr_match_sd =  ~((ifu_exu_tid_s2[1] ^ tid_d[1]) |
1246 
                           (ifu_exu_tid_s2[0] ^ tid_d[0]));
1247 
   dff_s thr_match_sd_dff(.din(thr_match_sd), .clk(clk), .q(thr_match_de),
1248 
                        .se(se), .si(), .so());
1249 
   assign thr_match_se =  ~((ifu_exu_tid_s2[1] ^ tid_e[1]) |
1250 
                           (ifu_exu_tid_s2[0] ^ tid_e[0]));
1251 
   dff_s thr_match_se_dff(.din(thr_match_se), .clk(clk), .q(thr_match_dm),
1252 
                        .se(se), .si(), .so());
1253 
   assign ld_thr_match_sm = ~((ifu_exu_tid_s2[1] ^ lsu_exu_thr_m[1]) |
1254 
                           (ifu_exu_tid_s2[0] ^ lsu_exu_thr_m[0]));
1255 
   dff_s ld_thr_match_sm_dff(.din(ld_thr_match_sm), .clk(clk), .q(ld_thr_match_dg), .se(se),
1256 
                           .si(), .so());
1257 
   assign ld_thr_match_sg = ~((ifu_exu_tid_s2[1] ^ ld_tid_g[1]) |
1258 
                           (ifu_exu_tid_s2[0] ^ ld_tid_g[0]));
1259 
   dff_s ld_thr_match_sg_dff(.din(ld_thr_match_sg), .clk(clk), .q(ld_thr_match_dg2), .se(se),
1260 
                           .si(), .so());
1261 
   sparc_exu_eclbyplog_rs1 byplog_rs1(.rs_sel_mux1_m(ecl_byp_rs1_mux1_sel_m),
1262 
                                  .rs_sel_mux1_w(ecl_byp_rs1_mux1_sel_w),
1263 
                                  .rs_sel_mux1_w2(ecl_byp_rs1_mux1_sel_w2),
1264 
                                  .rs_sel_mux1_other(ecl_byp_rs1_mux1_sel_other),
1265 
                                  .rs_sel_mux2_e(ecl_byp_rs1_mux2_sel_e),
1266 
                                  .rs_sel_mux2_rf(ecl_byp_rs1_mux2_sel_rf),
1267 
                                  .rs_sel_mux2_ld(ecl_byp_rs1_mux2_sel_ld),
1268 
                                  .rs_sel_mux2_usemux1(ecl_byp_rs1_mux2_sel_usemux1),
1269 
                                  .rs_sel_longmux_g2(ecl_byp_rs1_longmux_sel_g2),
1270 
                                  .rs_sel_longmux_w2(ecl_byp_rs1_longmux_sel_w2),
1271 
                                  .rs_sel_longmux_ldxa(ecl_byp_rs1_longmux_sel_ldxa),
1272 
                                  .rs   (ifu_exu_rs1_d[4:0]),
1273 
                                  .use_other(ifu_exu_dbrinst_d),
1274 
                                  /*AUTOINST*/
1275 
                                      // Outputs
1276 
                                      .ecl_byp_rcc_mux1_sel_m(ecl_byp_rcc_mux1_sel_m),
1277 
                                      .ecl_byp_rcc_mux1_sel_w(ecl_byp_rcc_mux1_sel_w),
1278 
                                      .ecl_byp_rcc_mux1_sel_w2(ecl_byp_rcc_mux1_sel_w2),
1279 
                                      .ecl_byp_rcc_mux1_sel_other(ecl_byp_rcc_mux1_sel_other),
1280 
                                      .ecl_byp_rcc_mux2_sel_usemux1(ecl_byp_rcc_mux2_sel_usemux1),
1281 
                                      .ecl_byp_rcc_mux2_sel_rf(ecl_byp_rcc_mux2_sel_rf),
1282 
                                      .ecl_byp_rcc_mux2_sel_e(ecl_byp_rcc_mux2_sel_e),
1283 
                                      .ecl_byp_rcc_mux2_sel_ld(ecl_byp_rcc_mux2_sel_ld),
1284 
                                      // Inputs
1285 
                                      .sehold(sehold),
1286 
                                      .rd_e(rd_e[4:0]),
1287 
                                      .rd_m(rd_m[4:0]),
1288 
                                      .ecl_irf_rd_w(ecl_irf_rd_w[4:0]),
1289 
                                      .ld_rd_g(ld_rd_g[4:0]),
1290 
                                      .wb_byplog_rd_w2(wb_byplog_rd_w2[4:0]),
1291 
                                      .wb_byplog_rd_g2(wb_byplog_rd_g2[4:0]),
1292 
                                      .tid_d(tid_d[1:0]),
1293 
                                      .thr_match_de(thr_match_de),
1294 
                                      .thr_match_dm(thr_match_dm),
1295 
                                      .ecl_irf_tid_w(ecl_irf_tid_w[1:0]),
1296 
                                      .ld_thr_match_dg(ld_thr_match_dg),
1297 
                                      .wb_byplog_tid_w2(wb_byplog_tid_w2[1:0]),
1298 
                                      .ld_thr_match_dg2(ld_thr_match_dg2),
1299 
                                      .ifu_exu_kill_e(ifu_exu_kill_e),
1300 
                                      .wb_e(wb_e),
1301 
                                      .bypass_m(bypass_m),
1302 
                                      .lsu_exu_dfill_vld_g(lsu_exu_dfill_vld_g),
1303 
                                      .bypass_w(bypass_w),
1304 
                                      .wb_byplog_wen_w2(wb_byplog_wen_w2),
1305 
                                      .wb_byplog_wen_g2(wb_byplog_wen_g2),
1306 
                                      .ecl_byp_ldxa_g(ecl_byp_ldxa_g));
1307 
 
1308 
   sparc_exu_eclbyplog byplog_rs2(.rs_sel_mux1_m(ecl_byp_rs2_mux1_sel_m),
1309 
                                  .rs_sel_mux1_w(ecl_byp_rs2_mux1_sel_w),
1310 
                                  .rs_sel_mux1_w2(ecl_byp_rs2_mux1_sel_w2),
1311 
                                  .rs_sel_mux1_other(ecl_byp_rs2_mux1_sel_other),
1312 
                                  .rs_sel_mux2_e(ecl_byp_rs2_mux2_sel_e),
1313 
                                  .rs_sel_mux2_rf(ecl_byp_rs2_mux2_sel_rf),
1314 
                                  .rs_sel_mux2_ld(ecl_byp_rs2_mux2_sel_ld),
1315 
                                  .rs_sel_mux2_usemux1(ecl_byp_rs2_mux2_sel_usemux1),
1316 
                                  .rs_sel_longmux_g2(ecl_byp_rs2_longmux_sel_g2),
1317 
                                  .rs_sel_longmux_w2(ecl_byp_rs2_longmux_sel_w2),
1318 
                                  .rs_sel_longmux_ldxa(ecl_byp_rs2_longmux_sel_ldxa),
1319 
                                  .rs   (ifu_exu_rs2_d[4:0]),
1320 
                                  .use_other(ifu_exu_useimm_d),
1321 
                                  /*AUTOINST*/
1322 
                                  // Inputs
1323 
                                  .sehold(sehold),
1324 
                                  .rd_e (rd_e[4:0]),
1325 
                                  .rd_m (rd_m[4:0]),
1326 
                                  .ecl_irf_rd_w(ecl_irf_rd_w[4:0]),
1327 
                                  .ld_rd_g(ld_rd_g[4:0]),
1328 
                                  .wb_byplog_rd_w2(wb_byplog_rd_w2[4:0]),
1329 
                                  .wb_byplog_rd_g2(wb_byplog_rd_g2[4:0]),
1330 
                                  .tid_d(tid_d[1:0]),
1331 
                                  .thr_match_de(thr_match_de),
1332 
                                  .thr_match_dm(thr_match_dm),
1333 
                                  .ecl_irf_tid_w(ecl_irf_tid_w[1:0]),
1334 
                                  .ld_thr_match_dg(ld_thr_match_dg),
1335 
                                  .wb_byplog_tid_w2(wb_byplog_tid_w2[1:0]),
1336 
                                  .ld_thr_match_dg2(ld_thr_match_dg2),
1337 
                                  .ifu_exu_kill_e(ifu_exu_kill_e),
1338 
                                  .wb_e (wb_e),
1339 
                                  .bypass_m(bypass_m),
1340 
                                  .lsu_exu_dfill_vld_g(lsu_exu_dfill_vld_g),
1341 
                                  .bypass_w(bypass_w),
1342 
                                  .wb_byplog_wen_w2(wb_byplog_wen_w2),
1343 
                                  .wb_byplog_wen_g2(wb_byplog_wen_g2),
1344 
                                  .ecl_byp_ldxa_g(ecl_byp_ldxa_g));
1345 
   sparc_exu_eclbyplog byplog_rs3(.rs_sel_mux1_m(ecl_byp_rs3_mux1_sel_m),
1346 
                                  .rs_sel_mux1_w(ecl_byp_rs3_mux1_sel_w),
1347 
                                  .rs_sel_mux1_w2(ecl_byp_rs3_mux1_sel_w2),
1348 
                                  .rs_sel_mux1_other(ecl_byp_rs3_mux1_sel_other),
1349 
                                  .rs_sel_mux2_e(ecl_byp_rs3_mux2_sel_e),
1350 
                                  .rs_sel_mux2_rf(ecl_byp_rs3_mux2_sel_rf),
1351 
                                  .rs_sel_mux2_ld(ecl_byp_rs3_mux2_sel_ld),
1352 
                                  .rs_sel_mux2_usemux1(ecl_byp_rs3_mux2_sel_usemux1),
1353 
                                  .rs_sel_longmux_g2(ecl_byp_rs3_longmux_sel_g2),
1354 
                                  .rs_sel_longmux_w2(ecl_byp_rs3_longmux_sel_w2),
1355 
                                  .rs_sel_longmux_ldxa(ecl_byp_rs3_longmux_sel_ldxa),
1356 
                                  .rs   ({ifu_exu_rs3_d[4:0]}),
1357 
                                  .use_other(1'b0),
1358 
                                  /*AUTOINST*/
1359 
                                  // Inputs
1360 
                                  .sehold(sehold),
1361 
                                  .rd_e (rd_e[4:0]),
1362 
                                  .rd_m (rd_m[4:0]),
1363 
                                  .ecl_irf_rd_w(ecl_irf_rd_w[4:0]),
1364 
                                  .ld_rd_g(ld_rd_g[4:0]),
1365 
                                  .wb_byplog_rd_w2(wb_byplog_rd_w2[4:0]),
1366 
                                  .wb_byplog_rd_g2(wb_byplog_rd_g2[4:0]),
1367 
                                  .tid_d(tid_d[1:0]),
1368 
                                  .thr_match_de(thr_match_de),
1369 
                                  .thr_match_dm(thr_match_dm),
1370 
                                  .ecl_irf_tid_w(ecl_irf_tid_w[1:0]),
1371 
                                  .ld_thr_match_dg(ld_thr_match_dg),
1372 
                                  .wb_byplog_tid_w2(wb_byplog_tid_w2[1:0]),
1373 
                                  .ld_thr_match_dg2(ld_thr_match_dg2),
1374 
                                  .ifu_exu_kill_e(ifu_exu_kill_e),
1375 
                                  .wb_e (wb_e),
1376 
                                  .bypass_m(bypass_m),
1377 
                                  .lsu_exu_dfill_vld_g(lsu_exu_dfill_vld_g),
1378 
                                  .bypass_w(bypass_w),
1379 
                                  .wb_byplog_wen_w2(wb_byplog_wen_w2),
1380 
                                  .wb_byplog_wen_g2(wb_byplog_wen_g2),
1381 
                                  .ecl_byp_ldxa_g(ecl_byp_ldxa_g));
1382 
   sparc_exu_eclbyplog byplog_rs3h(.rs_sel_mux1_m(ecl_byp_rs3h_mux1_sel_m),
1383 
                                  .rs_sel_mux1_w(ecl_byp_rs3h_mux1_sel_w),
1384 
                                  .rs_sel_mux1_w2(ecl_byp_rs3h_mux1_sel_w2),
1385 
                                  .rs_sel_mux1_other(ecl_byp_rs3h_mux1_sel_other),
1386 
                                  .rs_sel_mux2_e(ecl_byp_rs3h_mux2_sel_e),
1387 
                                  .rs_sel_mux2_rf(ecl_byp_rs3h_mux2_sel_rf),
1388 
                                  .rs_sel_mux2_ld(ecl_byp_rs3h_mux2_sel_ld),
1389 
                                  .rs_sel_mux2_usemux1(ecl_byp_rs3h_mux2_sel_usemux1),
1390 
                                  .rs_sel_longmux_g2(ecl_byp_rs3h_longmux_sel_g2),
1391 
                                  .rs_sel_longmux_w2(ecl_byp_rs3h_longmux_sel_w2),
1392 
                                  .rs_sel_longmux_ldxa(ecl_byp_rs3h_longmux_sel_ldxa),
1393 
                                  .rs   ({ifu_exu_rs3_d[4:1],1'b1}),
1394 
                                  .use_other(1'b0),
1395 
                                  /*AUTOINST*/
1396 
                                   // Inputs
1397 
                                   .sehold(sehold),
1398 
                                   .rd_e(rd_e[4:0]),
1399 
                                   .rd_m(rd_m[4:0]),
1400 
                                   .ecl_irf_rd_w(ecl_irf_rd_w[4:0]),
1401 
                                   .ld_rd_g(ld_rd_g[4:0]),
1402 
                                   .wb_byplog_rd_w2(wb_byplog_rd_w2[4:0]),
1403 
                                   .wb_byplog_rd_g2(wb_byplog_rd_g2[4:0]),
1404 
                                   .tid_d(tid_d[1:0]),
1405 
                                   .thr_match_de(thr_match_de),
1406 
                                   .thr_match_dm(thr_match_dm),
1407 
                                   .ecl_irf_tid_w(ecl_irf_tid_w[1:0]),
1408 
                                   .ld_thr_match_dg(ld_thr_match_dg),
1409 
                                   .wb_byplog_tid_w2(wb_byplog_tid_w2[1:0]),
1410 
                                   .ld_thr_match_dg2(ld_thr_match_dg2),
1411 
                                   .ifu_exu_kill_e(ifu_exu_kill_e),
1412 
                                   .wb_e(wb_e),
1413 
                                   .bypass_m(bypass_m),
1414 
                                   .lsu_exu_dfill_vld_g(lsu_exu_dfill_vld_g),
1415 
                                   .bypass_w(bypass_w),
1416 
                                   .wb_byplog_wen_w2(wb_byplog_wen_w2),
1417 
                                   .wb_byplog_wen_g2(wb_byplog_wen_g2),
1418 
                                   .ecl_byp_ldxa_g(ecl_byp_ldxa_g));
1419 
 
1420 
   /////////////////////////
1421 
   // Division control logic
1422 
   /////////////////////////
1423 
   sparc_exu_ecl_divcntl divcntl(
1424 
                                 .div_ecl_divisorin_31(byp_ecl_rs2_31_e),
1425 
                                 /*AUTOINST*/
1426 
                                 // Outputs
1427 
                                 .ecl_div_xinmask(ecl_div_xinmask),
1428 
                                 .ecl_div_keep_d(ecl_div_keep_d),
1429 
                                 .ecl_div_ld_inputs(ecl_div_ld_inputs),
1430 
                                 .ecl_div_sel_adder(ecl_div_sel_adder),
1431 
                                 .ecl_div_last_cycle(ecl_div_last_cycle),
1432 
                                 .ecl_div_almostlast_cycle(ecl_div_almostlast_cycle),
1433 
                                 .ecl_div_sel_div(ecl_div_sel_div),
1434 
                                 .divcntl_wb_req_g(divcntl_wb_req_g),
1435 
                                 .divcntl_ccr_cc_w2(divcntl_ccr_cc_w2[7:0]),
1436 
                                 .ecl_div_sel_64b(ecl_div_sel_64b),
1437 
                                 .ecl_div_sel_u32(ecl_div_sel_u32),
1438 
                                 .ecl_div_sel_pos32(ecl_div_sel_pos32),
1439 
                                 .ecl_div_sel_neg32(ecl_div_sel_neg32),
1440 
                                 .ecl_div_upper32_zero(ecl_div_upper32_zero),
1441 
                                 .ecl_div_upper33_one(ecl_div_upper33_one),
1442 
                                 .ecl_div_upper33_zero(ecl_div_upper33_zero),
1443 
                                 .ecl_div_dividend_sign(ecl_div_dividend_sign),
1444 
                                 .ecl_div_newq(ecl_div_newq),
1445 
                                 .ecl_div_subtract_l(ecl_div_subtract_l),
1446 
                                 .ecl_div_keepx(ecl_div_keepx),
1447 
                                 .ecl_div_cin(ecl_div_cin),
1448 
                                 // Inputs
1449 
                                 .clk   (clk),
1450 
                                 .se    (se),
1451 
                                 .reset (reset),
1452 
                                 .mdqctl_divcntl_input_vld(mdqctl_divcntl_input_vld),
1453 
                                 .wb_divcntl_ack_g(wb_divcntl_ack_g),
1454 
                                 .mdqctl_divcntl_reset_div(mdqctl_divcntl_reset_div),
1455 
                                 .div_ecl_gencc_in_msb_l(div_ecl_gencc_in_msb_l),
1456 
                                 .div_ecl_gencc_in_31(div_ecl_gencc_in_31),
1457 
                                 .div_ecl_upper32_equal(div_ecl_upper32_equal),
1458 
                                 .div_ecl_low32_nonzero(div_ecl_low32_nonzero),
1459 
                                 .ecl_div_signed_div(ecl_div_signed_div),
1460 
                                 .div_ecl_dividend_msb(div_ecl_dividend_msb),
1461 
                                 .div_ecl_xin_msb_l(div_ecl_xin_msb_l),
1462 
                                 .div_ecl_x_msb(div_ecl_x_msb),
1463 
                                 .div_ecl_d_msb(div_ecl_d_msb),
1464 
                                 .div_ecl_cout64(div_ecl_cout64),
1465 
                                 .ecl_div_div64(ecl_div_div64),
1466 
                                 .mdqctl_divcntl_muldone(mdqctl_divcntl_muldone),
1467 
                                 .ecl_div_muls(ecl_div_muls),
1468 
                                 .div_ecl_adder_out_31(div_ecl_adder_out_31),
1469 
                                 .muls_rs1_31_m_l(muls_rs1_31_m_l),
1470 
                                 .div_ecl_cout32(div_ecl_cout32),
1471 
                                 .rs2_data_31_m(rs2_data_31_m),
1472 
                                 .div_ecl_detect_zero_high(div_ecl_detect_zero_high),
1473 
                                 .div_ecl_detect_zero_low(div_ecl_detect_zero_low),
1474 
                                 .div_ecl_d_62(div_ecl_d_62));
1475 
 
1476 
   assign div_e = mdqctl_divcntl_input_vld;
1477 
   sparc_exu_ecl_mdqctl mdqctl(.div_zero_m(div_zero_m),
1478 
                               .byp_alu_rs1_data_31_e(byp_ecl_rs1_31_e),
1479 
                               .byp_alu_rs2_data_31_e(byp_ecl_rs2_31_e),
1480 
                               /*AUTOINST*/
1481 
                               // Outputs
1482 
                               .mdqctl_divcntl_input_vld(mdqctl_divcntl_input_vld),
1483 
                               .mdqctl_divcntl_reset_div(mdqctl_divcntl_reset_div),
1484 
                               .mdqctl_divcntl_muldone(mdqctl_divcntl_muldone),
1485 
                               .ecl_div_div64(ecl_div_div64),
1486 
                               .ecl_div_signed_div(ecl_div_signed_div),
1487 
                               .ecl_div_muls(ecl_div_muls),
1488 
                               .mdqctl_wb_divthr_g(mdqctl_wb_divthr_g[1:0]),
1489 
                               .mdqctl_wb_divrd_g(mdqctl_wb_divrd_g[4:0]),
1490 
                               .mdqctl_wb_multhr_g(mdqctl_wb_multhr_g[1:0]),
1491 
                               .mdqctl_wb_mulrd_g(mdqctl_wb_mulrd_g[4:0]),
1492 
                               .mdqctl_wb_divsetcc_g(mdqctl_wb_divsetcc_g),
1493 
                               .mdqctl_wb_mulsetcc_g(mdqctl_wb_mulsetcc_g),
1494 
                               .mdqctl_wb_yreg_shift_g(mdqctl_wb_yreg_shift_g),
1495 
                               .exu_mul_input_vld(exu_mul_input_vld),
1496 
                               .mdqctl_wb_yreg_wen_g(mdqctl_wb_yreg_wen_g),
1497 
                               .ecl_div_mul_sext_rs1_e(ecl_div_mul_sext_rs1_e),
1498 
                               .ecl_div_mul_sext_rs2_e(ecl_div_mul_sext_rs2_e),
1499 
                               .ecl_div_mul_get_new_data(ecl_div_mul_get_new_data),
1500 
                               .ecl_div_mul_keep_data(ecl_div_mul_keep_data),
1501 
                               .ecl_div_mul_get_32bit_data(ecl_div_mul_get_32bit_data),
1502 
                               .ecl_div_mul_wen(ecl_div_mul_wen),
1503 
                               // Inputs
1504 
                               .clk     (clk),
1505 
                               .se      (se),
1506 
                               .reset   (reset),
1507 
                               .ifu_exu_muldivop_d(ifu_exu_muldivop_d[4:0]),
1508 
                               .tid_d   (tid_d[1:0]),
1509 
                               .ifu_exu_rd_d(ifu_exu_rd_d[4:0]),
1510 
                               .tid_w1  (tid_w1[1:0]),
1511 
                               .flush_w1(flush_w1),
1512 
                               .ifu_exu_inst_vld_w(ifu_exu_inst_vld_w),
1513 
                               .wb_divcntl_ack_g(wb_divcntl_ack_g),
1514 
                               .divcntl_wb_req_g(divcntl_wb_req_g),
1515 
                               .mul_exu_ack(mul_exu_ack),
1516 
                               .ecl_div_sel_div(ecl_div_sel_div),
1517 
                               .ifu_exu_muls_d(ifu_exu_muls_d),
1518 
                               .div_ecl_detect_zero_high(div_ecl_detect_zero_high),
1519 
                               .div_ecl_detect_zero_low(div_ecl_detect_zero_low),
1520 
                               .ifu_tlu_flush_w(ifu_tlu_flush_w),
1521 
                               .early_flush_w(early_flush_w));
1522 
 
1523 
endmodule // sparc_exu_ecl
1524 
 
1525 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.