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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_exu_ecl_eccctl.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: sparc_exu_ecl_eccctl
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// Description: Implements the control logic for ecc checking.
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// This includes picking which error to fix (only one fixed per instruction),
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// enabling the checks, and signalling the errors.
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*/
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module sparc_exu_ecl_eccctl (/*AUTOARG*/
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// Outputs
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ue_trap_m, ecl_ecc_sel_rs1_m_l, ecl_ecc_sel_rs2_m_l,
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ecl_ecc_sel_rs3_m_l, ecl_ecc_log_rs1_m, ecl_ecc_log_rs2_m,
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ecl_ecc_log_rs3_m, ecl_byp_sel_ecc_m, ecl_ecc_rs1_use_rf_e,
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ecl_ecc_rs2_use_rf_e, ecl_ecc_rs3_use_rf_e, eccctl_wb_rd_m,
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exu_ifu_ecc_ce_m, exu_ifu_ecc_ue_m, exu_ifu_err_reg_m,
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ecl_byp_ecc_mask_m_l, exu_ifu_inj_ack, exu_ifu_err_synd_7_m,
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// Inputs
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clk, se, rst_tri_en, ecc_ecl_rs1_ce, ecc_ecl_rs1_ue,
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ecc_ecl_rs2_ce, ecc_ecl_rs2_ue, ecc_ecl_rs3_ce, ecc_ecl_rs3_ue,
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ecl_byp_rcc_mux2_sel_rf, ecl_byp_rs2_mux2_sel_rf,
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ecl_byp_rs3_mux2_sel_rf, rs1_vld_e, rs2_vld_e, rs3_vld_e,
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ifu_exu_rs1_m, ifu_exu_rs2_m, ifu_exu_rs3_m, rml_ecl_cwp_d,
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ifu_exu_ecc_mask, ifu_exu_inj_irferr, ifu_exu_disable_ce_e,
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wb_eccctl_spec_wen_next, ifu_exu_nceen_e, ifu_exu_inst_vld_e,
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rml_ecl_gl_e, cancel_rs3_ecc_e
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) ;
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input clk;
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input se;
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input rst_tri_en;
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input ecc_ecl_rs1_ce;
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input ecc_ecl_rs1_ue;
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input ecc_ecl_rs2_ce;
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input ecc_ecl_rs2_ue;
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input ecc_ecl_rs3_ce;
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input ecc_ecl_rs3_ue;
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input ecl_byp_rcc_mux2_sel_rf;
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input ecl_byp_rs2_mux2_sel_rf;
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input ecl_byp_rs3_mux2_sel_rf;
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input rs1_vld_e;
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input rs2_vld_e;
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input rs3_vld_e;
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input [4:0] ifu_exu_rs1_m;
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input [4:0] ifu_exu_rs2_m;
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input [4:0] ifu_exu_rs3_m;
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input [2:0] rml_ecl_cwp_d;
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input [7:0] ifu_exu_ecc_mask;
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input ifu_exu_inj_irferr;
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input ifu_exu_disable_ce_e;
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input wb_eccctl_spec_wen_next;
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input ifu_exu_nceen_e;
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input ifu_exu_inst_vld_e;
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input [1:0] rml_ecl_gl_e;
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input cancel_rs3_ecc_e;
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output ue_trap_m;
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output ecl_ecc_sel_rs1_m_l;
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output ecl_ecc_sel_rs2_m_l;
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output ecl_ecc_sel_rs3_m_l;
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output ecl_ecc_log_rs1_m;
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output ecl_ecc_log_rs2_m;
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output ecl_ecc_log_rs3_m;
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output ecl_byp_sel_ecc_m;
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output ecl_ecc_rs1_use_rf_e;
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output ecl_ecc_rs2_use_rf_e;
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output ecl_ecc_rs3_use_rf_e;
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output [4:0] eccctl_wb_rd_m;
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output exu_ifu_ecc_ce_m;
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output exu_ifu_ecc_ue_m;
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output [7:0] exu_ifu_err_reg_m;
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output [7:0] ecl_byp_ecc_mask_m_l;
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output exu_ifu_inj_ack;
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output exu_ifu_err_synd_7_m;
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wire sel_rs1_e;
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wire sel_rs2_e;
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wire sel_rs3_e;
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wire sel_rs1_m;
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wire sel_rs2_m;
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wire sel_rs3_m;
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wire safe_sel_rs1_m;
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wire safe_sel_rs2_m;
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wire safe_sel_rs3_m;
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wire [2:0] cwp_e;
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wire [2:0] cwp_m;
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wire [1:0] gl_m;
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wire inj_irferr_m;
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wire inj_irferr_w;
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wire detect_ce_e;
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wire detect_ue_e;
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wire flag_ecc_ce_e;
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wire flag_ecc_ue_e;
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wire [4:0] log_rs_m;
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wire rs1_ce_m;
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wire rs1_ue_m;
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wire rs2_ce_m;
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wire rs2_ue_m;
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wire rs3_ue_m;
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wire rs1_sel_rf_e;
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wire rs2_sel_rf_e;
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wire rs3_sel_rf_e;
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wire vld_rs3_ce_e;
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wire vld_rs3_ue_e;
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// Store whether rf value was used for ecc checking
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assign ecl_ecc_rs1_use_rf_e = rs1_sel_rf_e & rs1_vld_e & ifu_exu_inst_vld_e;
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assign ecl_ecc_rs2_use_rf_e = rs2_sel_rf_e & rs2_vld_e & ifu_exu_inst_vld_e;
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assign ecl_ecc_rs3_use_rf_e = rs3_sel_rf_e & rs3_vld_e & ifu_exu_inst_vld_e;
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dff_s rs1_rf_dff(.din(ecl_byp_rcc_mux2_sel_rf), .clk(clk),
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.q(rs1_sel_rf_e), .se(se), .si(), .so());
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dff_s rs2_rf_dff(.din(ecl_byp_rs2_mux2_sel_rf), .clk(clk),
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.q(rs2_sel_rf_e), .se(se), .si(), .so());
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dff_s rs3_rf_dff(.din(ecl_byp_rs3_mux2_sel_rf), .clk(clk),
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.q(rs3_sel_rf_e), .se(se), .si(), .so());
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assign vld_rs3_ce_e = ecc_ecl_rs3_ce & ~cancel_rs3_ecc_e;
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assign vld_rs3_ue_e = ecc_ecl_rs3_ue & ~cancel_rs3_ecc_e;
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assign detect_ce_e = (ecc_ecl_rs1_ce | ecc_ecl_rs2_ce | vld_rs3_ce_e);
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assign detect_ue_e = (ecc_ecl_rs1_ue | ecc_ecl_rs2_ue | vld_rs3_ue_e);
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// Generate trap signals
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assign flag_ecc_ue_e = (detect_ue_e |
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detect_ce_e & ifu_exu_disable_ce_e); // convert ce to ue
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assign flag_ecc_ce_e = detect_ce_e & ~ifu_exu_disable_ce_e;
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// Pass along signal to fix errors
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dff_s byp_sel_ecc_e2m(.din(flag_ecc_ce_e), .clk(clk), .q(ecl_byp_sel_ecc_m),
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.se(se), .si(), .so());
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dff_s ecc_ue_e2m(.din(flag_ecc_ue_e), .clk(clk), .q(exu_ifu_ecc_ue_m),
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.se(se), .si(), .so());
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dff_s nceen_e2m(.din(ifu_exu_nceen_e), .clk(clk), .q(nceen_m), .se(se), .si(), .so());
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assign ue_trap_m = exu_ifu_ecc_ue_m & nceen_m;
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// only report ce (and replay) if no ue
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assign exu_ifu_ecc_ce_m = ecl_byp_sel_ecc_m & ~exu_ifu_ecc_ue_m;
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// if globals then report %gl. otherwise log %cwp
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assign exu_ifu_err_reg_m[7:5] = (~log_rs_m[4] & ~log_rs_m[3])? {1'b0,gl_m[1:0]}: cwp_m[2:0];
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assign exu_ifu_err_reg_m[4:0] = log_rs_m[4:0];
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// Control for mux to ecc decoder (just ce)
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assign sel_rs1_e = ecc_ecl_rs1_ce;
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assign sel_rs2_e = ~ecc_ecl_rs1_ce & ecc_ecl_rs2_ce;
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assign sel_rs3_e = ~(ecc_ecl_rs1_ce | ecc_ecl_rs2_ce);
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dff_s ecc_sel_rs1_dff(.din(sel_rs1_e), .clk(clk), .q(sel_rs1_m),
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.se(se), .si(), .so());
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dff_s ecc_sel_rs2_dff(.din(sel_rs2_e), .clk(clk), .q(sel_rs2_m),
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.se(se), .si(), .so());
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dff_s ecc_sel_rs3_dff(.din(sel_rs3_e), .clk(clk), .q(sel_rs3_m),
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.se(se), .si(), .so());
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// Make selects one hot
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assign safe_sel_rs1_m = sel_rs1_m | rst_tri_en;
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assign safe_sel_rs2_m = sel_rs2_m & ~rst_tri_en;
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assign safe_sel_rs3_m = sel_rs3_m & ~rst_tri_en;
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assign ecl_ecc_sel_rs1_m_l = ~safe_sel_rs1_m;
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assign ecl_ecc_sel_rs2_m_l = ~safe_sel_rs2_m;
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assign ecl_ecc_sel_rs3_m_l = ~safe_sel_rs3_m;
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// Mux to generate the rd for fixed value
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mux3ds #(5) ecc_rd_mux(.dout(eccctl_wb_rd_m[4:0]),
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.in0(ifu_exu_rs1_m[4:0]),
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.in1(ifu_exu_rs2_m[4:0]),
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.in2(ifu_exu_rs3_m[4:0]),
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.sel0(safe_sel_rs1_m),
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.sel1(safe_sel_rs2_m),
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.sel2(safe_sel_rs3_m));
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// Control for muxes for logging errors
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assign ecl_ecc_log_rs1_m = rs1_ue_m | (rs1_ce_m & ~rs2_ue_m & ~rs3_ue_m);
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assign ecl_ecc_log_rs2_m = (rs2_ue_m & ~rs1_ue_m) | (rs2_ce_m & ~rs1_ue_m & ~rs1_ce_m & ~rs3_ue_m);
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assign ecl_ecc_log_rs3_m = ~(ecl_ecc_log_rs1_m | ecl_ecc_log_rs2_m);
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// Mux to generate the rs for error_logging
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mux3ds #(5) ecc_rdlog_mux(.dout(log_rs_m[4:0]),
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.in0(ifu_exu_rs1_m[4:0]),
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.in1(ifu_exu_rs2_m[4:0]),
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.in2(ifu_exu_rs3_m[4:0]),
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.sel0(ecl_ecc_log_rs1_m),
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.sel1(ecl_ecc_log_rs2_m),
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.sel2(ecl_ecc_log_rs3_m));
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dff_s #(3) cwp_d2e(.din(rml_ecl_cwp_d[2:0]), .clk(clk), .q(cwp_e[2:0]),
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.se(se), .si(), .so());
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dff_s #(3) cwp_e2m(.din(cwp_e[2:0]), .clk(clk), .q(cwp_m[2:0]),
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.se(se), .si(), .so());
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dff_s #(2) gl_e2m(.din(rml_ecl_gl_e[1:0]), .clk(clk), .q(gl_m[1:0]),
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.se(se), .si(), .so());
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// Syndrome needs to know if it was really a ce or ue
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mux3ds ecc_synd7_mux(.dout(exu_ifu_err_synd_7_m),
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.in0(rs1_ce_m),
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.in1(rs2_ce_m),
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.in2(~rs3_ue_m),
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.sel0(ecl_ecc_log_rs1_m),
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.sel1(ecl_ecc_log_rs2_m),
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.sel2(ecl_ecc_log_rs3_m));
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// signals for injecting errors
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// inject error if it is enabled and a write will probably happen
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// (don't bother to check kill_w
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assign inj_irferr_m = wb_eccctl_spec_wen_next & ifu_exu_inj_irferr;
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assign ecl_byp_ecc_mask_m_l = ~(ifu_exu_ecc_mask[7:0] & {8{inj_irferr_m}});
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dff_s inj_irferr_m2w(.din(inj_irferr_m), .clk(clk), .q(inj_irferr_w),
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.se(se), .si(), .so());
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assign exu_ifu_inj_ack = inj_irferr_w;
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// Pipeline Flops
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dff_s rs1_ue_e2m(.din(ecc_ecl_rs1_ue), .clk(clk), .q(rs1_ue_m), .se(se), .si(), .so());
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dff_s rs1_ce_e2m(.din(ecc_ecl_rs1_ce), .clk(clk), .q(rs1_ce_m), .se(se), .si(), .so());
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dff_s rs2_ue_e2m(.din(ecc_ecl_rs2_ue), .clk(clk), .q(rs2_ue_m), .se(se), .si(), .so());
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dff_s rs2_ce_e2m(.din(ecc_ecl_rs2_ce), .clk(clk), .q(rs2_ce_m), .se(se), .si(), .so());
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dff_s rs3_ue_e2m(.din(vld_rs3_ue_e), .clk(clk), .q(rs3_ue_m), .se(se), .si(), .so());
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endmodule // sparc_exu_ecl_eccctl
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