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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_exu_reg.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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module sparc_exu_reg (/*AUTOARG*/
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// Outputs
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data_out,
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// Inputs
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clk, se, thr_out, wen_w, thr_w, data_in_w
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) ;
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parameter SIZE = 3;
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input clk;
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input se;
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input [3:0] thr_out;
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input wen_w;
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input [3:0] thr_w;
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input [SIZE -1:0] data_in_w;
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output [SIZE-1:0] data_out;
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wire [SIZE-1:0] data_thr0;
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wire [SIZE-1:0] data_thr1;
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wire [SIZE-1:0] data_thr2;
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wire [SIZE-1:0] data_thr3;
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wire [SIZE-1:0] data_thr0_next;
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wire [SIZE-1:0] data_thr1_next;
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wire [SIZE-1:0] data_thr2_next;
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wire [SIZE-1:0] data_thr3_next;
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wire wen_thr0_w;
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wire wen_thr1_w;
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wire wen_thr2_w;
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wire wen_thr3_w;
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//////////////////////////////////
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// Output selection for reg
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//////////////////////////////////
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`ifdef FPGA_SYN_1THREAD
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assign data_out[SIZE -1:0] = data_thr0[SIZE -1:0];
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assign wen_thr0_w = (thr_w[0] & wen_w);
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// mux between new and current value
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mux2ds #(SIZE) data_next0_mux(.dout(data_thr0_next[SIZE -1:0]),
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.in0(data_thr0[SIZE -1:0]),
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.in1(data_in_w[SIZE -1:0]),
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.sel0(~wen_thr0_w),
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.sel1(wen_thr0_w));
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dff_s #(SIZE) dff_reg_thr0(.din(data_thr0_next[SIZE -1:0]), .clk(clk), .q(data_thr0[SIZE -1:0]),
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.se(se), .si(), .so());
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`else // !`ifdef FPGA_SYN_1THREAD
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// mux between the 4 regs
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mux4ds #(SIZE) mux_data_out1(.dout(data_out[SIZE -1:0]), .sel0(thr_out[0]),
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.sel1(thr_out[1]), .sel2(thr_out[2]),
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.sel3(thr_out[3]), .in0(data_thr0[SIZE -1:0]),
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.in1(data_thr1[SIZE -1:0]), .in2(data_thr2[SIZE -1:0]),
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.in3(data_thr3[SIZE -1:0]));
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//////////////////////////////////////
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// Storage of reg
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//////////////////////////////////////
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// enable input for each thread
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assign wen_thr0_w = (thr_w[0] & wen_w);
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assign wen_thr1_w = (thr_w[1] & wen_w);
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assign wen_thr2_w = (thr_w[2] & wen_w);
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assign wen_thr3_w = (thr_w[3] & wen_w);
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// mux between new and current value
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mux2ds #(SIZE) data_next0_mux(.dout(data_thr0_next[SIZE -1:0]),
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.in0(data_thr0[SIZE -1:0]),
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.in1(data_in_w[SIZE -1:0]),
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.sel0(~wen_thr0_w),
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.sel1(wen_thr0_w));
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mux2ds #(SIZE) data_next1_mux(.dout(data_thr1_next[SIZE -1:0]),
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.in0(data_thr1[SIZE -1:0]),
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.in1(data_in_w[SIZE -1:0]),
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.sel0(~wen_thr1_w),
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.sel1(wen_thr1_w));
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mux2ds #(SIZE) data_next2_mux(.dout(data_thr2_next[SIZE -1:0]),
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.in0(data_thr2[SIZE -1:0]),
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.in1(data_in_w[SIZE -1:0]),
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.sel0(~wen_thr2_w),
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.sel1(wen_thr2_w));
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mux2ds #(SIZE) data_next3_mux(.dout(data_thr3_next[SIZE -1:0]),
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.in0(data_thr3[SIZE -1:0]),
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.in1(data_in_w[SIZE -1:0]),
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.sel0(~wen_thr3_w),
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.sel1(wen_thr3_w));
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// store new value
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dff_s #(SIZE) dff_reg_thr0(.din(data_thr0_next[SIZE -1:0]), .clk(clk), .q(data_thr0[SIZE -1:0]),
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.se(se), .si(), .so());
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dff_s #(SIZE) dff_reg_thr1(.din(data_thr1_next[SIZE -1:0]), .clk(clk), .q(data_thr1[SIZE -1:0]),
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.se(se), .si(), .so());
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dff_s #(SIZE) dff_reg_thr2(.din(data_thr2_next[SIZE -1:0]), .clk(clk), .q(data_thr2[SIZE -1:0]),
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.se(se), .si(), .so());
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dff_s #(SIZE) dff_reg_thr3(.din(data_thr3_next[SIZE -1:0]), .clk(clk), .q(data_thr3[SIZE -1:0]),
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.se(se), .si(), .so());
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`endif // !`ifdef FPGA_SYN_1THREAD
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endmodule // sparc_exu_reg
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