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[/] [sparc64soc/] [trunk/] [T1-CPU/] [ffu/] [sparc_ffu_ctl.v] - Blame information for rev 2

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
2
// 
3
// OpenSPARC T1 Processor File: sparc_ffu_ctl.v
4
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
8
// modify it under the terms of the GNU General Public
9
// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
12
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
// General Public License for more details.
15
// 
16
// You should have received a copy of the GNU General Public
17
// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
21
////////////////////////////////////////////////////////////////////////
22
/*
23
//  Module Name: sparc_ffu_ctl
24
//      Description: This is the ffu control block.
25
*/
26
 
27
`include "iop.h"
28
`define FSR_NVA   9
29
`define FSR_OFA   8
30
`define FSR_UFA   7
31
`define FSR_DZA   6
32
`define FSR_NXA   5
33
`define FSR_NVC   4
34
`define FSR_OFC   3
35
`define FSR_UFC   2
36
`define FSR_DZC   1
37
`define FSR_NXC   0
38
 
39
 
40
module sparc_ffu_ctl (/*AUTOARG*/
41
   // Outputs
42
   ffu_exu_rsr_data_mid_m, ffu_exu_rsr_data_lo_m,
43
   ffu_exu_rsr_data_hi_m, ctl_vis_subtract, ctl_vis_sel_log,
44
   ctl_vis_sel_align, ctl_vis_sel_add, ctl_vis_log_sel_xor,
45
   ctl_vis_log_sel_pass, ctl_vis_log_sel_nor, ctl_vis_log_sel_nand,
46
   ctl_vis_log_pass_rs2, ctl_vis_log_pass_rs1,
47
   ctl_vis_log_pass_const, ctl_vis_log_invert_rs2,
48
   ctl_vis_log_invert_rs1, ctl_vis_log_constant, ctl_vis_cin,
49
   ctl_vis_align_odd, ctl_vis_align6, ctl_vis_align4, ctl_vis_align2,
50
   ctl_vis_align0, ctl_vis_add32, ctl_dp_wsr_data_w2, ctl_dp_thr_e,
51
   ctl_dp_gsr_wsr_w2, so, ctl_dp_rst_l, ffu_ifu_fpop_done_w2,
52
   ffu_ifu_cc_vld_w2, ffu_ifu_cc_w2, ffu_ifu_tid_w2,
53
   ffu_ifu_stallreq, ffu_ifu_ecc_ce_w2, ffu_ifu_ecc_ue_w2,
54
   ffu_ifu_err_reg_w2, ffu_ifu_err_synd_w2, ffu_ifu_fst_ce_w,
55
   ffu_lsu_kill_fst_w, ffu_ifu_inj_ack, ffu_lsu_data,
56
   ffu_lsu_fpop_rq_vld, ffu_lsu_blk_st_va_e, ffu_lsu_blk_st_e,
57
   ffu_tlu_trap_ieee754, ffu_tlu_trap_other, ffu_tlu_trap_ue,
58
   ffu_tlu_ill_inst_m, ffu_tlu_fpu_tid, ffu_tlu_fpu_cmplt,
59
   ctl_frf_ren, ctl_frf_wen, ctl_frf_addr, ctl_dp_fp_thr,
60
   ctl_dp_fcc_w2, ctl_dp_ftt_w2, ctl_dp_exc_w2, ctl_dp_ecc_sel_frf,
61
   ctl_dp_output_sel_rs1, ctl_dp_output_sel_rs2,
62
   ctl_dp_output_sel_frf, ctl_dp_output_sel_fsr, ctl_dp_rs2_frf_read,
63
   ctl_dp_rs2_sel_vis, ctl_dp_rs2_sel_fpu_lsu, ctl_dp_rs2_keep_data,
64
   ctl_dp_rd_ecc, ctl_dp_fsr_sel_ld, ctl_dp_fsr_sel_fpu,
65
   ctl_dp_fsr_sel_old, ctl_dp_noshift64_frf, ctl_dp_shift_frf_right,
66
   ctl_dp_shift_frf_left, ctl_dp_zero_low32_frf, ctl_dp_new_rs1,
67
   ctl_dp_sign, ctl_dp_flip_fpu, ctl_dp_flip_lsu, ctl_dp_noflip_fpu,
68
   ctl_dp_noflip_lsu, ctl_frf_write_synd,
69
   // Inputs
70
   ifu_tlu_sraddr_d, exu_ffu_wsr_inst_e, exu_ffu_gsr_scale_m,
71
   exu_ffu_gsr_rnd_m, exu_ffu_gsr_mask_m, exu_ffu_gsr_align_m,
72
   dp_ctl_gsr_scale_e, dp_ctl_gsr_mask_e, rclk, si, se, grst_l,
73
   arst_l, rst_tri_en, dp_ctl_rs2_sign, cpx_vld, cpx_fcmp, cpx_req,
74
   cpx_fccval, cpx_fpexc, dp_ctl_fsr_fcc, dp_ctl_fsr_rnd,
75
   dp_ctl_fsr_tem, dp_ctl_fsr_aexc, dp_ctl_fsr_cexc,
76
   dp_ctl_synd_out_low, dp_ctl_synd_out_high, ifu_ffu_fpop1_d,
77
   ifu_ffu_fpop2_d, ifu_ffu_visop_d, ifu_ffu_fpopcode_d,
78
   ifu_ffu_frs1_d, ifu_ffu_frs2_d, ifu_ffu_frd_d, ifu_ffu_fld_d,
79
   ifu_ffu_fst_d, ifu_ffu_ldst_single_d, ifu_ffu_tid_d,
80
   ifu_ffu_fcc_num_d, ifu_ffu_mvcnd_m, ifu_ffu_inj_frferr,
81
   ifu_exu_ecc_mask, ifu_ffu_ldfsr_d, ifu_ffu_ldxfsr_d,
82
   ifu_ffu_stfsr_d, ifu_ffu_quad_op_e, ifu_tlu_inst_vld_w,
83
   lsu_ffu_flush_pipe_w, ifu_tlu_flush_w, lsu_ffu_ack,
84
   lsu_ffu_ld_vld, lsu_ffu_bld_cnt_w, dp_ctl_ld_fcc, ifu_exu_nceen_e,
85
   ifu_exu_disable_ce_e, lsu_ffu_blk_asi_e, exu_ffu_ist_e,
86
   ifu_tlu_flsh_inst_e, ifu_lsu_ld_inst_e, lsu_ffu_stb_full0,
87
   lsu_ffu_stb_full1, lsu_ffu_stb_full2, lsu_ffu_stb_full3,
88
//sotheas,8/17/04: fixed eco 6529
89
   lsu_ffu_st_dtlb_perr_g
90
//////////////////////////////
91
   ) ;
92
   /*AUTOINPUT*/
93
   // Beginning of automatic inputs (from unused autoinst inputs)
94
   input [31:0]         dp_ctl_gsr_mask_e;      // To visctl of sparc_ffu_ctl_visctl.v
95
   input [4:0]          dp_ctl_gsr_scale_e;     // To visctl of sparc_ffu_ctl_visctl.v
96
   input [2:0]          exu_ffu_gsr_align_m;    // To visctl of sparc_ffu_ctl_visctl.v
97
   input [31:0]         exu_ffu_gsr_mask_m;     // To visctl of sparc_ffu_ctl_visctl.v
98
   input [2:0]          exu_ffu_gsr_rnd_m;      // To visctl of sparc_ffu_ctl_visctl.v
99
   input [4:0]          exu_ffu_gsr_scale_m;    // To visctl of sparc_ffu_ctl_visctl.v
100
   input                exu_ffu_wsr_inst_e;     // To visctl of sparc_ffu_ctl_visctl.v
101
   input [6:0]          ifu_tlu_sraddr_d;       // To visctl of sparc_ffu_ctl_visctl.v
102
   // End of automatics
103
   input rclk;
104
   input si;
105
   input se;
106
   input grst_l;
107
   input arst_l;
108
   input rst_tri_en;
109
   input [1:0] dp_ctl_rs2_sign;
110
 
111
   input          cpx_vld;
112
   input          cpx_fcmp;
113
   input [3:0]    cpx_req;
114
   input [1:0]    cpx_fccval;
115
   input [4:0]    cpx_fpexc;
116
   input [7:0] dp_ctl_fsr_fcc;
117
   input [1:0] dp_ctl_fsr_rnd;
118
   input [4:0] dp_ctl_fsr_tem;
119
         input [4:0] dp_ctl_fsr_aexc;
120
         input [4:0] dp_ctl_fsr_cexc;
121
 
122
   input [6:0] dp_ctl_synd_out_low;   // signals for ecc errors
123
   input [6:0] dp_ctl_synd_out_high;
124
 
125
   input       ifu_ffu_fpop1_d;
126
   input       ifu_ffu_fpop2_d;
127
   input       ifu_ffu_visop_d;
128
   input [8:0] ifu_ffu_fpopcode_d;
129
   input [4:0] ifu_ffu_frs1_d;
130
   input [4:0] ifu_ffu_frs2_d;
131
   input [4:0] ifu_ffu_frd_d;
132
   input       ifu_ffu_fld_d;
133
   input       ifu_ffu_fst_d;
134
   input       ifu_ffu_ldst_single_d;
135
   input [1:0] ifu_ffu_tid_d;
136
   input [1:0] ifu_ffu_fcc_num_d;
137
   input       ifu_ffu_mvcnd_m;
138
 
139
   input       ifu_ffu_inj_frferr;
140
   input [6:0] ifu_exu_ecc_mask;
141
 
142
   input       ifu_ffu_ldfsr_d,
143
               ifu_ffu_ldxfsr_d,
144
               ifu_ffu_stfsr_d;
145
   input       ifu_ffu_quad_op_e;
146
 
147
   input       ifu_tlu_inst_vld_w;
148
   input       lsu_ffu_flush_pipe_w;
149
   input       ifu_tlu_flush_w;
150
 
151
   input        lsu_ffu_ack;
152
   input        lsu_ffu_ld_vld;
153
   input [2:0]  lsu_ffu_bld_cnt_w;
154
   input [7:0]  dp_ctl_ld_fcc;
155
 
156
   input        ifu_exu_nceen_e;// enable ecc traps
157
   input        ifu_exu_disable_ce_e; // all ce are treated as ue
158
   input        lsu_ffu_blk_asi_e;
159
   input        exu_ffu_ist_e;
160
   input        ifu_tlu_flsh_inst_e;
161
   input        ifu_lsu_ld_inst_e;
162
   input        lsu_ffu_stb_full0;
163
   input        lsu_ffu_stb_full1;
164
   input        lsu_ffu_stb_full2;
165
   input        lsu_ffu_stb_full3;
166
 
167
   input        lsu_ffu_st_dtlb_perr_g; //sotheas,8/17/04: fixed eco 6529, when asserted terminated
168
                                        //                 block store
169
 
170
   /*AUTOOUTPUT*/
171
   // Beginning of automatic outputs (from unused autoinst outputs)
172
   output [3:0]         ctl_dp_gsr_wsr_w2;      // From visctl of sparc_ffu_ctl_visctl.v
173
   output [3:0]         ctl_dp_thr_e;           // From visctl of sparc_ffu_ctl_visctl.v
174
   output [36:0]        ctl_dp_wsr_data_w2;     // From visctl of sparc_ffu_ctl_visctl.v
175
   output               ctl_vis_add32;          // From visctl of sparc_ffu_ctl_visctl.v
176
   output               ctl_vis_align0;         // From visctl of sparc_ffu_ctl_visctl.v
177
   output               ctl_vis_align2;         // From visctl of sparc_ffu_ctl_visctl.v
178
   output               ctl_vis_align4;         // From visctl of sparc_ffu_ctl_visctl.v
179
   output               ctl_vis_align6;         // From visctl of sparc_ffu_ctl_visctl.v
180
   output               ctl_vis_align_odd;      // From visctl of sparc_ffu_ctl_visctl.v
181
   output               ctl_vis_cin;            // From visctl of sparc_ffu_ctl_visctl.v
182
   output               ctl_vis_log_constant;   // From visctl of sparc_ffu_ctl_visctl.v
183
   output               ctl_vis_log_invert_rs1; // From visctl of sparc_ffu_ctl_visctl.v
184
   output               ctl_vis_log_invert_rs2; // From visctl of sparc_ffu_ctl_visctl.v
185
   output               ctl_vis_log_pass_const; // From visctl of sparc_ffu_ctl_visctl.v
186
   output               ctl_vis_log_pass_rs1;   // From visctl of sparc_ffu_ctl_visctl.v
187
   output               ctl_vis_log_pass_rs2;   // From visctl of sparc_ffu_ctl_visctl.v
188
   output               ctl_vis_log_sel_nand;   // From visctl of sparc_ffu_ctl_visctl.v
189
   output               ctl_vis_log_sel_nor;    // From visctl of sparc_ffu_ctl_visctl.v
190
   output               ctl_vis_log_sel_pass;   // From visctl of sparc_ffu_ctl_visctl.v
191
   output               ctl_vis_log_sel_xor;    // From visctl of sparc_ffu_ctl_visctl.v
192
   output               ctl_vis_sel_add;        // From visctl of sparc_ffu_ctl_visctl.v
193
   output               ctl_vis_sel_align;      // From visctl of sparc_ffu_ctl_visctl.v
194
   output               ctl_vis_sel_log;        // From visctl of sparc_ffu_ctl_visctl.v
195
   output               ctl_vis_subtract;       // From visctl of sparc_ffu_ctl_visctl.v
196
   output [31:0]        ffu_exu_rsr_data_hi_m;  // From visctl of sparc_ffu_ctl_visctl.v
197
   output [7:0]         ffu_exu_rsr_data_lo_m;  // From visctl of sparc_ffu_ctl_visctl.v
198
   output [2:0]         ffu_exu_rsr_data_mid_m; // From visctl of sparc_ffu_ctl_visctl.v
199
   // End of automatics
200
   output               so;
201
   output               ctl_dp_rst_l;
202
   output       ffu_ifu_fpop_done_w2;
203
   output [3:0] ffu_ifu_cc_vld_w2;// one hot valid for each set of fcc
204
   output [7:0] ffu_ifu_cc_w2;// all 4 sets of fcc
205
   output [1:0] ffu_ifu_tid_w2;
206
   output       ffu_ifu_stallreq; // stall pipe so blk st can issue
207
 
208
   output       ffu_ifu_ecc_ce_w2;  // correctable ecc error
209
   output       ffu_ifu_ecc_ue_w2;  // uncorrectable ecc error
210
   output [5:0] ffu_ifu_err_reg_w2;
211
   output [13:0] ffu_ifu_err_synd_w2;
212
   output       ffu_ifu_fst_ce_w;
213
   output       ffu_lsu_kill_fst_w;
214
   output       ffu_ifu_inj_ack;
215
 
216
   output [80:64] ffu_lsu_data;
217
   output         ffu_lsu_fpop_rq_vld ;   // ffu dispatches fpop issue request.
218
   output [5:3]  ffu_lsu_blk_st_va_e;
219
   output        ffu_lsu_blk_st_e;
220
 
221
   output         ffu_tlu_trap_ieee754;
222
   output         ffu_tlu_trap_other;
223
   output     ffu_tlu_trap_ue;
224
   output     ffu_tlu_ill_inst_m;
225
 
226
   output [1:0] ffu_tlu_fpu_tid;
227
   output       ffu_tlu_fpu_cmplt;
228
 
229
   output       ctl_frf_ren;
230
   output [1:0] ctl_frf_wen;
231
   output [6:0] ctl_frf_addr;
232
 
233
   output [3:0] ctl_dp_fp_thr;
234
 
235
   output [7:0] ctl_dp_fcc_w2;
236
   output [2:0] ctl_dp_ftt_w2;
237
   output [9:0] ctl_dp_exc_w2;
238
 
239
   output ctl_dp_ecc_sel_frf;
240
 
241
 
242
   // mux selects
243
   output       ctl_dp_output_sel_rs1;
244
   output       ctl_dp_output_sel_rs2;
245
   output       ctl_dp_output_sel_frf;
246
   output       ctl_dp_output_sel_fsr;
247
 
248
   output       ctl_dp_rs2_frf_read;
249
   output       ctl_dp_rs2_sel_vis;
250
   output       ctl_dp_rs2_sel_fpu_lsu;
251
   output       ctl_dp_rs2_keep_data;
252
   output   ctl_dp_rd_ecc;
253
 
254
   output [3:0] ctl_dp_fsr_sel_ld,
255
                ctl_dp_fsr_sel_fpu,
256
                ctl_dp_fsr_sel_old;
257
 
258
   output       ctl_dp_noshift64_frf;
259
   output       ctl_dp_shift_frf_right;
260
   output       ctl_dp_shift_frf_left;
261
   output       ctl_dp_zero_low32_frf;
262
 
263
   output ctl_dp_new_rs1;
264
 
265
   output [1:0] ctl_dp_sign;
266
 
267
   output       ctl_dp_flip_fpu;
268
   output       ctl_dp_flip_lsu;
269
   output       ctl_dp_noflip_fpu;
270
   output       ctl_dp_noflip_lsu;
271
 
272
 
273
   wire     clk;
274
   wire     reset;
275
   wire     ffu_reset_l;
276
   // FPOP is broken into parts:
277
   // [8:4] fpop_high
278
   // [3:2] fpop_mid
279
   // [1:0] fpop_size
280
   wire         fpop_size_0;    // 2 lsbs of fpop
281
   wire         fpop_size_1;
282
 
283
   wire         fpop_high_0;    // 4 msbs of fpop
284
   wire         fpop_high_2;
285
   wire         fpop_high_4;
286
   wire         fpop_high_5;
287
   wire         fpop_high_6;
288
   wire         fpop_high_8;
289
   wire         fpop_high_a;
290
   wire         fpop_high_c;
291
   wire         fpop_high_d;
292
   wire         fpop_high_e;
293
   wire         fpop_high_10;
294
   wire         fpop_high_18;
295
   wire    fpop_low_1;
296
   wire    fpop_low_2;
297
   wire    fpop_low_4;
298
   wire    fpop_low_5;
299
   wire    fpop_low_6;
300
   wire    fpop_low_8;
301
   wire    fpop_low_9;
302
   wire    fpop_low_a;
303
   wire    fpop_low_d;
304
   wire    fpop_low_e;
305
 
306
   wire         source_single_e;
307
   wire         source_single_next;
308
   wire         source_single;
309
 
310
   wire         dest_single_e;
311
   wire         dest_single_next;
312
   wire         dest_single;
313
 
314
   wire [4:0]   frs1_e;
315
   wire [5:0]   rs1_e;
316
   wire [5:0]   rs1_next;
317
   wire [5:0]   rs1;
318
   wire [4:0]   frs2_e;
319
   wire [5:0]   rs2_e;
320
   wire [4:0]   frd_e;
321
   wire         ldst_single_e;
322
   wire [5:0]   rd_e;
323
   wire [5:1]   st_rd_d;
324
   wire [5:1]   write_addr;
325
 
326
   wire [5:0]    rs2_next;
327
   wire [5:0]    rs2;
328
   wire [5:0]    rd_next;
329
   wire [5:0]    rd;
330
   wire [5:1]   blk_rd;
331
 
332
   wire         is_fpop_d;
333
   wire    shift_frf_rs2_m;
334
   wire    shift_frf_rs1_w;
335
   wire    shift_frf_right_next;
336
   wire    shift_frf_right;
337
   wire    shift_frf_left_next;
338
   wire    shift_frf_left;
339
   wire    noshift64_frf_next;
340
   wire    noshift64_frf;
341
 
342
   wire         abs_w;
343
   wire         neg_w;
344
   wire         cond_move_e;
345
   wire         cond_move_m;
346
   wire         move_e;
347
   wire         move_m;
348
   wire         move_m_valid;
349
   wire         move_w;
350
   wire   move_w_valid;
351
   wire   move_w2;
352
   wire   move_w2_vld;
353
   wire   move_wen_m;
354
   wire   move_wen_w;
355
   wire         move_wen_w2;
356
   wire         move_wen_w2_valid;
357
 
358
   wire   vis_nofrf_e;
359
   wire         ren_rs2_e;
360
   wire         ren_rs2_e_vld;
361
   wire         ren_rs2_m;
362
   wire         ren_rs2_m_vld;
363
   wire         ren_rs2_w;
364
   wire         ren_rs2_w2;
365
   wire         ren_rs2_w3;
366
   wire         ren_rs2_w4;
367
   wire         ren_rs1_e;
368
   wire         ren_rs1_m;
369
   wire         ren_rs1_w;
370
   wire         ren_rs1_w_vld;
371
   wire         ren_rs1_w2_vld;
372
   wire         ren_rs1_w2;
373
   wire         ren_rs1_w3;
374
   wire         ren_rs1_w4;
375
   wire         ren_rs1_w5;
376
   wire         read_rs1;
377
   wire         read_rs2;
378
   wire   read_rd;
379
   wire         read_bst;
380
 
381
   wire         fpu_op_e;
382
   wire         fpu_op_m;
383
   wire         fpu_op_w_vld;
384
   wire         fpu_op_w;
385
   wire         fpu_op_w2;
386
   wire         fpu_op_w2_vld;
387
   wire         fpu_op_w3;
388
   wire         fpu_op_w3_vld;
389
   wire         any_op_e;
390
   wire         any_op_m;
391
   wire         any_op_w;
392
   wire         any_op_w2;
393
   wire         any_op_m_valid;
394
   wire   visop_e;
395
   wire   visop_m;
396
   wire   visop_w_vld;
397
 
398
   wire         fld_e;
399
   wire         fld_m;
400
   wire         fst_e;
401
   wire         fst_m;
402
   wire         fst_w;
403
   wire         zero_lower_data_next;
404
 
405
   wire   fpop1_e;
406
   wire   fpop2_e;
407
   wire   fpop1_next;
408
   wire   fpop1;
409
   wire   fpop2_next;
410
   wire   fpop2;
411
   wire   visop_next;
412
   wire   visop;
413
   wire         kill_m;
414
   wire         killed_w;
415
   wire         kill_w;
416
   wire         kill_unimpl_w;
417
   wire         kill_fp;
418
   wire         kill_eccchk_w;
419
   wire   flush_w;
420
   wire   flush_w2;
421
 
422
   wire [1:0]    tid_next;
423
   wire [1:0]   tid;
424
   wire [1:0]   extra_tid;
425
   wire [8:0]    opf_next;
426
   wire [8:0]    opf;
427
   wire [5:1]   early_frf_rnum;
428
   wire [5:1]   frf_rnum;
429
   wire [1:0]   frf_tid;
430
   wire [1:0]   fpu_rnd;
431
 
432
   wire         thr_match_mw2;
433
   wire         thr_match_ww2;
434
   wire         thr_match_fpw2;
435
   wire [1:0]    tid_e,
436
                tid_m,
437
                tid_w,
438
                tid_w2;
439
 
440
   wire         fpop1_ready_w2_next;
441
   wire         fpop2_ready_w3_next;
442
   wire         fpop1_ready_w2;
443
   wire         fpop2_ready_w3;
444
   wire   issue_fpop2;
445
 
446
   wire         ldfsr,
447
                ldxfsr,
448
                stfsr_e,
449
                stfsr_w,
450
                stfsr_qual_w,
451
                ldfsr_vld,
452
                ldxfsr_vld;
453
   wire   stfsr_w2;
454
   wire   stfsr_w2_vld;
455
 
456
   wire   clear_ftt;
457
 
458
   wire [1:0]    ldfsr_next;
459
 
460
   wire         is_fpu_result;
461
 
462
   wire   output_sel_rs1_next;
463
   wire   output_sel_frf_next;
464
   wire   output_sel_fsr_next;
465
   wire   output_sel_rs2_next;
466
   wire   output_sel_rs1;
467
   wire   output_sel_frf;
468
   wire   output_sel_fsr;
469
   wire   output_sel_rs2;
470
 
471
   wire   ffu_op_done_next;
472
   wire   ffu_op_done;
473
   wire   ffu_op_done_vld;
474
   wire         external_wen_next;
475
   wire         lsu_pkt_vld;
476
   wire [1:0]    lsu_pkt_type;
477
   wire         store_ready;
478
   wire         load_pending;
479
   wire         load_pending_next;
480
   wire   blk_ld_done;
481
   wire   blk_ld_m;
482
   wire         blk_load_pending;
483
   wire         blk_load_pending_next;
484
   wire         fp_pending,
485
                fp_pending_next;
486
 
487
   wire [3:0]    fcc_num_dec;
488
   wire [1:0]    fcc_num,
489
                fcc_num_next;
490
 
491
   wire [7:0]    fpu_fcc;
492
   wire [9:0]    fp_exc_w2;
493
 
494
   wire         fcc_sel_fpu;
495
   wire         fcc_sel_ldx;
496
   wire         fcc_sel_ld;
497
   wire         fcc_sel_old;
498
   wire         cc_changed;
499
   wire         rf_wen;
500
   wire   rf_wen_next;
501
   wire   rf_ecc_gen_next;
502
   wire   rf_ecc_gen;
503
   wire   vis_wen_next;
504
   wire   vis_result;
505
 
506
   wire [4:0] fsr_tem_d1;
507
   wire       ieee_trap;
508
   wire         take_ieee_trap;
509
   wire         take_other_trap;
510
   wire [4:0]    ieee_trap_vec;
511
   wire         fpexc_nxc;
512
   wire   fpexc_ofc;
513
   wire   fpexc_ufc;
514
 
515
   wire [1:0] error_detected;
516
   wire [1:0] possible_ue;
517
   wire [1:0] ce;
518
   wire [1:0] prev_err_detected;
519
   wire [1:0] prev_poss_ue;
520
   wire       rollback_fst_m;
521
   wire       rollback_fst_w;
522
   wire       rollback_rs2_w2;
523
   wire       rollback_rs1_w3;
524
   wire       rollback_c1_next;
525
   wire   rollback_c1;
526
   wire   rollback_c1_vld;
527
   wire   rollback_c2;
528
   wire   rollback_c3;
529
   wire   rolled_back_next;
530
   wire   rolled_back;
531
   wire   chk_rs1_w2;
532
   wire         check_ecc_next;
533
   wire [1:0] chk_ecc_m;
534
   wire [1:0] chk_ecc_w;
535
   wire [1:0] chk_ecc_w2;
536
   wire [1:0] chk_ecc;
537
   wire [1:0] chk_ecc_prev;
538
   wire   disable_ce_m;
539
   wire   disable_ce_w;
540
   wire         fst_ce_w;
541
   wire         fst_ue_w;
542
   wire         fst_ce_w2;
543
   wire         fst_ue_w2;
544
   wire         rs2_ce_w2;
545
   wire         rs2_ue_w2;
546
   wire         rs2_fst_ce_w2_vld;
547
   wire         rs2_fst_ue_w2_vld;
548
   wire         rs2_fst_ce_w3;
549
   wire         rs2_fst_ue_w3;
550
   wire   rs1_ce_w3;
551
   wire         ce_w3;
552
   wire         ue_w3;
553
   wire   nceen;
554
   wire   nceen_next;
555
   wire   ue_trap_w3;
556
   wire [1:0]    previous_ce;
557
   wire         previous_ue;
558
   wire [1:0]    ecc_wen_next;
559
   wire [1:0]    ecc_wen_gen_next;
560
   wire [1:0]    ecc_wen_gen;
561
   wire [1:0]    ecc_wen;
562
   wire         inject_err_next;
563
   wire [6:0]    err_data;
564
   wire         inject_err;
565
   wire   wen_rs1_ecc;
566
   wire   wen_rs2_ecc;
567
   wire   ecc_kill_rs2_w2;
568
   wire [13:0] new_err_synd;
569
   wire [13:0] err_synd_d1;
570
   wire [13:0] err_synd_next;
571
   wire [5:0]  new_err_reg;
572
   wire [5:0]  err_reg_next;
573
   wire [5:0]  err_reg_d1;
574
   wire        log_new_err;
575
   wire   kill_st_ce_w;
576
   wire   possible_kill_st_ue_m;
577
   wire   possible_kill_st_ce_m;
578
   wire   possible_kill_st_ue_w;
579
   wire   possible_kill_st_ce_w;
580
 
581
   wire         unimpl_op_e,
582
                unimpl_op_all_e,
583
                unimpl_op_m,
584
                unimpl_op_w,
585
                unimpl_qual_w,
586
                unimpl_qual_w2,
587
                unimpl_op_w2;
588
   wire    illegal_vis_e;
589
   wire    illegal_vis_m;
590
   wire    illegal_blk_m;
591
   wire    illegal_rs1_e;
592
   wire    illegal_field_e;
593
   wire    convert_op_e;
594
 
595
   wire          cpx_vld_d1;
596
   wire          cpx_fcmp_d1;
597
   wire [3:0]    cpx_req_d1;
598
   wire [1:0]    cpx_fccval_d1;
599
   wire [4:0]    cpx_fpexc_d1;
600
 
601
   wire   bst_m;
602
   wire   bst_w;
603
   wire   st_dtlb_perr_w2_l;
604
   wire   can_issue_bst_c2;
605
   wire   other_mem_op_e;
606
   wire [5:0] bst_rs;
607
   wire [2:0] bst_cnt;
608
   wire [2:0] bst_cnt_next;
609
   wire       bst_read_req;
610
   wire       bst_issue_c1;
611
   wire       bst_issue_c2;
612
   wire       bst_issue_c3;
613
   wire       bst_issue_c4;
614
   wire       bst_issue_c5;
615
   wire       bst_issue_c6;
616
   wire       bst_issue_c1_next;
617
   wire       bst_issue_c2_next;
618
   wire       bst_issue_c3_next;
619
   wire       bst_issue_c4_next;
620
   wire       bst_issue_c5_next;
621
   wire       bst_issue_c6_next;
622
   wire       bst_done;
623
   wire [2:0] bld_cnt_d1;
624
   wire [2:0] bld_cnt_d2;
625
   wire [2:0] bld_cnt_d3;
626
   wire       stb_full0;
627
   wire       stb_full1;
628
   wire       stb_full2;
629
   wire       stb_full3;
630
   wire       stb_full_c2;
631
   wire [5:0] bst_stall_cnt;
632
   wire [5:0] bst_stall_cnt_next;
633
   wire       bst_stall_req;
634
   wire       bst_stall_req_next;
635
   wire       fld_done;
636
   wire       ld_ret;
637
   wire   bst_ce_c4;
638
   wire   bst_ue_c4;
639
   wire   fixed_bst_ce;
640
   wire   fixed_bst_ce_next;
641
   wire   blk_asi_m;
642
 
643
//
644
// Code begins here
645
//
646
   assign clk = rclk;
647
   // Reset flop
648
    dffrl_async rstff(.din (grst_l),
649
                        .q   (ffu_reset_l),
650
                        .clk (clk),
651
                        .rst_l (arst_l), .si(), .so(), .se(se));
652
   assign        ctl_dp_rst_l = ffu_reset_l;
653
   assign        reset = ~ffu_reset_l;
654
   // Stage cpx data by one cycle
655
   dff_s #(13) cpx_dff(.din({cpx_vld, cpx_fcmp, cpx_req[3:0], cpx_fccval[1:0], cpx_fpexc[4:0]}),
656
                     .q({cpx_vld_d1, cpx_fcmp_d1, cpx_req_d1[3:0], cpx_fccval_d1[1:0], cpx_fpexc_d1[4:0]}),
657
                     .clk(clk), .se(se), .si(), .so());
658
   dff_s #(3) lsu_bld_cnt1_dff(.din({lsu_ffu_bld_cnt_w[2:0]}), .clk(clk),
659
                         .q({bld_cnt_d1[2:0]}), .se(se), .si(), .so());
660
   dff_s #(3) lsu_bld_cnt2_dff(.din({bld_cnt_d1[2:0]}), .clk(clk),
661
                         .q({bld_cnt_d2[2:0]}), .se(se), .si(), .so());
662
   dff_s #(3) lsu_bld_cnt3_dff(.din({bld_cnt_d2[2:0]}), .clk(clk),
663
                         .q({bld_cnt_d3[2:0]}), .se(se), .si(), .so());
664
 
665
//----------------------------------------
666
// Decode Instruction From IFU
667
//----------------------------------------
668
   dff_s #(3) fpop_d2e(.din({ifu_ffu_fpop1_d, ifu_ffu_fpop2_d, ifu_ffu_visop_d}), .clk(clk),
669
                     .q({fpop1_e, fpop2_e, visop_e}), .se(se), .si(), .so());
670
   assign        fpop1_next = (any_op_e | reset)? fpop1_e: fpop1;
671
   assign        fpop2_next = (any_op_e | reset)? fpop2_e: fpop2;
672
   assign        visop_next = (any_op_e | reset)? visop_e: visop;
673
   dff_s #(3) fpop_dff(.din({fpop1_next,fpop2_next,visop_next}),
674
                     .q({fpop1,fpop2,visop}),
675
                     .clk(clk), .se(se), .si(), .so());
676
 
677
   assign  fpop_size_0 = ~opf[1] & ~opf[0];
678
   assign  fpop_size_1 = ~opf[1] & opf[0];
679
 
680
   assign  fpop_low_1 = ~opf[3] & ~opf[2] & ~opf[1] & opf[0];
681
   assign  fpop_low_2 = ~opf[3] & ~opf[2] & opf[1] & ~opf[0];
682
   assign  fpop_low_4 = ~opf[3] & opf[2] & ~opf[1] & ~opf[0];
683
   assign  fpop_low_5 = ~opf[3] & opf[2] & ~opf[1] & opf[0];
684
   assign  fpop_low_6 = ~opf[3] & opf[2] & opf[1] & ~opf[0];
685
   assign  fpop_low_8 = opf[3] & ~opf[2] & ~opf[1] & ~opf[0];
686
   assign  fpop_low_9 = opf[3] & ~opf[2] & ~opf[1] & opf[0];
687
   assign  fpop_low_a = opf[3] & ~opf[2] & opf[1] & ~opf[0];
688
   assign  fpop_low_d = opf[3] & opf[2] & ~opf[1] & opf[0];
689
   assign  fpop_low_e = opf[3] & opf[2] & opf[1] & ~opf[0];
690
 
691
   assign  fpop_high_0 = ~opf[8] & ~opf[7] & ~opf[6] & ~opf[5] & ~opf[4];
692
   assign  fpop_high_2 = ~opf[8] & ~opf[7] & ~opf[6] & opf[5] & ~opf[4];
693
   assign  fpop_high_4 = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & ~opf[4];
694
   assign  fpop_high_5 = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & opf[4];
695
   assign  fpop_high_6 = ~opf[8] & ~opf[7] & opf[6] & opf[5] & ~opf[4];
696
   assign  fpop_high_a = ~opf[8] & opf[7] & ~opf[6] & opf[5] & ~opf[4];
697
   assign  fpop_high_8 = ~opf[8] & opf[7] & ~opf[6] & ~opf[5] & ~opf[4];
698
   assign  fpop_high_c = ~opf[8] & opf[7] & opf[6] & ~opf[5] & ~opf[4];
699
   assign  fpop_high_d = ~opf[8] & opf[7] & opf[6] & ~opf[5] & opf[4];
700
   assign  fpop_high_e = ~opf[8] & opf[7] & opf[6] & opf[5] & ~opf[4];
701
   assign  fpop_high_10 = opf[8] & ~opf[7] & ~opf[6] & ~opf[5] & ~opf[4];
702
   assign  fpop_high_18 = opf[8] & opf[7] & ~opf[6] & ~opf[5] & ~opf[4];
703
 
704
   assign  unimpl_op_e = ~((fpop_low_1 | fpop_low_2) & (fpop_high_0 | fpop_high_4 | fpop_high_8 |
705
                                                        fpop1_e & fpop_high_d |
706
                                                        fpop2_e & (fpop_high_5 | fpop_high_c |
707
                                                                           fpop_high_10 | fpop_high_18)) |
708
                           (fpop_low_4 | fpop_low_8) & fpop1_e & (fpop_high_8 | fpop_high_c) |
709
                           (fpop_low_5 | fpop_low_6) & (fpop_high_4 |
710
                                                        fpop1_e & fpop_high_0 |
711
                                                        fpop2_e & (fpop_high_2 | fpop_high_5 |
712
                                                                           fpop_high_6 | fpop_high_a |
713
                                                                           fpop_high_c | fpop_high_e)) |
714
                           fpop_low_6 & fpop1_e & fpop_high_c |
715
                           fpop_low_9 & fpop1_e & (fpop_high_0 | fpop_high_4 | fpop_high_6 |
716
                                                           fpop_high_c) |
717
                           fpop_low_a & fpop1_e & (fpop_high_0 | fpop_high_4) |
718
                           (fpop_low_d | fpop_low_e) & fpop1_e & fpop_high_4) & (fpop1_e | fpop2_e);
719
   assign illegal_field_e = fpop2_e & (fpop_high_5 & |rd_e[4:2] |// bits 29:27 must be zero on fcmp
720
                                       ~opf[4] & ~opf[2] & rs1_e[4]);// bit 18 must be zero on fmovcc
721
 
722
 
723
   assign  convert_op_e = fpop1_e & opf[7];
724
   assign  illegal_rs1_e = (frs1_e[4:0] != 5'b00000) & (move_e & ~rollback_c3 | convert_op_e);
725
 
726
//
727
// Decode size of source and destination. don't care for unimplemented ops
728
//
729
   assign source_single_e = (fpop_high_c & fpop_size_0) | //32b int
730
                                 (opf[0]);// single (also quad but those are illegal
731
 
732
/* -----\/----- EXCLUDED -----\/-----
733
   assign  convert_op = (ifu_ffu_fpopcode_d[7] |fpop_high_6_d) & ifu_ffu_fpop1_d;
734
   assign dest_single_d = (is_fpop_d)? (fpop_size_1_d & ~convert_op) | // sgl and not conv
735
                                         (ifu_ffu_fpop1_d & ifu_ffu_fpopcode_d[7] & ~ifu_ffu_fpopcode_d[3] &
736
                                          (~fpop_high_8_d | ifu_ffu_fpopcode_d[2])) |// int to s or float to short int
737
                                           (ifu_ffu_visop_d & ifu_ffu_fpopcode_d[0]) :// vis single
738
                                        ifu_ffu_ldst_single_d;
739
 -----/\----- EXCLUDED -----/\----- */
740
   assign dest_single_e = (fpop1_e & (~opf[1] & opf[0] & ~(opf[7] |fpop_high_6) | // sgl and not conv
741
                                              opf[7] & ~opf[3] &
742
                                              (~fpop_high_8 | opf[2])) |// int to s or float to short int
743
                           fpop2_e & fpop_size_1 |
744
                           visop_e & opf[0] | // vis single
745
                           (fst_e | fld_e) & ldst_single_e);
746
 
747
   assign unimpl_op_all_e = (unimpl_op_e | ifu_ffu_quad_op_e |
748
                             illegal_rs1_e | illegal_field_e);
749
 
750
   dff_s #1 qopm_ff(.din (unimpl_op_all_e),
751
                  .q   (unimpl_op_m),
752
                  .clk (clk), .se(se), .si(), .so());
753
 
754
   dff_s #1 qopw_ff(.din (unimpl_op_m),
755
                  .q   (unimpl_op_w),
756
                  .clk (clk), .se(se), .si(), .so());
757
   assign unimpl_qual_w = unimpl_op_w & ~kill_unimpl_w;
758
   assign unimpl_qual_w2 = unimpl_op_w2 & ~flush_w2;
759
 
760
   dff_s #1 qopw2_ff(.din (unimpl_qual_w),
761
                   .q   (unimpl_op_w2),
762
                   .clk (clk), .se(se), .si(), .so());
763
 
764
 
765
   // Decode register encoding (bit[5] wrapped to bit[0] for non singles)
766
   // Also the storage is flopped around so odd regs are at even addresses 
767
   // in the regfile for singles.  this helps because everything external 
768
   // expects data to be [63:0] not [31:0, 63:32] on doubles.
769
 
770
   assign rs1_e[5] = frs1_e[0] & ~source_single_e;// zero for singles
771
   assign rs1_e[4:2] = frs1_e[4:2];
772
   assign rs1_e[1] = frs1_e[1];
773
   assign rs1_e[0] = frs1_e[0] & source_single_e;// only nonzro for sgl
774
 
775
   assign rs2_e[5] = frs2_e[0] & ~source_single_e;// zero for singles
776
   assign rs2_e[4:2] = frs2_e[4:2];
777
   assign rs2_e[1] = frs2_e[1];
778
   assign rs2_e[0] = frs2_e[0] & source_single_e;// only nonzro for sgl
779
 
780
   assign rd_e[5] = frd_e[0] & ~dest_single_e;// zero for singles
781
   assign rd_e[4:2] = frd_e[4:2];
782
   assign rd_e[1] = frd_e[1];
783
   assign rd_e[0] = frd_e[0] & dest_single_e;// only nonzro for sgl
784
 
785
 
786
   // Decode general type of operation
787
   assign is_fpop_d = ifu_ffu_fpop1_d | ifu_ffu_fpop2_d | ifu_ffu_visop_d;
788
 
789
   // Do locally
790
   assign move_e = fpop_high_0 & (fpop1_e | (fpop1 & rollback_c3)) |
791
                                                (rollback_c3 & fpop2 & ~opf[4]);// rollback cond_move
792
   // cond moves don't get rollback because they either don't happen or become unconditional
793
   assign cond_move_e = fpop2_e & ~opf[4];
794
 
795
   assign abs_w = move_w & fpop_high_0 & opf[3];
796
   assign neg_w = move_w & fpop_high_0 & opf[2];
797
 
798
   // Send to FPU
799
   assign fpu_op_e = ((~fpop_high_0 & fpop1_next) | (fpop_high_5 & fpop2_next)) & (any_op_e | rollback_c3);
800
 
801
   // FRF read indication
802
   assign ren_rs2_e = (fpop1_e | fpop2_e | visop_e) | rollback_c3;
803
   assign ren_rs2_e_vld = ren_rs2_e & ~vis_nofrf_e;
804
   assign ren_rs2_m_vld = ren_rs2_m & (cond_move_m & ifu_ffu_mvcnd_m | ~cond_move_m);
805
   assign ren_rs1_e = ((~vis_nofrf_e & visop_e) | // all vis except siam read rs1
806
                       (rollback_c3 & visop) |
807
                       ((fpop2_next & opf[4]) | //FCMP
808
                        (fpop1_next & ~opf[7] & opf[6])) &      // add,sub,mul,div
809
                       (any_op_e | rollback_c3 & ~reset));
810
   assign ren_rs1_w_vld = ren_rs1_w & ~kill_eccchk_w;
811
   assign ren_rs1_w2_vld = ren_rs1_w2 & ~flush_w2;
812
 
813
   //------------------------------------
814
   // Store and wait for FPop to complete
815
   //------------------------------------
816
   // Storage of control signals
817
 
818
   // >>>>> added ~kill_fp
819
   // set these in e so that kill_fp doesn't kill spuriously
820
   assign load_pending_next = fld_e |          // set
821
                (load_pending & ~lsu_ffu_ld_vld & ~kill_fp & ~blk_ld_m);
822
   assign fld_done = lsu_ffu_ld_vld & ~kill_fp & load_pending;
823
   dffr_s ldpend_dff(.din (load_pending_next),
824
                               .q   (load_pending),
825
                               .clk (clk),
826
                               .rst (reset),
827
                               .se(se), .si(), .so());
828
 
829
   assign blk_ld_m = fld_m & blk_asi_m;
830
   assign blk_ld_done = lsu_ffu_ld_vld & ~kill_fp & (bld_cnt_d1[2:0] == 3'b111) & blk_load_pending;
831
   assign blk_load_pending_next = (blk_ld_m & ~kill_m)  | // set
832
          (blk_load_pending & ~kill_fp & ~ffu_ifu_fpop_done_w2);
833
   dffr_s blk_ldpend_dff(.din(blk_load_pending_next),
834
                       .q(blk_load_pending),
835
                       .clk(clk),
836
                       .rst(reset),
837
                       .se(se), .si(), .so());
838
 
839
   assign fp_pending_next = fpu_op_e |   // set
840
                            (fp_pending & ~is_fpu_result & ~kill_fp);
841
   dffr_s fppend_dff(.din(fp_pending_next),
842
                               .q(fp_pending),
843
                               .clk(clk),
844
                               .rst (reset),
845
                               .se(se), .si(), .so());
846
 
847
   // rs1
848
   dff_s #(5) rs1_d2e(.din(ifu_ffu_frs1_d[4:0]), .clk(clk), .q(frs1_e[4:0]), .se(se), .si(), .so());
849
   mux2ds #(6) rs1_mux(.dout (rs1_next[5:0]),
850
                          .in0  (rs1[5:0]),
851
                          .in1  (rs1_e[5:0]),
852
                          .sel0  (~any_op_e),
853
                          .sel1  (any_op_e));
854
   dff_s #(6) rs1_dff(.din(rs1_next[5:0]),
855
                                .clk(clk),
856
                                .q(rs1[5:0]),
857
                    .se(se), .si(), .so());
858
   // rs2
859
   dff_s #(5) rs2_d2e(.din(ifu_ffu_frs2_d[4:0]), .clk(clk), .q(frs2_e[4:0]), .se(se), .si(), .so());
860
   mux2ds #(6) rs2_mux(.dout(rs2_next[5:0]),
861
                       .in0 (rs2[5:0]),
862
                       .in1 (rs2_e[5:0]),
863
                       .sel0(~any_op_e),
864
                       .sel1 (any_op_e));
865
   dff_s #(6) rs2_dff(.din (rs2_next[5:0]),
866
                                .clk (clk),
867
                                .q   (rs2[5:0]),
868
                    .se(se), .si(), .so());
869
   // rd
870
   dff_s #(6) rd_d2e(.din({ifu_ffu_ldst_single_d,ifu_ffu_frd_d[4:0]}), .clk(clk),
871
                   .q({ldst_single_e,frd_e[4:0]}),
872
                   .se(se), .si(), .so());
873
   mux2ds #(6) rd_mux(.dout (rd_next[5:0]),
874
                      .in0  (rd[5:0]),
875
                      .in1  (rd_e[5:0]),
876
                      .sel0 (~any_op_e),
877
                      .sel1  (any_op_e));
878
   dff_s #(6) rd_dff(.din (rd_next[5:0]),
879
                               .clk (clk),
880
                               .q    (rd[5:0]),
881
                   .se  (se), .si(), .so());
882
   // rs size
883
   mux2ds source_single_mux(.dout (source_single_next),
884
                            .in0  (source_single),
885
                            .in1  (source_single_e),
886
                            .sel0(~any_op_e),
887
                            .sel1 (any_op_e));
888
   dff_s source_single_dff(.din(source_single_next),
889
                                           .clk(clk),
890
                                           .q(source_single),
891
                         .se(se), .si(), .so());
892
   // rd size
893
   assign dest_single_next = (any_op_e)? dest_single_e: dest_single;
894
   dff_s dest_single_dff(.din (dest_single_next),
895
                                            .clk (clk),
896
                                            .q   (dest_single),
897
                          .se  (se), .si(), .so());
898
   // thread
899
   mux2ds #(2) tid_mux(.dout (tid_next[1:0]),
900
                       .in0  (tid[1:0]),
901
                       .in1  (tid_e[1:0]),
902
                       .sel0 (~any_op_e),
903
                       .sel1  (any_op_e));
904
   dff_s #(2) tid_dff(.din(tid_next[1:0]),
905
                                .clk(clk),
906
                                .q(tid[1:0]),
907
                    .se(se), .si(), .so());
908
   // extra tid to help fanout for critical signals
909
   dff_s #(2) extra_tid_dff(.din(tid_next[1:0]),
910
                          .clk(clk), .q(extra_tid[1:0]), .se(se), .si(), .so());
911
   // fcc num
912
   mux2ds #(2) fcc_mux(.dout (fcc_num_next[1:0]),
913
                       .in0   (fcc_num[1:0]),
914
                       .in1   (ifu_ffu_fcc_num_d[1:0]),
915
                       .sel0 (~is_fpop_d),
916
                       .sel1   (is_fpop_d));
917
   dff_s #(2) fcc_dff(.din (fcc_num_next[1:0]),
918
                                .clk (clk),
919
                                .q   (fcc_num[1:0]),
920
                    .se  (se), .si(), .so());
921
 
922
   // ldfsr
923
   mux2ds #(2) ldfsr_mux(.dout (ldfsr_next[1:0]),
924
                         .in0  ({ldfsr, ldxfsr}),
925
                         .in1  ({ifu_ffu_ldfsr_d, ifu_ffu_ldxfsr_d}),
926
                         .sel0  (~ifu_ffu_fld_d),
927
                         .sel1  (ifu_ffu_fld_d));
928
   dff_s #(2) ldfsr_dff(.din (ldfsr_next[1:0]),
929
                                  .clk (clk),
930
                                  .q   ({ldfsr, ldxfsr}),
931
                      .se  (se), .si(), .so());
932
 
933
   // op code
934
   mux2ds #(9) opf_mux(.dout (opf_next[8:0]),
935
                       .in0  (opf[8:0]),
936
                       .in1  (ifu_ffu_fpopcode_d[8:0]),
937
                       .sel0  (~is_fpop_d),
938
                       .sel1  (is_fpop_d));
939
   dff_s #(9) opf_dff(.din(opf_next[8:0]),
940
                                .clk(clk),
941
                                .q(opf[8:0]),
942
                   .se(se), .si(), .so());
943
   //----------
944
   // FP Pipe
945
   //----------
946
   dff_s fop_e2m(.din(any_op_e), .clk(clk),
947
                     .q(any_op_m),
948
                     .se(se), .si(), .so());
949
 
950
   dff_s fop_m2w(.din(any_op_m_valid), .clk(clk),
951
                     .q(any_op_w),
952
                     .se(se), .si(), .so());
953
   dff_s fop_w2w2(.din(any_op_w), .clk(clk),
954
                     .q(any_op_w2),
955
                     .se(se), .si(), .so());
956
 
957
   dff_s fst_d2e(.din(ifu_ffu_fst_d),  .clk(clk),
958
                     .q  (fst_e),
959
                     .se(se), .si(), .so());
960
   dff_s fst_e2m(.din(fst_e), .clk(clk),
961
                     .q  (fst_m),
962
                     .se(se), .si(), .so());
963
   dff_s fst_m2w(.din(fst_m), .clk(clk),
964
                     .q  (fst_w),
965
                     .se(se), .si(), .so());
966
   dff_s fld_d2e(.din(ifu_ffu_fld_d),  .clk(clk),
967
                     .q  (fld_e),
968
                     .se(se), .si(), .so());
969
   dff_s fld_e2m(.din(fld_e),  .clk(clk),
970
                     .q  (fld_m),
971
                     .se(se), .si(), .so());
972
 
973
   dff_s ren_rs2_e2m(.din(ren_rs2_e_vld), .clk(clk),
974
                               .q(ren_rs2_m),
975
                               .se(se), .si(), .so());
976
   dff_s ren_rs2_m2w(.din(ren_rs2_m_vld), .clk(clk),
977
                               .q(ren_rs2_w),
978
                               .se(se), .si(), .so());
979
   dff_s ren_rs2_w2w2(.din(ren_rs2_w), .clk(clk),
980
                                .q(ren_rs2_w2),
981
                                .se(se), .si(), .so());
982
   dff_s ren_rs2_w22w3(.din(ren_rs2_w2), .clk(clk),
983
                                .q(ren_rs2_w3),
984
                                .se(se), .si(), .so());
985
   dff_s ren_rs2_w32w4(.din(ren_rs2_w3), .clk(clk),
986
                                .q(ren_rs2_w4),
987
                                .se(se), .si(), .so());
988
 
989
   dff_s ren_rs1_e2m(.din(ren_rs1_e), .clk(clk),
990
                               .q(ren_rs1_m),
991
                               .se(se), .si(), .so());
992
   dff_s ren_rs1_m2w(.din(ren_rs1_m), .clk(clk),
993
                               .q(ren_rs1_w),
994
                               .se(se), .si(), .so());
995
   dff_s ren_rs1_w2w2(.din(ren_rs1_w_vld), .clk(clk),
996
                               .q(ren_rs1_w2),
997
                               .se(se), .si(), .so());
998
   dff_s ren_rs1_w22w3(.din(ren_rs1_w2_vld), .clk(clk),
999
                               .q(ren_rs1_w3),
1000
                               .se(se), .si(), .so());
1001
   dff_s ren_rs1_w32w4(.din(ren_rs1_w3), .clk(clk),
1002
                               .q(ren_rs1_w4),
1003
                               .se(se), .si(), .so());
1004
   dff_s ren_rs1_w42w5(.din(ren_rs1_w4), .clk(clk),
1005
                               .q(ren_rs1_w5),
1006
                               .se(se), .si(), .so());
1007
 
1008
   dff_s cond_move_e2m(.din(cond_move_e), .clk(clk),
1009
                                 .q(cond_move_m),
1010
                                 .se(se), .si(), .so());
1011
 
1012
   dff_s move_e2m(.din(move_e), .clk(clk),
1013
                            .q(move_m),
1014
                            .se(se), .si(), .so());
1015
   dff_s move_m2w(.din(move_m_valid), .clk(clk),
1016
                            .q(move_w),
1017
                            .se(se), .si(), .so());
1018
   dff_s move_wen_m2w(.din(move_wen_m), .clk(clk), .q(move_wen_w),
1019
                    .se(se), .si(), .so());
1020
   dff_s move_wen_w2w2(.din(move_wen_w), .clk(clk), .q(move_wen_w2),
1021
                    .se(se), .si(), .so());
1022
   dff_s move_wdff(.din(move_w_valid), .clk(clk), .q(move_w2), .se(se), .si(), .so());
1023
 
1024
   dff_s stfsr_d2e(.din(ifu_ffu_stfsr_d),
1025
                             .q(stfsr_e),
1026
                             .clk(clk),
1027
                             .se(se), .si(), .so());
1028
 
1029
   dff_s fpu_op_e2m(.din(fpu_op_e), .clk(clk),
1030
                              .q(fpu_op_m),
1031
                              .se(se), .si(), .so());
1032
   dff_s fpu_op_m2w(.din(fpu_op_m), .clk(clk),
1033
                              .q(fpu_op_w),
1034
                              .se(se), .si(), .so());
1035
   dff_s fpu_op_w2w2(.din(fpu_op_w_vld), .clk(clk),
1036
                              .q(fpu_op_w2),
1037
                              .se(se), .si(), .so());
1038
   dff_s fpu_op_w22w3(.din(fpu_op_w2_vld), .clk(clk),
1039
                              .q(fpu_op_w3),
1040
                              .se(se), .si(), .so());
1041
 
1042
   dff_s #(2) tid_d2e(.din(ifu_ffu_tid_d[1:0]),
1043
                                .clk(clk),
1044
                                .q(tid_e[1:0]),
1045
                                .se(se), .si(), .so());
1046
 
1047
   dff_s #(2) tid_e2m(.din(tid_e[1:0]),
1048
                                .clk(clk),
1049
                                .q(tid_m[1:0]),
1050
                                .se(se), .si(), .so());
1051
 
1052
   dff_s #(2) tid_m2w(.din(tid_m[1:0]),
1053
                                .clk(clk),
1054
                                .q(tid_w[1:0]),
1055
                                .se(se), .si(), .so());
1056
 
1057
   dff_s #(2) tid_w2w2(.din(tid_w[1:0]),
1058
                                 .clk(clk),
1059
                                 .q(tid_w2[1:0]),
1060
                                 .se(se), .si(), .so());
1061
 
1062
   dff_s dff_killed_w(.din(kill_m),
1063
                                .clk(clk),
1064
                                .q(killed_w),
1065
                                .se(se), .si(), .so());
1066
 
1067
   dff_s dff_flush_w2(.din(flush_w), .clk(clk), .q(flush_w2), .se(se), .si(), .so());
1068
 
1069
   assign  thr_match_mw2 = ~((tid_m[1] ^ tid_w2[1]) |
1070
                           (tid_m[0] ^ tid_w2[0]));
1071
   assign  thr_match_ww2 = ~((tid_w[1] ^ tid_w2[1]) |
1072
                           (tid_w[0] ^ tid_w2[0]));
1073
 
1074
   assign thr_match_fpw2 = ~((tid[1] ^ tid_w2[1]) |
1075
                           (tid[0] ^ tid_w2[0]));
1076
 
1077
   // new fpops squash previous ones (only possible in m or w, but w will also have ifu_tlu_flush_w)
1078
   // all kill_w signals do not include lsu_ffu_flush_pipe_w.  This must be included at the final destination
1079
   assign flush_w = (lsu_ffu_flush_pipe_w | ifu_tlu_flush_w) & ~rolled_back;
1080
   assign any_op_e = fpop1_e | fpop2_e | fst_e | fld_e | visop_e;
1081
   assign any_op_m_valid = any_op_m & ~any_op_e;
1082
   assign  kill_m = (thr_match_mw2 & flush_w2) | any_op_e;
1083
   assign  kill_eccchk_w = (~ifu_tlu_inst_vld_w | killed_w | unimpl_op_w | any_op_e |
1084
                            (thr_match_ww2 & flush_w2)) & ~rolled_back;
1085
   // unimplemented ops don't check rolled_back because they trap before rollback happens
1086
   assign  kill_unimpl_w = (~ifu_tlu_inst_vld_w | killed_w | any_op_e
1087
                          | (thr_match_ww2 & flush_w2));
1088
   assign  kill_w = (~ifu_tlu_inst_vld_w | killed_w | any_op_e |
1089
                          unimpl_op_w | ffu_lsu_kill_fst_w | (thr_match_ww2 & flush_w2)) & ~rolled_back;
1090
   // this kills the "pending" signals that are set in the E stage.
1091
   // Since they are set in E all the kills can be delayed by one cycle without
1092
   // squashing a new, valid op
1093
   assign  kill_fp = (thr_match_fpw2 & flush_w2 | any_op_e |
1094
                                  any_op_w & (~ifu_tlu_inst_vld_w | unimpl_op_w)) & ~rolled_back;
1095
 
1096
 
1097
//----------------------------
1098
// Control for muxes that manipulate data to/from FRF
1099
//----------------------------
1100
   // implement fmov/fmovcc
1101
   assign  move_wen_m = move_m | (cond_move_m & ifu_ffu_mvcnd_m);
1102
   assign  move_wen_w2_valid = move_wen_w2 & move_w2_vld;
1103
   assign  move_m_valid = (move_m | cond_move_m);
1104
   // used for updating fsr
1105
   assign  move_w_valid = move_w & ~kill_w;
1106
   assign  move_w2_vld = move_w2 & ~flush_w2 & ~rollback_rs2_w2 & ~(rs2_ue_w2 & nceen);
1107
 
1108
   // negation or absolute value happen to rs2 in the m_stage if needed
1109
   assign  ctl_dp_sign[1] = (dp_ctl_rs2_sign[1] ^ neg_w) & ~abs_w;
1110
   assign  ctl_dp_sign[0] = (source_single) ?
1111
                             (dp_ctl_rs2_sign[0] ^ neg_w) & ~abs_w :
1112
                              dp_ctl_rs2_sign[0];
1113
 
1114
   //
1115
   // Shifts to align sgl precision 32b data
1116
   //
1117
   // mux for moving around single data from frf
1118
 
1119
   // shift on moves or stores
1120
   assign shift_frf_rs2_m = (rs2[0] ^ rd[0]) & (move_m | cond_move_m | visop_m) & ~fst_e;
1121
   assign shift_frf_rs1_w = (rs1[0] ^ rd[0]) & visop_w_vld; //check for squash
1122
 
1123
   assign  shift_frf_right_next = (source_single & shift_frf_rs2_m & ~rs2[0]) |
1124
                                      (source_single & shift_frf_rs1_w & ~rs1[0]) |
1125
                                      (dest_single_e & fst_e & ~rd_e[0]);
1126
 
1127
   assign  shift_frf_left_next = ((source_single & rs2[0] & (shift_frf_rs2_m | fpu_op_m & ~fst_e) |
1128
                                   source_single & rs1[0] & (shift_frf_rs1_w | fpu_op_w_vld))
1129
                                  & ~shift_frf_right_next);
1130
 
1131
   assign  noshift64_frf_next = ~(shift_frf_right_next | shift_frf_left_next);
1132
 
1133
   assign  ctl_dp_shift_frf_right = shift_frf_right & ~rst_tri_en;
1134
   assign  ctl_dp_shift_frf_left = shift_frf_left & ~rst_tri_en;
1135
   assign  ctl_dp_noshift64_frf = noshift64_frf | rst_tri_en;
1136
 
1137
   // fpu expects lower 32 bits to be zero on single operands
1138
   assign  zero_lower_data_next = ((source_single & ~rs1[0] & fpu_op_w_vld) |
1139
                                   (source_single & ~rs2[0] & fpu_op_m));
1140
 
1141
   dff_s shift_frf_right_dff(.din(shift_frf_right_next), .clk(clk), .q(shift_frf_right),
1142
                           .se(se), .si(), .so());
1143
   dff_s shift_frf_left_dff(.din(shift_frf_left_next), .clk(clk), .q(shift_frf_left),
1144
                           .se(se), .si(), .so());
1145
   dff_s noshift64_dff(.din(noshift64_frf_next), .clk(clk), .q(noshift64_frf),
1146
                     .se(se), .si(), .so());
1147
   dff_s noshift32_dff(.din(zero_lower_data_next), .clk(clk), .q(ctl_dp_zero_low32_frf),
1148
                     .se(se), .si(), .so());
1149
 
1150
   wire    flip_fpu;
1151
   wire    flip_lsu;
1152
   // mux for rearranging data from fpu
1153
   // data comes in with msb always at b63.  This means that singles with an odd
1154
   // rd must be flipped so that the data ends up in the correct
1155
   //  registers.
1156
   assign  flip_fpu = (dest_single & rd[0]);// single with odd rd
1157
 
1158
   // mux for rearranging data from lsu
1159
   // data comes in [63:0].  This means that singles with an even
1160
   // rd must be flipped so that the data ends up in the correct
1161
   //  registers.
1162
   assign  flip_lsu = (dest_single & ~rd[0]);// single with even rd
1163
 
1164
   assign  ctl_dp_noflip_lsu = ld_ret & ~flip_lsu;
1165
   assign  ctl_dp_flip_lsu = ld_ret & flip_lsu;
1166
   assign  ctl_dp_noflip_fpu = ~ld_ret & ~flip_fpu & is_fpu_result & ~cpx_fcmp_d1;
1167
   assign  ctl_dp_flip_fpu = ~ld_ret & ~ctl_dp_noflip_fpu;
1168
 
1169
 
1170
//---------------------------------
1171
// LSU Interface
1172
//---------------------------------
1173
 
1174
   // Note that stores fit into the standard pipeline so they are automatically 
1175
   // accepted and do not require an ACK.  The lsu will check for kills in m and w.
1176
 
1177
   assign  store_ready = fst_m | bst_issue_c3;
1178
   assign  fpu_op_w_vld = fpu_op_w & ~kill_w;
1179
   assign  fpu_op_w2_vld = fpu_op_w2 & ~flush_w2 & ~ecc_kill_rs2_w2;
1180
   assign  fpu_op_w3_vld = fpu_op_w3 & ~ue_trap_w3 & ~rollback_rs1_w3;
1181
   // don't qual with inst_vld since it takes too much time?
1182
   // Resolved with Sanjay:
1183
   //    Will never receive ack in the same cycle req was first made
1184
   assign  fpop1_ready_w2_next = (fpu_op_w3_vld |
1185
                                                         (fpop1_ready_w2 & ~lsu_ffu_ack));
1186
 
1187
   dffr_s #1 fpop1_w2_dff(.din (fpop1_ready_w2_next),
1188
                                   .q   (fpop1_ready_w2),
1189
                                   .rst (reset),
1190
                                   .clk (clk), .se(se), .si(), .so());
1191
 
1192
   // once op1 has been accepted, move to w2, and in the next cycle op2 is ready
1193
   //
1194
   // C1 -- recv ack, send op1 (fpop1_ready_w2)
1195
   // C2 -- send op2 (fpop2_ready_w3)
1196
   assign fpop2_ready_w3_next = fpop1_ready_w2 & lsu_ffu_ack;
1197
 
1198
   dff_s fpop2_w22w3(.din (fpop2_ready_w3_next),
1199
                               .q   (fpop2_ready_w3),
1200
                               .clk(clk), .se(se), .si(), .so());
1201
 
1202
 
1203
   // request in W2 and wait till an ack is received
1204
   //    Will never receive ack in the same cycle req was first made
1205
   assign ffu_lsu_fpop_rq_vld = fpu_op_w3_vld;
1206
 
1207
   // valid pkt sent to lsu (after request)
1208
   assign issue_fpop2 = fpop2_ready_w3 & ~opf[7];// not conversion op
1209
   assign  lsu_pkt_vld = fpop1_ready_w2 | fpu_op_w3_vld | issue_fpop2 | store_ready;
1210
 
1211
   assign lsu_pkt_type[1:0] = {store_ready, fpop2_ready_w3};
1212
 
1213
   // Create packet for LSU: ffu_lsu_data[80:0]
1214
   //     80 = vld
1215
   //     79:78 = type (00 = fpu operand 1, 01 = fpu operand 2, 10 = fp store)
1216
   //     77:76 = tid
1217
   //     75:68 = floating point opcode
1218
   //     67:66 = fcc
1219
   //     65:64 = rounding mode
1220
   //     63:0 = data
1221
   assign ffu_lsu_data[80:64] = {lsu_pkt_vld,
1222
                                 lsu_pkt_type[1:0],
1223
                                 extra_tid[1:0],
1224
                                 opf[7:0],
1225
                                 fcc_num[1:0],
1226
                                 fpu_rnd[1:0]};  // rounding mode
1227
 
1228
   // Select data to send to LSU.  This is calculated one cycle early and flopped
1229
   assign output_sel_rs1_next = fpop2_ready_w3_next & ~fst_e & ~bst_issue_c3_next;     // rs2 is sent first (fpop1)
1230
   assign output_sel_frf_next = fst_e & ~stfsr_e | bst_issue_c3_next;   // store data
1231
   assign output_sel_fsr_next = fst_e & stfsr_e & ~bst_issue_c3_next;
1232
   assign output_sel_rs2_next = ~(fpop2_ready_w3_next | fst_e | bst_issue_c3_next);
1233
   assign ctl_dp_output_sel_rs1 = output_sel_rs1 & ~rst_tri_en;
1234
   assign ctl_dp_output_sel_frf = output_sel_frf & ~rst_tri_en;
1235
   assign ctl_dp_output_sel_fsr = output_sel_fsr & ~rst_tri_en;
1236
   assign ctl_dp_output_sel_rs2 = output_sel_rs2 | rst_tri_en;
1237
   dff_s #(4) output_sel_dff(.din({output_sel_rs1_next,output_sel_rs2_next,output_sel_frf_next,output_sel_fsr_next}),
1238
                           .q({output_sel_rs1,output_sel_rs2,output_sel_frf,output_sel_fsr}),
1239
                           .clk(clk), .se(se), .si(), .so());
1240
 
1241
 
1242
   dff_s #1 sfsrw_ff(.din (ctl_dp_output_sel_fsr),
1243
                               .q   (stfsr_w),
1244
                               .clk (clk), .se(se), .si(), .so());
1245
   dff_s stfsr_wdff(.din(stfsr_qual_w), .clk(clk), .q(stfsr_w2), .se(se), .si(), .so());
1246
   assign stfsr_qual_w =  (stfsr_w & ~kill_w);
1247
   assign stfsr_w2_vld = stfsr_w2 & ~flush_w2;
1248
 
1249
 
1250
   //------------------------------------------------------
1251
   //  Block Stores
1252
   //------------------------------------------------------
1253
   // interface with lsu.  bst packet issues in c3
1254
   // check for stb_full so it doesn't confuse lsu.  Don't have to count inflight packets
1255
   // because none exist by bst_issue_c2
1256
   assign        ffu_lsu_blk_st_e = bst_issue_c2 & ~stb_full_c2;
1257
   assign        ffu_lsu_blk_st_va_e[5:3] = bst_cnt[2:0];
1258
   assign        bst_done = bst_issue_c4 & (bst_cnt[2:0] == 3'b111) & ~bst_ce_c4 & ~(bst_ue_c4 & nceen);
1259
 
1260
   mux4ds stb_full_mux (.dout(stb_full_c2),
1261
                        .in0(stb_full0),
1262
                        .in1(stb_full1),
1263
                        .in2(stb_full2),
1264
                        .in3(stb_full3),
1265
                        .sel0(ctl_dp_fp_thr[0]),
1266
                        .sel1(ctl_dp_fp_thr[1]),
1267
                        .sel2(ctl_dp_fp_thr[2]),
1268
                        .sel3(ctl_dp_fp_thr[3]));
1269
 
1270
   assign        other_mem_op_e = exu_ffu_ist_e | ifu_tlu_flsh_inst_e | ifu_lsu_ld_inst_e;
1271
   assign        can_issue_bst_c2  = (~other_mem_op_e & ~stb_full_c2);
1272
   assign bst_m = fst_m & blk_asi_m;
1273
 
1274
   assign bst_rs[5:0] = {rd[5:4], bst_cnt[2:0], 1'b0};
1275
 
1276
   // bst starts when bst hits w and is done when the 7th pckt has issued
1277
   assign bst_issue_c1_next = ((bst_w & ~kill_w) |
1278
                               (bst_issue_c4 & ~(bst_cnt[2:0] == 3'b111) & ~bst_ce_c4 &
1279
                                ~(bst_ue_c4 & nceen)) | bst_issue_c6);
1280
 
1281
   // sotheas,9/14/04: fixed eco 6910, suppress block store start on dtlb perr
1282
   //                  using registered version of lsu_ffu_st_dtlb_perr_g
1283
   //   WAS:
1284
   //        assign bst_issue_c2_next = ((bst_issue_c1 & ~(any_op_w2 & flush_w2)) | (bst_issue_c2 & ~can_issue_bst_c2)) & ~reset;
1285
   //   IS:
1286
   dff_s #1 st_dtlbperr_ff(.din (!lsu_ffu_st_dtlb_perr_g),
1287
                               .q   (st_dtlb_perr_w2_l),
1288
                               .clk (clk), .se(se), .si(), .so());
1289
   assign bst_issue_c2_next = ((bst_issue_c1 & ~(any_op_w2 & flush_w2) & st_dtlb_perr_w2_l)
1290
                             | (bst_issue_c2 & ~can_issue_bst_c2)) & ~reset;
1291
   assign bst_issue_c3_next = bst_issue_c2 & can_issue_bst_c2 & ~reset;
1292
   assign bst_issue_c4_next = bst_issue_c3 & ~reset;
1293
   assign bst_issue_c5_next = bst_issue_c4 & bst_ce_c4 & ~reset;
1294
   assign bst_issue_c6_next = bst_issue_c5 & ~reset;
1295
 
1296
   // bst keeps reading in both c1 and c2 in case it stalls in c2
1297
   assign bst_read_req = bst_issue_c1 | bst_issue_c2;
1298
   // counter resets to 1 when bst hits w, increments when one is issued to lsu without ce
1299
   assign bst_cnt_next[2:0] = (bst_w?                            3'b001:
1300
                               (bst_issue_c4 & ~bst_ce_c4)?  (bst_cnt[2:0] + 3'b001):
1301
                                               bst_cnt[2:0]);
1302
 
1303
   ///////////////////
1304
   // bst starvation
1305
   //----------------
1306
   // when six bit counter saturates then a req to stall inst issue is made
1307
   // The request stays high until a bst gets issued
1308
   ///////////////////
1309
   assign ffu_ifu_stallreq = bst_stall_req;
1310
   assign bst_stall_req_next = ((bst_stall_cnt[5:0] == 6'b111111) & bst_issue_c2 & ~can_issue_bst_c2 |
1311
                                bst_stall_req & other_mem_op_e);
1312
   assign bst_stall_cnt_next[5:0] = (~bst_issue_c2)? 6'd0: bst_stall_cnt[5:0] + 6'd1;
1313
 
1314
   /////////////////////
1315
   // bst ecc control
1316
   /////////////////////
1317
   // if a ce occurs even after correction then it is converted to a ue
1318
   assign bst_ue_c4 = bst_issue_c4 & (previous_ue | (fixed_bst_ce & |previous_ce[1:0]));
1319
   assign bst_ce_c4 = bst_issue_c4 & |previous_ce[1:0] & ~fixed_bst_ce & ~previous_ue;
1320
   assign fixed_bst_ce_next = bst_ce_c4 | (fixed_bst_ce & ~bst_issue_c4);
1321
 
1322
   dff_s #(4) stb_full_dff(.din({lsu_ffu_stb_full0,lsu_ffu_stb_full1,lsu_ffu_stb_full2,lsu_ffu_stb_full3}),
1323
                         .q({stb_full0, stb_full1, stb_full2, stb_full3}),
1324
                         .clk(clk), .se(se), .si(), .so());
1325
   dff_s blk_asi_dff(.din(lsu_ffu_blk_asi_e), .clk(clk), .q(blk_asi_m),
1326
                   .se(se), .si(), .so());
1327
   dffr_s bst_fix_ce_dff(.din(fixed_bst_ce_next), .clk(clk), .q(fixed_bst_ce),
1328
                       .se(se), .si(), .so(), .rst(reset));
1329
   dff_s #(3) bst_cnt_dff(.din(bst_cnt_next[2:0]), .clk(clk), .q(bst_cnt[2:0]),
1330
                        .se(se), .si(), .so());
1331
   dff_s bst_m2w(.din(bst_m), .clk(clk), .q(bst_w), .se(se), .si(), .so());
1332
   dff_s bst_issue_c1_dff(.din(bst_issue_c1_next), .clk(clk), .q(bst_issue_c1), .se(se),
1333
                     .si(), .so());
1334
   dff_s bst_issue_c2_dff(.din(bst_issue_c2_next), .clk(clk), .q(bst_issue_c2), .se(se),
1335
                     .si(), .so());
1336
   dff_s bst_issue_c3_dff(.din(bst_issue_c3_next), .clk(clk), .q(bst_issue_c3), .se(se),
1337
                     .si(), .so());
1338
   dff_s bst_issue_c4_dff(.din(bst_issue_c4_next), .clk(clk), .q(bst_issue_c4), .se(se),
1339
                     .si(), .so());
1340
   dff_s bst_issue_c5_dff(.din(bst_issue_c5_next), .clk(clk), .q(bst_issue_c5), .se(se),
1341
                     .si(), .so());
1342
   dff_s bst_issue_c6_dff(.din(bst_issue_c6_next), .clk(clk), .q(bst_issue_c6), .se(se),
1343
                     .si(), .so());
1344
   dff_s #(6) bst_stall_cntdff(.din(bst_stall_cnt_next[5:0]), .clk(clk), .q(bst_stall_cnt[5:0]),
1345
                             .se(se), .si(), .so());
1346
   dffr_s bst_stall_reqdff(.din(bst_stall_req_next), .clk(clk), .q(bst_stall_req),
1347
                        .se(se), .si(), .so(), .rst(reset));
1348
 
1349
//----------------------------------------
1350
// Decode Returning FPU/LSU packets
1351
//----------------------------------------
1352
 
1353
   // FPU result pulled off of cpx
1354
   assign is_fpu_result = (cpx_req_d1 == `FP_RET) ?
1355
                           cpx_vld_d1 & fp_pending : 1'b0;
1356
   assign ld_ret = lsu_ffu_ld_vld & ~(thr_match_fpw2 & flush_w2) & (blk_load_pending | load_pending);
1357
 
1358
   // select frf write data
1359
   // don't write data on Fcompares
1360
   assign ctl_dp_rs2_sel_fpu_lsu = is_fpu_result & ~cpx_fcmp_d1 | ld_ret;
1361
   assign ctl_dp_rs2_sel_vis = vis_result & ~ctl_dp_rs2_sel_fpu_lsu;
1362
   assign ctl_dp_rs2_frf_read = (ren_rs2_w | ctl_dp_rd_ecc) & ~ctl_dp_rs2_sel_fpu_lsu & ~vis_result;
1363
   assign ctl_dp_rs2_keep_data = ~(ren_rs2_w | ctl_dp_rd_ecc | vis_result |
1364
                                   ctl_dp_rs2_sel_fpu_lsu);
1365
 
1366
   // selects for rs2 result mux
1367
   assign ctl_dp_rd_ecc = fst_ce_w | rollback_rs2_w2 | bst_ce_c4 | rollback_rs1_w3;
1368
 
1369
   // Selects for rs1 mux
1370
   assign ctl_dp_new_rs1 = ren_rs1_w2;
1371
 
1372
//----------------------------------------
1373
// FRF Controls
1374
//----------------------------------------   
1375
   // WEN for frf from load, FPU result or mov
1376
   assign external_wen_next = ld_ret & ~(ldfsr | ldxfsr) | (is_fpu_result & ~cpx_fcmp_d1 & ~take_ieee_trap);
1377
   assign rf_ecc_gen_next = external_wen_next | vis_wen_next;
1378
 
1379
   dff_s rf_eccgen_dff(.din(rf_ecc_gen_next), .q(rf_ecc_gen), .clk(clk), .se(se), .si(), .so());
1380
   dff_s rf_wen_dff(.din(rf_wen_next), .q(rf_wen), .clk(clk), .se(se), .si(), .so());
1381
   // check for flush_pipe for moves
1382
   assign rf_wen_next = rf_ecc_gen & ~(any_op_w2 & flush_w2) | move_wen_w2_valid;
1383
 
1384
 
1385
   // REN and WEN must be mutually exclusive.  This works because WEN is always after W
1386
   // if a new fpop has arrived to cancel it.
1387
   // The even register is the upper half, odd is the lower half
1388
   assign ctl_frf_wen[1] = ((rf_wen & ~rd[0]) | ecc_wen[1]) & ~ctl_frf_ren;   // double or even sgl
1389
   assign ctl_frf_wen[0] = ((rf_wen & (~dest_single | rd[0])) | ecc_wen[0]) & ~ctl_frf_ren; // dbl or odd sgl
1390
 
1391
   // REN for frf  -- rd rs2 in D, rs1 in E
1392
   assign read_rs2 = ren_rs2_e;
1393
   assign read_rs1 = ren_rs1_m;
1394
   assign read_rd = ifu_ffu_fst_d;
1395
   assign read_bst = bst_read_req;
1396
   // expanded out the terms for reading rs2 to help timing
1397
   assign ctl_frf_ren = (read_rs1 | read_rs2 |
1398
                         ifu_ffu_fst_d | bst_read_req);
1399
 
1400
   assign early_frf_rnum[5:1] = read_rs2?  rs2_next[5:1]:
1401
                                read_rs1?  rs1[5:1]:
1402
                                read_bst?  bst_rs[5:1]:
1403
                                           write_addr[5:1];
1404
   assign     st_rd_d[5:1] = {ifu_ffu_frd_d[0] & ~ifu_ffu_ldst_single_d, ifu_ffu_frd_d[4:1]};
1405
   mux2ds #5 frf_rnum_mux(.dout(frf_rnum[5:1]),
1406
                            .in0(early_frf_rnum[5:1]),
1407
                            .in1(st_rd_d[5:1]),
1408
                            .sel0(~read_rd),
1409
                            .sel1(read_rd));
1410
 
1411
   assign frf_tid[1:0] = (read_rd)? ifu_ffu_tid_d[1:0]: tid_next[1:0];
1412
 
1413
   assign wen_rs2_ecc = |ecc_wen[1:0] & ren_rs2_w4;
1414
   assign wen_rs1_ecc = |ecc_wen[1:0] & ren_rs1_w5;
1415
   assign blk_rd[5:1] = rd[5:1] + {2'b0, bld_cnt_d3[2:0]};
1416
   assign write_addr[5:1] = wen_rs2_ecc?          rs2[5:1] :
1417
                            wen_rs1_ecc?          rs1[5:1] :
1418
                            bst_issue_c6?         bst_rs[5:1]:
1419
                            blk_load_pending?     blk_rd[5:1]:
1420
                                                  rd[5:1];
1421
 
1422
   // Address is combination of tid and rnum
1423
   assign ctl_frf_addr[6:0] = {frf_tid[1:0], frf_rnum[5:1]};
1424
 
1425
//----------------------------------------
1426
// Data from FPU forwarded to IFU
1427
//----------------------------------------
1428
   // Send thrid to IFU
1429
   assign ffu_ifu_tid_w2[1:0] = tid;
1430
 
1431
   // completion is always signalled after the w-stage so that flush_pipe, etc.
1432
   // can be checked.  For lds and fpops this is signalled after they write.
1433
   // ecc_kill_rs2_w is checked for move and fst because the "compeletion"
1434
   // is signalled over a separate interface so rollback can occur.
1435
   // This is staged 2 cycles to allow for the cycle of ecc generation.
1436
   //
1437
   assign ffu_op_done_next = ((is_fpu_result & ~take_ieee_trap) | fld_done |
1438
                              blk_ld_done | bst_done | vis_result |
1439
                              fst_w & ~bst_w & ~kill_w);
1440
   dff_s ffu_op_done_dff(.din(ffu_op_done_next), .clk(clk), .q(ffu_op_done),
1441
                       .se(se), .si(), .so());
1442
   // sotheas,9/14/04: fixed eco 6910, send done on dtlb perr for block store
1443
   //                  using registered version of lsu_ffu_st_dtlb_perr_g
1444
   //   WAS:
1445
   //     assign ffu_op_done_vld = ffu_op_done & ~(any_op_w2 & flush_w2) | move_w2_vld;
1446
   assign ffu_op_done_vld = (ffu_op_done | (bst_issue_c1 & !st_dtlb_perr_w2_l) )
1447
                            & ~(any_op_w2 & flush_w2) | move_w2_vld;
1448
   dff_s ffu_op_done2_dff(.din(ffu_op_done_vld), .clk(clk), .q(ffu_ifu_fpop_done_w2),
1449
                        .se(se), .si(), .so());
1450
 
1451
//------------------------------------------
1452
// FSR Controls
1453
//------------------------------------------
1454
 
1455
   assign ctl_dp_fp_thr[0] = ~extra_tid[1] & ~extra_tid[0];
1456
   assign ctl_dp_fp_thr[1] = ~extra_tid[1] &  extra_tid[0];
1457
   assign ctl_dp_fp_thr[2] =  extra_tid[1] & ~extra_tid[0];
1458
   assign ctl_dp_fp_thr[3] =  extra_tid[1] &  extra_tid[0];
1459
 
1460
   // CC's
1461
   assign fcc_num_dec[0] = ~fcc_num[1] & ~fcc_num[0];
1462
   assign fcc_num_dec[1] = ~fcc_num[1] & fcc_num[0];
1463
   assign fcc_num_dec[2] = fcc_num[1] & ~fcc_num[0];
1464
   assign fcc_num_dec[3] = fcc_num[1] & fcc_num[0];
1465
 
1466
   // selects to load next fsr from
1467
   // stfsr or fmov always clear ftt
1468
   assign clear_ftt = stfsr_w2_vld | move_w2_vld | is_fpu_result;
1469
 
1470
   assign ctl_dp_fsr_sel_fpu[3:0] = ({4{is_fpu_result | move_w2_vld | take_other_trap | stfsr_w2_vld}}
1471
                                     & ctl_dp_fp_thr[3:0]);
1472
   assign ctl_dp_fsr_sel_ld[3:0] =  ({4{ld_ret & (ldfsr | ldxfsr)}} &
1473
                                     ~ctl_dp_fsr_sel_fpu[3:0] & ctl_dp_fp_thr[3:0]);
1474
   assign ctl_dp_fsr_sel_old[3:0] =  (~ctl_dp_fsr_sel_fpu[3:0] & ~ctl_dp_fsr_sel_ld[3:0]);
1475
 
1476
   // align fcc depending on which fcc_num was used
1477
   mux4ds #8 fcc_ret_mux(.dout (fpu_fcc[7:0]),
1478
                         .in0  ({dp_ctl_fsr_fcc[7:2], cpx_fccval_d1[1:0]}),
1479
                         .in1  ({dp_ctl_fsr_fcc[7:4], cpx_fccval_d1[1:0], dp_ctl_fsr_fcc[1:0]}),
1480
                         .in2  ({dp_ctl_fsr_fcc[7:6], cpx_fccval_d1[1:0], dp_ctl_fsr_fcc[3:0]}),
1481
                         .in3  ({cpx_fccval_d1[1:0], dp_ctl_fsr_fcc[5:0]}),
1482
                         .sel0 (fcc_num_dec[0]),
1483
                         .sel1 (fcc_num_dec[1]),
1484
                         .sel2 (fcc_num_dec[2]),
1485
                         .sel3 (fcc_num_dec[3]));
1486
 
1487
   // set fcc if this was an fcmp instruction
1488
   assign fcc_sel_fpu = cpx_fcmp_d1 & ~ieee_trap & is_fpu_result;
1489
   assign fcc_sel_ld = ~is_fpu_result & ldfsr_vld;
1490
   assign fcc_sel_ldx = ~is_fpu_result & ~ldfsr_vld & ldxfsr_vld;
1491
   assign fcc_sel_old = ~fcc_sel_fpu & ~fcc_sel_ld & ~fcc_sel_ldx;
1492
   mux4ds #8 fcc_set_mux(.dout (ctl_dp_fcc_w2[7:0]),
1493
                                           .in0  (dp_ctl_fsr_fcc[7:0]),
1494
                                           .in1  (fpu_fcc[7:0]),
1495
                                           .in2  (dp_ctl_ld_fcc[7:0]),
1496
                                           .in3  ({dp_ctl_fsr_fcc[7:2], dp_ctl_ld_fcc[1:0]}),
1497
                                           .sel0 (fcc_sel_old),
1498
                                           .sel1 (fcc_sel_fpu),
1499
                                           .sel2 (fcc_sel_ldx),
1500
                                           .sel3 (fcc_sel_ld));
1501
 
1502
   // get fcc's from ldfsr instruction
1503
   assign ldfsr_vld = ldfsr & load_pending;
1504
   assign ldxfsr_vld = ldxfsr & load_pending;
1505
 
1506
   wire   cc_changed_w2;
1507
 
1508
   // fcc set by fcmp, ldfsr or ldxfsr
1509
   assign cc_changed = fcc_sel_fpu |
1510
                             fld_done & (ldfsr_vld | ldxfsr_vld);
1511
 
1512
   dff_s cc_changed_dff(.din(cc_changed), .clk(clk), .q(cc_changed_w2),
1513
                      .se(se), .si(), .so());
1514
   dff_s #(8) cc_next(.din(ctl_dp_fcc_w2[7:0]), .clk(clk), .q(ffu_ifu_cc_w2[7:0]),
1515
                    .se(se), .si(), .so());
1516
 
1517
   assign ffu_ifu_cc_vld_w2[3:0] = ctl_dp_fp_thr[3:0] & {4{cc_changed_w2}};
1518
 
1519
//-----------------------------------
1520
// Traps
1521
//-----------------------------------   
1522
 
1523
   // illegal instruction if blk ld/st is not 8 dp regs aligned
1524
   dff_s illegal_vis_e2m (.din(illegal_vis_e), .clk(clk), .q(illegal_vis_m),
1525
                        .se(se), .si(), .so());
1526
   assign illegal_blk_m = (blk_ld_m | bst_m) & (rd[0] | rd[1] | rd[2] | rd[3]) & ~dest_single;
1527
   assign ffu_tlu_ill_inst_m = illegal_blk_m | illegal_vis_m;
1528
 
1529
   assign ctl_dp_ftt_w2 = take_ieee_trap      ? 3'b001 :
1530
                          unimpl_qual_w2        ? 3'b011 :
1531
                          clear_ftt           ? 3'b000 :
1532
                                                3'bxxx;
1533
 
1534
// SPARC V9 Underflow, Overflow, Inexact behavior: 
1535
//
1536
//      Exception(s)             |            Current
1537
//      Detected    Trap Enable  | fp_        Exception
1538
//      in f.p.     Mask Bits    | exception_ Bits (in
1539
//      operation   (in FSR.TEM) | ieee_754   FSR.cexc)   
1540
//      ----------- ------------ | Trap       ----------- 
1541
//      of  uf  nx  OFM UFM NXM  | Occurs?    ofc ufc nxc  Notes
1542
//      --- --- --- --- --- ---  | ---------- --- --- ---  -----
1543
//       -   -   -   x   x   x   |  no         0   0   0   
1544
//       -   -   *   x   x   0   |  no         0   0   1 
1545
//       -   *   *   x   0   0   |  no         0   1   1
1546
//       *   -   *   0   x   0   |  no         1   0   1    (2)
1547
//                               | 
1548
//       -   -   *   x   x   1   |  yes        0   0   1 
1549
//       -   *   *   x   0   1   |  yes        0   0   1 
1550
//       -   *   -   x   1   x   |  yes        0   1   0
1551
//       -   *   *   x   1   x   |  yes        0   1   0 
1552
//       *   -   *   1   x   x   |  yes        1   0   0    (2)
1553
//       *   -   *   0   x   1   |  yes        0   0   1    (2)
1554
//
1555
//      (2) Overflow is always accompanied by inexact.
1556
//
1557
//
1558
// The FPU does not receive FSR.TEM bits. FSR.TEM bits are used within
1559
// the FFU for the following cases:
1560
// (1) fp_exception_ieee_754 trap detection
1561
//     If a FPop generates an IEEE exception (nv, of, uf, dz, nx) for
1562
//     which the corresponding trap enable (TEM) is set, then a
1563
//     fp_exception_ieee_754 trap is caused. FSR.cexc field has one bit
1564
//     set corresponding to the IEEE exception, and FSR.aexc field is
1565
//     unchanged.
1566
// (2) Clear FSR.nxc if an overflow (underflow) exception does trap
1567
//     because FSR.OFM (FSR.UFM) is set, regardless of whether FSR.NXM
1568
//     is set. Set FSR.ofc (FSR.ufc).
1569
// (3) Clear FSR.ofc (FSR.ufc) if overflow (underflow) exception traps
1570
//     and FSR.OFM (FSR.UFM) is not set and FSR.NXM is set. Set FSR.nxc.
1571
// (4) Clear FSR.ufc if the result is exact (FSR.nxc is not set) and
1572
//     FSR.UFM is not set. This case represents an exact denormalized
1573
//     result.
1574
//
1575
// Note: - FPU will signal underflow to the FFU for all "tiny" results.
1576
//       - FPU always reports inexact along with overflow.
1577
   dff_s #(5) tem_dff(.din(dp_ctl_fsr_tem[4:0]), .clk(clk), .q(fsr_tem_d1),
1578
                    .se(se), .si(), .so());
1579
   assign fpexc_nxc =
1580
          cpx_fpexc_d1[`FSR_NXC] &
1581
          ~(( fsr_tem_d1[3] & cpx_fpexc_d1[`FSR_OFC]) |    // enabled  of
1582
            ( fsr_tem_d1[2] & cpx_fpexc_d1[`FSR_UFC])  );  // enabled  uf
1583
 
1584
   assign fpexc_ofc =
1585
          cpx_fpexc_d1[`FSR_OFC] &
1586
          ~(~fsr_tem_d1[3] & fsr_tem_d1[0] & cpx_fpexc_d1[`FSR_NXC]); // disabled of and enabled nx
1587
 
1588
   assign fpexc_ufc =
1589
          cpx_fpexc_d1[`FSR_UFC] &
1590
          ~(~fsr_tem_d1[2] & ( fsr_tem_d1[0] & cpx_fpexc_d1[`FSR_NXC])) & // disabled uf & enabled nx
1591
          ~(~fsr_tem_d1[2] & ~cpx_fpexc_d1[`FSR_NXC]) ; // disabled uf with no inexact
1592
                                                               // (i.e. exact denorm w/ UFM=0)
1593
 
1594
 
1595
   assign ieee_trap_vec[4:0] =
1596
          ({cpx_fpexc_d1[4],
1597
            fpexc_ofc,
1598
            fpexc_ufc,
1599
            cpx_fpexc_d1[1],
1600
            fpexc_nxc       } & fsr_tem_d1[4:0]);
1601
 
1602
 
1603
   // ieee trap has least priority.  Put through a flop for timing reasons
1604
   assign ieee_trap = (|ieee_trap_vec[4:0]);
1605
   assign take_ieee_trap = ieee_trap & is_fpu_result;
1606
   dff_s trap_ieee_dff(.din(take_ieee_trap), .clk(clk), .q(ffu_tlu_trap_ieee754),
1607
                     .se(se), .si(), .so());
1608
 
1609
   assign take_other_trap = unimpl_qual_w2;
1610
   assign ffu_tlu_trap_other = take_other_trap;
1611
   assign ffu_tlu_trap_ue = ue_trap_w3;
1612
 
1613
   // current exception
1614
   assign fp_exc_w2[4:0] =
1615
          ({cpx_fpexc_d1[4],
1616
            fpexc_ofc,
1617
            fpexc_ufc,
1618
            cpx_fpexc_d1[1],
1619
            fpexc_nxc       });
1620
 
1621
 
1622
 
1623
 
1624
   // accrued exceptions
1625
   // fp_exc_w2 = dp_ctl_fsr_aexc | cpx_fpexc_d1 & {5{~take_ieee_trap}};
1626
   assign fp_exc_w2[`FSR_NVA] = dp_ctl_fsr_aexc[`FSR_NVC] |
1627
                             is_fpu_result & cpx_fpexc_d1[`FSR_NVC] & ~fsr_tem_d1[`FSR_NVC];
1628
   assign fp_exc_w2[`FSR_DZA] = dp_ctl_fsr_aexc[`FSR_DZC] |
1629
                             is_fpu_result & cpx_fpexc_d1[`FSR_DZC] & ~fsr_tem_d1[`FSR_DZC];
1630
   assign fp_exc_w2[`FSR_UFA] = dp_ctl_fsr_aexc[`FSR_UFC] |
1631
                             is_fpu_result & fpexc_ufc & ~fsr_tem_d1[`FSR_UFC];
1632
   assign fp_exc_w2[`FSR_OFA] = dp_ctl_fsr_aexc[`FSR_OFC] |
1633
                             is_fpu_result & fpexc_ofc & ~fsr_tem_d1[`FSR_OFC];
1634
   assign fp_exc_w2[`FSR_NXA] = dp_ctl_fsr_aexc[`FSR_NXC] |
1635
                             is_fpu_result & fpexc_nxc & ~fsr_tem_d1[`FSR_NXC];
1636
 
1637
   assign ctl_dp_exc_w2[9:5] = fp_exc_w2[9:5];
1638
   // move, abs, etc will clear cexc, fpu_results will update, all else will leave unchanged
1639
   wire   update_cexc;
1640
   assign update_cexc = is_fpu_result | move_w2_vld;
1641
   assign ctl_dp_exc_w2[4:0] = ((update_cexc)? fp_exc_w2[4:0] & {5{is_fpu_result}}:
1642
                                dp_ctl_fsr_cexc[4:0]);
1643
 
1644
 
1645
 
1646
   ////////////////////////////////
1647
   // ECC control
1648
   ////////////////////////////////
1649
   // Generation of the parity bit for writes
1650
   wire [13:0] gen_synd_d1;
1651
   wire        gen_par_hi;
1652
   wire        gen_par_low;
1653
   wire [6:0]  error_inj_data;
1654
   output [13:0] ctl_frf_write_synd;
1655
   dff_s #(14) gen_synd_dff (.din({dp_ctl_synd_out_high[6:0],dp_ctl_synd_out_low[6:0]}),
1656
                           .q(gen_synd_d1[13:0]), .clk(clk), .se(se), .si(), .so());
1657
   assign  gen_par_hi = ^gen_synd_d1[13:7];
1658
   assign  gen_par_low = ^gen_synd_d1[6:0];
1659
   assign  ctl_frf_write_synd[13:0] = ({gen_par_hi,gen_synd_d1[12:7],gen_par_low,gen_synd_d1[5:0]} ^
1660
                                       {error_inj_data[6:0],error_inj_data[6:0]});
1661
   /////////////////////////////////
1662
   // error injection
1663
   /////////////////////////////////
1664
   // injection doesn't check for flush on wen
1665
   assign  inject_err_next = ifu_ffu_inj_frferr & rf_wen_next;
1666
   assign error_inj_data[6:0] = {7{inject_err}} & err_data[6:0];
1667
   dff_s #(7) err_data_dff(.din(ifu_exu_ecc_mask[6:0]),
1668
                     .q(err_data[6:0]),
1669
                     .clk(clk), .se(se), .si(), .so());
1670
   dff_s err_cntl(.din(inject_err_next),
1671
                .q(inject_err),
1672
                .clk(clk), .se(se), .si(), .so());
1673
   // speculate on error injection (don't check flush_pipe etc)
1674
   assign ffu_ifu_inj_ack = inject_err;
1675
 
1676
 
1677
   // check the upper half on a double or a single with an even reg num
1678
   // check the lower half on a double or a single with an odd reg num
1679
   // ecc block will run on frf input for reads
1680
   // otherwise it will run on the rd_data
1681
   assign check_ecc_next = ren_rs2_m | fst_e | ren_rs1_w | bst_issue_c3_next;
1682
   dff_s check_ecc_dff(.din(check_ecc_next), .clk(clk), .q(ctl_dp_ecc_sel_frf),
1683
                     .se(se), .si(), .so());
1684
   // rs1 will not be checked if a ce was detected on rs2.  If there was a ue on rs2
1685
   // rs1 will be checked and a ce will be corrected, but the error on rs2 will be logged
1686
   assign chk_rs1_w2 = ren_rs1_w2;
1687
   assign chk_ecc_m[1] = fst_m & ~rd[0] & ~output_sel_fsr;
1688
   assign chk_ecc_m[0] = fst_m & (~dest_single | rd[0]) & ~output_sel_fsr;
1689
   assign chk_ecc_w[1] = ren_rs2_w & ~kill_eccchk_w & ~rs2[0];
1690
   assign chk_ecc_w[0] = ren_rs2_w & ~kill_eccchk_w & (~source_single | rs2[0]);
1691
   assign chk_ecc_w2[1] = chk_rs1_w2 & ~rs1[0];
1692
   assign chk_ecc_w2[0] = chk_rs1_w2 & (~source_single | rs1[0]);
1693
 
1694
   assign chk_ecc[1:0] = chk_ecc_m[1:0] | chk_ecc_w[1:0] | chk_ecc_w2[1:0] | {2{bst_issue_c3}};
1695
   dff_s #(2) chk_ecc_dff(.din(chk_ecc[1:0]), .clk(clk), .q(chk_ecc_prev[1:0]),
1696
                        .se(se), .si(), .so());
1697
 
1698
   assign     error_detected[1] = |dp_ctl_synd_out_high[5:0];
1699
   assign     error_detected[0] = |dp_ctl_synd_out_low[5:0];
1700
 
1701
   assign     possible_ue[1] = ~dp_ctl_synd_out_high[6] & chk_ecc[1];
1702
   assign     possible_ue[0] = ~dp_ctl_synd_out_low[6] & chk_ecc[0];
1703
   assign     ce[1] = dp_ctl_synd_out_high[6] & chk_ecc[1];
1704
   assign     ce[0] = dp_ctl_synd_out_low[6] & chk_ecc[0];
1705
 
1706
   assign rollback_fst_m = ((dp_ctl_synd_out_high[6] & chk_ecc_m[1] & ~disable_ce_m) |
1707
                        (dp_ctl_synd_out_low[6] & chk_ecc_m[0] & ~disable_ce_m));
1708
   dff_s rollback_m2w(.din(rollback_fst_m), .clk(clk), .q(rollback_fst_w), .se(se), .si(), .so());
1709
   dff_s #(2) possible_ue_dff(.din(possible_ue[1:0]), .clk(clk), .q(prev_poss_ue[1:0]),
1710
                            .se(se), .si(), .so());
1711
   dff_s #(2) ce_dff(.din(ce[1:0]), .clk(clk), .q(previous_ce[1:0]),
1712
                            .se(se), .si(), .so());
1713
   dff_s #(2) err_det_dff(.din(error_detected[1:0]), .clk(clk), .q(prev_err_detected[1:0]),
1714
                            .se(se), .si(), .so());
1715
   assign previous_ue = |(prev_err_detected[1:0] & prev_poss_ue[1:0]);
1716
 
1717
   dff_s #(2) ecc_wen1_dff(.din(ecc_wen_gen_next[1:0]), .clk(clk), .q(ecc_wen_gen[1:0]),
1718
                        .se(se), .si(), .so());
1719
   dff_s #(2) ecc_wen2_dff(.din(ecc_wen_next[1:0]), .clk(clk), .q(ecc_wen[1:0]),
1720
                        .se(se), .si(), .so());
1721
   // if the ecc error was in the m stage we need to check for a kill
1722
   // if the ecc error was in the w stage we need to check flush
1723
   // ECC errors on rs1 will not be written back to the frf.  The data that is used will be corrected.
1724
   assign ecc_wen_gen_next[1:0] = previous_ce[1:0] &
1725
          {2{bst_issue_c4 | fst_ce_w | rollback_rs2_w2 | rollback_rs1_w3}};
1726
   assign ecc_wen_next = ecc_wen_gen[1:0] & {2{~(fst_ce_w2 & flush_w2)}};
1727
 
1728
   // pass along ce and ue so trap can be signalled to ffu and tlu
1729
   // if disable_ce_m then don't tell ifu reissue ce.  Instead convert to a ue.
1730
   dff_s disable_ce_e2m(.din(ifu_exu_disable_ce_e), .clk(clk), .q(disable_ce_m),
1731
                      .se(se), .si(), .so());
1732
   dff_s disable_ce_m2w(.din(disable_ce_m), .clk(clk), .q(disable_ce_w),
1733
                      .se(se), .si(), .so());
1734
   assign fst_ce_w = rollback_fst_w & ~kill_eccchk_w;
1735
   assign fst_ue_w = fst_w & (previous_ue | (disable_ce_w & |(previous_ce[1:0])))  & ~kill_eccchk_w;
1736
   assign rollback_rs2_w2 = (ren_rs2_w2 & ~flush_w2 & |previous_ce[1:0]
1737
                             & ~rolled_back);
1738
   assign rs2_ce_w2 = ren_rs2_w2 & |previous_ce[1:0] & ~rolled_back & ~previous_ue;
1739
   assign rs2_ue_w2 = ren_rs2_w2 & (previous_ue | (rolled_back & |previous_ce[1:0]));
1740
   // must check for flush because eccchk doesn't do this
1741
   assign rs2_fst_ce_w2_vld = (rs2_ce_w2 | fst_ce_w2) & ~flush_w2;
1742
   assign rs2_fst_ue_w2_vld = (rs2_ue_w2 | fst_ue_w2) & ~flush_w2;
1743
   dff_s ce_w2w2(.din(fst_ce_w), .clk(clk), .q(fst_ce_w2),
1744
               .se(se), .si(), .so());
1745
   dff_s ue_w2w2(.din(fst_ue_w), .clk(clk), .q(fst_ue_w2),
1746
               .se(se), .si(), .so());
1747
   dff_s ce_w22w3(.din(rs2_fst_ce_w2_vld), .clk(clk), .q(rs2_fst_ce_w3),
1748
               .se(se), .si(), .so());
1749
   dff_s ue_w22w3(.din(rs2_fst_ue_w2_vld), .clk(clk), .q(rs2_fst_ue_w3),
1750
               .se(se), .si(), .so());
1751
 
1752
   assign rs1_ce_w3 = ren_rs1_w3 & |previous_ce[1:0] & ~previous_ue & ~rolled_back;
1753
   assign rollback_rs1_w3 = rs1_ce_w3 & ~ue_trap_w3;
1754
   assign ce_w3 = (rs1_ce_w3 | rs2_fst_ce_w3);
1755
   assign ue_w3 = (ren_rs1_w3 & (previous_ue | (rolled_back & |previous_ce[1:0]))) | rs2_fst_ue_w3;
1756
 
1757
   assign ffu_ifu_ecc_ce_w2 = (ce_w3 | bst_ce_c4);
1758
   assign ffu_ifu_ecc_ue_w2 = (ue_w3 | bst_ue_c4);
1759
 
1760
   // error logging signals.  The error register priority is fst, bst, rs1_ue, rs2_ue, rs1_ce, rs2_ce
1761
   assign log_new_err = (ren_rs2_w2 | bst_issue_c4 | fst_w |
1762
                         (ren_rs1_w3 & previous_ue) | (rs1_ce_w3 & ~rs2_fst_ue_w3));
1763
   assign new_err_reg[5:0] = fst_w ?        rd[5:0]:
1764
                             bst_issue_c4 ? bst_rs[5:0]:
1765
                             ren_rs2_w2 ?    rs2[5:0]:
1766
                                            rs1[5:0];
1767
   assign err_reg_next[5:0] = (log_new_err) ? new_err_reg[5:0] : err_reg_d1[5:0];
1768
   dff_s #(6) err_reg_dff(.din(err_reg_next[5:0]), .clk(clk), .q(err_reg_d1[5:0]),
1769
                        .se(se), .si(), .so());
1770
   assign ffu_ifu_err_reg_w2[5:0] = err_reg_d1[5:0];
1771
 
1772
   // storage of error syndrome for logging
1773
   // For singles the invalid half of the syndrome is zeroed out.
1774
   // The syndrome reported to the ifu will be latched until a new error is detected
1775
   assign      new_err_synd[13:7] = gen_synd_d1[13:7] & {7{chk_ecc_prev[1]}};
1776
   assign      new_err_synd[6:0] = gen_synd_d1[6:0] & {7{chk_ecc_prev[0]}};
1777
   assign      err_synd_next[13:0] = (log_new_err)? new_err_synd: err_synd_d1;
1778
   dff_s #(14) err_synd_d1ff(.din(err_synd_next[13:0]), .clk(clk), .q(err_synd_d1[13:0]),
1779
                          .se(se), .si(), .so());
1780
   assign      ffu_ifu_err_synd_w2[13:0] = err_synd_d1[13:0];
1781
 
1782
   // kill moves and fpu ops
1783
   assign ecc_kill_rs2_w2 = rollback_rs2_w2 | (rs2_ue_w2 & nceen);
1784
 
1785
 
1786
   // pipe along enable signal for ue traps
1787
   assign nceen_next = (any_op_e)? ifu_exu_nceen_e: (nceen & ~rollback_fst_w);
1788
   dff_s nceen_dff(.din(nceen_next), .clk(clk), .q(nceen),
1789
                 .se(se), .si(), .so());
1790
   assign ue_trap_w3 = (ue_w3 | bst_ue_c4) & nceen;
1791
 
1792
   // signals for killing stores on ecc
1793
   // use this to kill any rs2/rd ce   
1794
   assign ffu_ifu_fst_ce_w = rollback_fst_w;
1795
 
1796
   // These signals kill the entry in the store buffer for any ce or trapping ue.  Very critical timing.
1797
   assign possible_kill_st_ce_m = ((fst_m & ~output_sel_fsr & ~(disable_ce_m & ~nceen)) |
1798
                                   (bst_issue_c3 & ~(fixed_bst_ce & ~nceen)));
1799
   assign possible_kill_st_ue_m = (fst_m & ~output_sel_fsr & nceen | bst_issue_c3 & nceen);
1800
   assign kill_st_ce_w = (|previous_ce[1:0]) & possible_kill_st_ce_w;
1801
   assign ffu_lsu_kill_fst_w = (previous_ue)? possible_kill_st_ue_w: kill_st_ce_w;
1802
   dff_s kill_fst_ce_dff(.din(possible_kill_st_ce_m), .clk(clk), .q(possible_kill_st_ce_w),
1803
                       .se(se), .si(), .so());
1804
   dff_s kill_fst_ue_dff(.din(possible_kill_st_ue_m), .clk(clk), .q(possible_kill_st_ue_w),
1805
                       .se(se), .si(), .so());
1806
 
1807
   // rollback signals
1808
   assign rollback_c1_next = rollback_rs2_w2 | rollback_rs1_w3;
1809
   dffr_s #(3) rollback_dff(.din({rollback_c1_next,rollback_c1_vld,rollback_c2}),
1810
                         .q({rollback_c1, rollback_c2, rollback_c3}),
1811
                         .clk(clk), .se(se), .si(), .so(), .rst(reset));
1812
   // if both rs1 and rs2 rollback then the state machine needs to start on rs1
1813
   assign rollback_c1_vld = rollback_c1 & ~ue_trap_w3 & ~rollback_rs1_w3;
1814
 
1815
   assign rolled_back_next = rollback_c1_vld | rolled_back & ~any_op_e;
1816
   dffr_s rollback_state(.din(rolled_back_next), .q(rolled_back),
1817
                        .rst(reset), .clk(clk),
1818
                        .se(se), .si(), .so());
1819
 
1820
   //////////////////////////////
1821
   // Performance counter signals
1822
   //////////////////////////////
1823
   assign ffu_tlu_fpu_tid[1:0] = tid[1:0] & {2{is_fpu_result}}; // don't toggle wire if not needed
1824
   assign ffu_tlu_fpu_cmplt = is_fpu_result;
1825
 
1826
   sparc_ffu_ctl_visctl visctl(
1827
                               .illegal_vis_e(illegal_vis_e),
1828
                               .vis_nofrf_e(vis_nofrf_e),
1829
                               .visop_e (visop_e),
1830
                               .visop_m (visop_m),
1831
                               .visop_w_vld (visop_w_vld),
1832
                               .vis_wen_next (vis_wen_next),
1833
                               .ifu_ffu_rnd_e(frs2_e[2:0]),
1834
                               .fpu_rnd (fpu_rnd[1:0]),
1835
                               .vis_result(vis_result),
1836
                               /*AUTOINST*/
1837
                               // Outputs
1838
                               .ctl_vis_sel_add(ctl_vis_sel_add),
1839
                               .ctl_vis_sel_log(ctl_vis_sel_log),
1840
                               .ctl_vis_sel_align(ctl_vis_sel_align),
1841
                               .ctl_vis_add32(ctl_vis_add32),
1842
                               .ctl_vis_subtract(ctl_vis_subtract),
1843
                               .ctl_vis_cin(ctl_vis_cin),
1844
                               .ctl_vis_align0(ctl_vis_align0),
1845
                               .ctl_vis_align2(ctl_vis_align2),
1846
                               .ctl_vis_align4(ctl_vis_align4),
1847
                               .ctl_vis_align6(ctl_vis_align6),
1848
                               .ctl_vis_align_odd(ctl_vis_align_odd),
1849
                               .ctl_vis_log_sel_pass(ctl_vis_log_sel_pass),
1850
                               .ctl_vis_log_sel_nand(ctl_vis_log_sel_nand),
1851
                               .ctl_vis_log_sel_nor(ctl_vis_log_sel_nor),
1852
                               .ctl_vis_log_sel_xor(ctl_vis_log_sel_xor),
1853
                               .ctl_vis_log_invert_rs1(ctl_vis_log_invert_rs1),
1854
                               .ctl_vis_log_invert_rs2(ctl_vis_log_invert_rs2),
1855
                               .ctl_vis_log_constant(ctl_vis_log_constant),
1856
                               .ctl_vis_log_pass_const(ctl_vis_log_pass_const),
1857
                               .ctl_vis_log_pass_rs1(ctl_vis_log_pass_rs1),
1858
                               .ctl_vis_log_pass_rs2(ctl_vis_log_pass_rs2),
1859
                               .ffu_exu_rsr_data_hi_m(ffu_exu_rsr_data_hi_m[31:0]),
1860
                               .ffu_exu_rsr_data_mid_m(ffu_exu_rsr_data_mid_m[2:0]),
1861
                               .ffu_exu_rsr_data_lo_m(ffu_exu_rsr_data_lo_m[7:0]),
1862
                               .ctl_dp_wsr_data_w2(ctl_dp_wsr_data_w2[36:0]),
1863
                               .ctl_dp_gsr_wsr_w2(ctl_dp_gsr_wsr_w2[3:0]),
1864
                               .ctl_dp_thr_e(ctl_dp_thr_e[3:0]),
1865
                               // Inputs
1866
                               .clk     (clk),
1867
                               .se      (se),
1868
                               .reset   (reset),
1869
                               .opf     (opf[8:0]),
1870
                               .tid_w2  (tid_w2[1:0]),
1871
                               .tid_e   (tid_e[1:0]),
1872
                               .tid     (tid[1:0]),
1873
                               .kill_w  (kill_w),
1874
                               .ifu_tlu_sraddr_d(ifu_tlu_sraddr_d[6:0]),
1875
                               .exu_ffu_wsr_inst_e(exu_ffu_wsr_inst_e),
1876
                               .exu_ffu_gsr_align_m(exu_ffu_gsr_align_m[2:0]),
1877
                               .exu_ffu_gsr_rnd_m(exu_ffu_gsr_rnd_m[2:0]),
1878
                               .exu_ffu_gsr_mask_m(exu_ffu_gsr_mask_m[31:0]),
1879
                               .exu_ffu_gsr_scale_m(exu_ffu_gsr_scale_m[4:0]),
1880
                               .dp_ctl_fsr_rnd(dp_ctl_fsr_rnd[1:0]),
1881
                               .flush_w2(flush_w2),
1882
                               .thr_match_mw2(thr_match_mw2),
1883
                               .thr_match_ww2(thr_match_ww2),
1884
                               .ifu_tlu_inst_vld_w(ifu_tlu_inst_vld_w),
1885
                               .ue_trap_w3(ue_trap_w3),
1886
                               .frs1_e  (frs1_e[4:0]),
1887
                               .frs2_e  (frs2_e[4:0]),
1888
                               .frd_e   (frd_e[4:0]),
1889
                               .rollback_c3(rollback_c3),
1890
                               .rollback_rs2_w2(rollback_rs2_w2),
1891
                               .visop   (visop),
1892
                               .rollback_rs1_w3(rollback_rs1_w3),
1893
                               .dp_ctl_gsr_mask_e(dp_ctl_gsr_mask_e[31:0]),
1894
                               .dp_ctl_gsr_scale_e(dp_ctl_gsr_scale_e[4:0]));
1895
 
1896
endmodule // sparc_ffu_ctl

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