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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: sparc_ifu_errctl.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

////////////////////////////////////////////////////////////////////////

/*

//  Module Name:  sparc_ifu_errctl

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

`include "lsu.h"

module sparc_ifu_errctl(/*AUTOARG*/

   // Outputs

   erc_erd_pgsz_b0, erc_erd_pgsz_b1, ifu_lsu_asi_rd_unc,

   ifu_lsu_ldxa_tid_w2, ifu_lsu_ldxa_data_vld_w2,

   ifu_lsu_fwd_data_vld, ifu_lsu_error_inj, ifu_exu_ecc_mask,

   ifu_exu_inj_irferr, ifu_ffu_inj_frferr, ifu_exu_nceen_e,

   ifu_lsu_nceen, ifu_spu_nceen, erb_fcl_spu_uetrap,

   erb_ifq_itlberr_s1, erb_ifq_ifeterr_d1, erb_dtu_ifeterr_d1,

   erb_fcl_itlb_ce_d1, erb_fcl_ce_trapvec, erb_fcl_ue_trapvec,

   erb_fcl_ifet_uevec_d1, erc_erd_errstat_asidata,

   erc_erd_errinj_asidata, erc_erd_erren_asidata,

   erc_erd_eadr0_sel_irf_l, erc_erd_eadr0_sel_itlb_l,

   erc_erd_eadr0_sel_frf_l, erc_erd_eadr0_sel_lsu_l,

   erc_erd_asiway_s1_l, erc_erd_eadr1_sel_pcd1_l,

   erc_erd_eadr1_sel_l1pa_l, erc_erd_eadr1_sel_l2pa_l,

   erc_erd_eadr1_sel_other_l, erc_erd_eadr2_sel_mx1_l,

   erc_erd_eadr2_sel_wrt_l, erc_erd_eadr2_sel_mx0_l,

   erc_erd_eadr2_sel_old_l, erc_erd_asi_thr_l,

   erc_erd_asisrc_sel_icd_s_l, erc_erd_asisrc_sel_misc_s_l,

   erc_erd_asisrc_sel_err_s_l, erc_erd_asisrc_sel_itlb_s_l,

   erc_erd_errasi_sel_en_l, erc_erd_errasi_sel_stat_l,

   erc_erd_errasi_sel_inj_l, erc_erd_errasi_sel_addr_l,

   erc_erd_miscasi_sel_ict_l, erc_erd_miscasi_sel_imask_l,

   erc_erd_miscasi_sel_other_l, erc_erd_ld_imask, erb_reset, so,

   // Inputs

   rclk, se, si, arst_l, grst_l, erd_erc_tte_pgsz, icv_itlb_valid_f,

   fcl_erb_ievld_s1, fcl_erb_tevld_s1, fcl_erb_immuevld_s1,

   fcl_erb_inst_issue_d, fcl_erb_inst_vld_d1, ifu_tlu_inst_vld_w,

   ifu_lsu_thrid_s, fcl_erb_asi_tid_f, ifq_fcl_asi_tid_bf,

   fcl_erb_clear_iferr, fcl_erb_itlbrd_vld_s, fcl_erb_itlbrd_data_s,

   erd_erc_tagpe_s1, erd_erc_nirpe_s1, erd_erc_fetpe_s1,

   erd_erc_tlbt_pe_s1, erd_erc_tlbd_pe_s1, tlu_lsu_pstate_priv, tlu_hpstate_priv,

   lsu_ifu_dtlb_data_su, lsu_ifu_dtlb_data_ue, lsu_ifu_dtlb_tag_ue,

   lsu_ifu_dcache_data_perror, lsu_ifu_dcache_tag_perror,

   lsu_ifu_l2_unc_error, lsu_ifu_l2_corr_error, lsu_ifu_io_error,

   lsu_ifu_error_tid, spu_ifu_unc_err_w1, spu_ifu_mamem_err_w1,

   spu_ifu_corr_err_w2, spu_ifu_int_w2, spu_ifu_ttype_tid_w2,

   lsu_ifu_inj_ack, ffu_ifu_ecc_ce_w2, ffu_ifu_ecc_ue_w2,

   ffu_ifu_inj_ack, ffu_ifu_tid_w2, exu_ifu_ecc_ce_m,

   exu_ifu_ecc_ue_m, exu_ifu_inj_ack, ifq_erb_ue_rep, ifq_erb_ce_rep,

   ifq_erb_l2_ue, ifq_erb_io_ue, ifq_erb_ifet_ce, ifq_erb_l2err_tid,

   ifq_erb_rdtag_f, ifq_erb_rdinst_f, ifq_erb_asi_erren_i2,

   ifq_erb_asi_errstat_i2, ifq_erb_asi_errinj_i2,

   ifq_erb_asi_erraddr_i2, ifq_erb_asi_imask_i2, ifq_erb_asiwr_i2,

   ifq_fcl_asird_bf, ifq_erb_fwdrd_bf, ifq_erb_asidata_i2,

   ifq_erb_asiway_f

   );

   input        rclk,

                se,

                si,

                arst_l,

                grst_l;

   input [2:0]  erd_erc_tte_pgsz;

   input [3:0]  icv_itlb_valid_f;

   input        fcl_erb_ievld_s1,

                            fcl_erb_tevld_s1,

                            fcl_erb_immuevld_s1;

   input        fcl_erb_inst_issue_d;

   input        fcl_erb_inst_vld_d1;

   input        ifu_tlu_inst_vld_w;

   input [1:0]  ifu_lsu_thrid_s,

                            fcl_erb_asi_tid_f,

                            ifq_fcl_asi_tid_bf;

   input [3:0]  fcl_erb_clear_iferr;

   input        fcl_erb_itlbrd_vld_s,

                            fcl_erb_itlbrd_data_s;

   input [3:0]  erd_erc_tagpe_s1;

   input        erd_erc_nirpe_s1,

                            erd_erc_fetpe_s1;

   input [1:0]  erd_erc_tlbt_pe_s1,

                            erd_erc_tlbd_pe_s1;

   input [3:0]  tlu_lsu_pstate_priv;

   input [3:0]  tlu_hpstate_priv;

   input        lsu_ifu_dtlb_data_su,

                            lsu_ifu_dtlb_data_ue,

                            lsu_ifu_dtlb_tag_ue,

                            lsu_ifu_dcache_data_perror,

                            lsu_ifu_dcache_tag_perror,

                            lsu_ifu_l2_unc_error,

                            lsu_ifu_l2_corr_error,

                            lsu_ifu_io_error;

   input [1:0]  lsu_ifu_error_tid;

   input        spu_ifu_unc_err_w1,  // 1 cycle earlier for timing reasons

                spu_ifu_mamem_err_w1,// 1 cycle earlier for timing reasons

                spu_ifu_corr_err_w2,

                spu_ifu_int_w2;

   input [1:0]  spu_ifu_ttype_tid_w2;

   input [3:0]  lsu_ifu_inj_ack;

   input        ffu_ifu_ecc_ce_w2;

   input        ffu_ifu_ecc_ue_w2;

   input        ffu_ifu_inj_ack;

   input [1:0]  ffu_ifu_tid_w2;

   input        exu_ifu_ecc_ce_m,

                            exu_ifu_ecc_ue_m;

   input        exu_ifu_inj_ack;

   input        ifq_erb_ue_rep;

   input        ifq_erb_ce_rep;

   input        ifq_erb_l2_ue;

   input        ifq_erb_io_ue;

   input        ifq_erb_ifet_ce;

   input [1:0]  ifq_erb_l2err_tid;

   input        ifq_erb_rdtag_f;

   input        ifq_erb_rdinst_f;

   input        ifq_erb_asi_erren_i2;

   input        ifq_erb_asi_errstat_i2;

   input        ifq_erb_asi_errinj_i2;

   input        ifq_erb_asi_erraddr_i2;

   input        ifq_erb_asi_imask_i2;

   input        ifq_erb_asiwr_i2;

   input        ifq_fcl_asird_bf;

   input        ifq_erb_fwdrd_bf;

   input [31:0] ifq_erb_asidata_i2;

   input [1:0]  ifq_erb_asiway_f;

   output       erc_erd_pgsz_b0;

   output       erc_erd_pgsz_b1;

   output       ifu_lsu_asi_rd_unc;

   output [1:0] ifu_lsu_ldxa_tid_w2;

   output       ifu_lsu_ldxa_data_vld_w2;

   output       ifu_lsu_fwd_data_vld;

   output [3:0] ifu_lsu_error_inj;

   output [7:0] ifu_exu_ecc_mask;

   output       ifu_exu_inj_irferr;

   output       ifu_ffu_inj_frferr;

   output       ifu_exu_nceen_e;

   output [3:0] ifu_lsu_nceen;

   output [3:0] ifu_spu_nceen;  //  copy going north

   output [3:0] erb_fcl_spu_uetrap;

   output       erb_ifq_itlberr_s1;

   output       erb_ifq_ifeterr_d1;

   output       erb_dtu_ifeterr_d1;

   output       erb_fcl_itlb_ce_d1;

   output [3:0] erb_fcl_ce_trapvec;

   output [3:0] erb_fcl_ue_trapvec;

   output [3:0] erb_fcl_ifet_uevec_d1;

   output [22:0] erc_erd_errstat_asidata;

   output [31:0] erc_erd_errinj_asidata;

   output [1:0]  erc_erd_erren_asidata;

   // mux selects

   output [3:0]  erc_erd_eadr0_sel_irf_l,

                             erc_erd_eadr0_sel_itlb_l,

                             erc_erd_eadr0_sel_frf_l,

                             erc_erd_eadr0_sel_lsu_l;

   output [3:0]  erc_erd_asiway_s1_l;

   output [3:0]  erc_erd_eadr1_sel_pcd1_l,

                             erc_erd_eadr1_sel_l1pa_l,

                             erc_erd_eadr1_sel_l2pa_l,

                             erc_erd_eadr1_sel_other_l;

   output [3:0]  erc_erd_eadr2_sel_mx1_l,

                             erc_erd_eadr2_sel_wrt_l,

                             erc_erd_eadr2_sel_mx0_l,

                             erc_erd_eadr2_sel_old_l;

   output [3:0]  erc_erd_asi_thr_l;

   output        erc_erd_asisrc_sel_icd_s_l,

                             erc_erd_asisrc_sel_misc_s_l,

                             erc_erd_asisrc_sel_err_s_l,

                             erc_erd_asisrc_sel_itlb_s_l;

   output        erc_erd_errasi_sel_en_l,

                             erc_erd_errasi_sel_stat_l,

                             erc_erd_errasi_sel_inj_l,

                             erc_erd_errasi_sel_addr_l;

   output        erc_erd_miscasi_sel_ict_l,

                             erc_erd_miscasi_sel_imask_l,

                             erc_erd_miscasi_sel_other_l;

   output        erc_erd_ld_imask;

   output        erb_reset,

                 so;

   // Local Signals

   wire          spu_unc_err_w2,

                 spu_mamem_err_w2;

   wire          lsu_dtlb_data_su,

                             lsu_dtlb_data_ue,

                             lsu_dtlb_tag_ue,

                             lsu_dcache_data_perror,

                             lsu_dcache_tag_perror,

                             lsu_l2_unc_error,

                             lsu_l2_corr_error,

                             lsu_io_error;

   wire [1:0]    lsu_error_tid;

   wire [3:0]    valid_s1;

   wire [1:0]    tid_d,

                 ffu_tid_w3,

                 l2ierr_tid,

                 spu_tid_w2,

                 asi_tid_w2,

                             asi_tid_s1;

   wire [3:0]    thr_e,

                 thr_d,

                             thr_d1,

                             thr_m,

                             thr_w,

                 ffu_thr_w3,

                             asi_thr_s,

                 asi_thr_w2,

                             asi_thr_i2,

                             thr_lsu_err,

                 thr_spu_err,

                             thr_l2ie;

   wire          itlb_feterr_s1,

                             tlb_feterr_d1,

                 itlb_errtr_s1_l,

                 itlb_errtr_d1_l;

   wire          tlb_fet_ce_d1,

                             tlb_fet_ue_d1;

   wire [3:0]    alltag_err_s1;

   wire          itlb_tagerr_s1,

                             itlb_dataerr_s1,

                             insterr_d1,

                 insterr_s1,

                             insterr_qual_d1,

                             ictagerr_s1,

                             ictagerr_d1,

                             ictagerr_qual_d1;

   wire          asi_daterr_d1,

                             asi_tagerr_d1,

                             asi_rd_err_d1;

   wire          asi_ttevld_s1,

                             asi_tdevld_s1;

   wire [3:0]    any_tlbasi_err;

   wire [3:0]    dmdu,

                             dmdu_nxt,

                             dmsu,

                             dmsu_nxt,

                             dmt,

                             dmt_nxt,

                             ddc,

                             ddc_nxt,

                             dtc,

                             dtc_nxt,

                             ldau,

                             ldau_nxt,

                             ncu,

                             ncu_nxt,

                 mau,

                 mau_nxt,

                             any_lsu_err,

                             any_lsu_ue,

                             any_lsu_ce,

                 any_spu_ce,

                 any_spu_ue,

                             imt,

                             imt_nxt,

                             frc,

                             frc_nxt,

                             irc,

                             irc_nxt,

                             fru,

                             fru_nxt,

                             iru,

                             iru_nxt,

                             any_rf_err,

                             any_rf_ce,

                             any_rf_ue,

                             any_irf_err,

                             any_frf_err,

                             idc,

                             idc_nxt,

                             itc,

                             itc_nxt,

                             imdu,

                             imdu_nxt,

                             any_err_vld,

                             any_ue_vld,

//                           any_ce_vld,

                             early_idc,

                             early_idc_nxt,

                             early_itc,

                             early_itc_nxt,

                             early_imdu,

                             early_imdu_nxt,

                             early_ldau,

                             early_ldau_nxt,

                             early_ncu,

                             early_ncu_nxt,

                             early_l2ce,

                             early_l2ce_nxt,

                             any_ifu_ce,

                             any_ifu_ue,

                             any_ifu_err,

                             any_iferr_vld;

   wire [3:0]    meu,

                             meu_nxt,

                             mec,

                             mec_nxt,

                             priv,

                             priv_nxt,

                             early_meu,

                             early_meu_nxt,

                             early_mec,

                             early_mec_nxt,

                             early_priv,

                             early_priv_nxt;

   wire [22:0]   err_stat0,

                             err_stat1,

                             err_stat2,

                             err_stat3;

   wire [3:0]    ifet_ce_vld,

                 ifet_ue_vld;

   wire [3:0]    l2if_unc_err,

                             l2if_corr_err;

   wire [3:0]    ce_trapvec,

                             ue_trapvec,

                             ifu_ce_trap;

   wire          wrt_errinj_i2;

   wire [7:0]    ecc_mask,

                             ecc_mask_nxt;

   wire [1:0]    errinj_ctl,

                             errinj_ctl_nxt;

   wire [5:0]    errinj_vec,

                             errinj_vec_nxt,

                             corr_errinj_vec;

//   wire [3:0]    icache_pa_err_d1;

   wire          irf_ce_w,

                 irf_ce_unq,

                             irf_ue_w,

                 irf_ue_unq;

   wire [3:0]    sel_lsu_err,

                             sel_ifuspu_err,

                             sel_rftlb_err;

   wire          clr_err_qual_e,

                 clr_elyff_e,

                 clr_elyff_m,

                 clr_elyff_w;

   wire [3:0]    early_err_vec_e,

                             clear_ely_reg_w,

                             mov_ely_reg_w;

   wire [3:0]    clear_iferr_d1;

   wire [1:0]    asi_way_s1;

   wire [3:0]    dec_asiway_s1;

   wire [3:0]    asi_wrt_err_stat,

                             asi_wrt_err_en,

//                           asi_wrt_err_inj,

                             asi_wrt_err_addr;

   wire          dmdu_wrt_data,

                             dmsu_wrt_data,

                             imdu_wrt_data,

                             idc_wrt_data,

                             itc_wrt_data,

                             ddc_wrt_data,

                             dtc_wrt_data,

                             imt_wrt_data,

                             dmt_wrt_data,

                             ldau_wrt_data,

                             ncu_wrt_data,

                 mau_wrt_data,

                             fru_wrt_data,

                             frc_wrt_data,

                             iru_wrt_data,

                             irc_wrt_data,

                             meu_wrt_data,

                             mec_wrt_data,

                             priv_wrt_data;

   wire          nceen_wrt_data,

                             ceen_wrt_data;

   wire [3:0]    ceen,

                             ceen_nxt,

                             nceen,

                             nceen_nxt;

   wire          nceen_d;

   wire          rdtag_s,

                             rdinst_s,

                             asi_erren_f,

                             asi_errstat_f,

                             asi_errinj_f,

                             asi_erraddr_f,

                             asi_imask_f,

                             asi_erren_s,

                             asi_errstat_s,

                             asi_errinj_s,

                             asi_erraddr_s,

                             asi_imask_s;

   wire          asird_f,

                             asird_s;

   wire          fwdrd_f,

                 fwdrd_s,

                 asifwd_rd_s,

                 rdinst_f,

                 fwdrd_d;

   wire          ldxa_data_vld_s,

                 ldxa_data_vld_d;

   wire          err_asi_s;

   wire          erb_reset_l;

   wire          ffu_ce_w3;

   wire          ffu_ue_w3;

   wire [3:0]     any_lsu_ue_priv_state;

   wire [3:0]     any_priv_state;

   wire          clk;

//   

// Code Begins Here

//

   assign        clk = rclk;

   // reset buffer

   dffrl_async rstff(.din (grst_l),

                     .q   (erb_reset_l),

                     .clk (clk), .se(se), .si(), .so(),

                     .rst_l (arst_l));

   assign       erb_reset = ~erb_reset_l;

   // need to encode page size before sending it back

   assign erc_erd_pgsz_b0 = (erd_erc_tte_pgsz[2] |

                                    erd_erc_tte_pgsz[1] |

                              erd_erc_tte_pgsz[0]);

   assign erc_erd_pgsz_b1 = (~erd_erc_tte_pgsz[2] &

                                   erd_erc_tte_pgsz[1]);

   // Don't need this with SPARC_HPV_EN

   // default to tte_lock_d1 = 0

   // 05/30/03: tlb correctible errors disabled.

   // so treat as if lock = 1 and force ue.

//   dff #(1) lk_ff(.din (erd_erc_tte_lock_s1),

//                            .q   (tte_lock_d1),

//                            .clk (clk), .se(se), .si(), .so());

//-----------------------

// Basic pipeline signals

//-----------------------

   // thr_s1 also contains asi tid

   dff_s #(2) tidd_reg(.din (ifu_lsu_thrid_s),

                                 .q   (tid_d),

                                 .clk (clk), .se(se), .si(), .so());

   assign thr_d[0] = ~tid_d[1] & ~tid_d[0];

   assign thr_d[1] = ~tid_d[1] &  tid_d[0];

   assign thr_d[2] =  tid_d[1] & ~tid_d[0];

   assign thr_d[3] =  tid_d[1] &  tid_d[0];

   dff_s #(4) thre_reg(.din (thr_d),

                                 .q   (thr_e),

                                 .clk (clk), .se(se), .si(), .so());

   assign thr_d1 = thr_e;

   dff_s #(4) thrm_reg(.din (thr_e),

                                 .q   (thr_m),

                                 .clk (clk),  .se(se), .si(), .so());

   dff_s #(4) thrw_reg(.din (thr_m),

                                 .q   (thr_w),

                                 .clk (clk),  .se(se), .si(), .so());

//-----------------------------

// lsu flops (added for timing)

//-----------------------------

   // all the lsu signals go to the final mux in the errdp, to help

   // with timing.  This is no longer necessary, in fact it is no

   // longer desired, since we have added the flop below to stage all

   // the lsu signals.  However, the design is not changed, to save

   // the extra effort in physical composition to rip up the errdp.

   dff_s #(10) lspipe_reg(.din ({lsu_ifu_dtlb_data_su,

                               lsu_ifu_dtlb_data_ue,

                               lsu_ifu_dtlb_tag_ue,

                               lsu_ifu_dcache_data_perror,

                               lsu_ifu_dcache_tag_perror,

                               lsu_ifu_l2_unc_error,

                               lsu_ifu_l2_corr_error,

                               lsu_ifu_io_error,

                               lsu_ifu_error_tid[1:0]}),

                        .q   ({lsu_dtlb_data_su,

                               lsu_dtlb_data_ue,

                               lsu_dtlb_tag_ue,

                               lsu_dcache_data_perror,

                               lsu_dcache_tag_perror,

                               lsu_l2_unc_error,

                               lsu_l2_corr_error,

                               lsu_io_error,

                               lsu_error_tid[1:0]}),

                        .clk (clk), .se(se), .si(), .so());

   assign any_priv_state = tlu_lsu_pstate_priv | tlu_hpstate_priv;

   //Bug 6821: added so that lsu ue's errors pickup the delayed priv level

   dff_s #(4) lsu_priv_reg(.din (any_priv_state),

                        .q   (any_lsu_ue_priv_state),

                        .clk (clk), .se(se), .si(), .so());

   // thread from lsu

   assign thr_lsu_err[0] = ~lsu_error_tid[1] & ~lsu_error_tid[0];

   assign thr_lsu_err[1] = ~lsu_error_tid[1] &  lsu_error_tid[0];

   assign thr_lsu_err[2] =  lsu_error_tid[1] & ~lsu_error_tid[0];

   assign thr_lsu_err[3] =  lsu_error_tid[1] &  lsu_error_tid[0];

   // thread from spu

   // From Farnad: tid is ready several cycles before everything else.

   // In the ifu, I will assume 1 cycle before

   dff_s #(2) sptid_reg(.din (spu_ifu_ttype_tid_w2),

                      .q   (spu_tid_w2),

                      .clk (clk), .se(se), .so(), .si());

   dff_s #(2) spe1_reg(.din ({spu_ifu_unc_err_w1,

                            spu_ifu_mamem_err_w1}),

                      .q   ({spu_unc_err_w2,

                             spu_mamem_err_w2}),

                      .clk (clk), .se(se), .so(), .si());

   assign thr_spu_err[0] = ~spu_tid_w2[1] & ~spu_tid_w2[0];

   assign thr_spu_err[1] = ~spu_tid_w2[1] &  spu_tid_w2[0];

   assign thr_spu_err[2] =  spu_tid_w2[1] & ~spu_tid_w2[0];

   assign thr_spu_err[3] =  spu_tid_w2[1] &  spu_tid_w2[0];

   // thread from ifq

   dff_s #(2) ifqthr_reg(.din (ifq_erb_l2err_tid),

                       .q   (l2ierr_tid),

                       .clk (clk), .se(se), .so(), .si());

   assign thr_l2ie[0] = ~l2ierr_tid[1] & ~l2ierr_tid[0];

   assign thr_l2ie[1] = ~l2ierr_tid[1] &  l2ierr_tid[0];

   assign thr_l2ie[2] =  l2ierr_tid[1] & ~l2ierr_tid[0];

   assign thr_l2ie[3] =  l2ierr_tid[1] &  l2ierr_tid[0];

//---------------------------------------

// Error Detection -- icache errors

//---------------------------------------

   // itlb inst fetch errors

   assign itlb_feterr_s1 = (erd_erc_tlbd_pe_s1[0] ^ erd_erc_tlbd_pe_s1[1]) &

                                               fcl_erb_immuevld_s1;

   assign erb_ifq_itlberr_s1 = itlb_feterr_s1 & nceen_d;

   dff_s #(1) itfete_ff(.din (itlb_feterr_s1),

                                  .q   (tlb_feterr_d1),

                                  .clk (clk), .se(se), .si(), .so());

   assign itlb_errtr_s1_l = ~erb_ifq_itlberr_s1;

   dff_s #(1) itume_ff(.din (itlb_errtr_s1_l),

                                 .q   (itlb_errtr_d1_l),

                                 .clk (clk), .se(se), .si(), .so());

//   assign tlb_fet_ce_d1 = tlb_feterr_d1 & ~tte_lock_d1;

//   assign tlb_fet_ue_d1 = tlb_feterr_d1 & tte_lock_d1;

   assign tlb_fet_ce_d1 = 1'b0;

   assign tlb_fet_ue_d1 = tlb_feterr_d1;

   // instruction errors

//   assign insterr_s1 = (erd_erc_nirpe_s1 | erd_erc_fetpe_s1) & 

//                                         fcl_erb_ievld_s1;

//   dff #(1)  inserr_ff(.din (insterr_s1),

//                                 .q   (insterr_d1),

//                                 .clk (clk), .se(se), .si(), .so());

   assign insterr_s1 = (erd_erc_fetpe_s1 | erd_erc_nirpe_s1) &

                         fcl_erb_ievld_s1;

   dff_s #(1)  feterr_ff(.din (insterr_s1),

                                   .q   (insterr_d1),

                                   .clk (clk), .se(se), .si(), .so());

//   dff #(1)  nirerr_ff(.din (erd_erc_nirpe_s1),

//                                 .q   (nirpe_d1),

//                                 .clk (clk), .se(se), .si(), .so());

//   dff #(1)  ievld1_ff(.din (fcl_erb_ievld_s1),

//                                 .q   (ievld_d1),

//                                 .clk (clk), .se(se), .si(), .so());

   assign insterr_qual_d1 = insterr_d1 & ~tlb_feterr_d1;

   // tag errors

   dff_s #(4)  vld_reg(.din (icv_itlb_valid_f),

                                 .q   (valid_s1),

                                 .clk (clk), .se(se), .si(), .so());

   assign alltag_err_s1 = erd_erc_tagpe_s1 & valid_s1;

   assign ictagerr_s1 = (|alltag_err_s1[3:0]) & fcl_erb_tevld_s1;

   dff_s #(1)  itagerr_ff(.din (ictagerr_s1),

                                    .q   (ictagerr_d1),

                                    .clk (clk), .se(se), .si(), .so());

   assign  ictagerr_qual_d1 = ictagerr_d1 & ~insterr_d1 &

                                    ~tlb_feterr_d1;

   // Corrective action for IFU errors

   // force an imiss if there is a inst/tag parity error

   assign  erb_ifq_ifeterr_d1 = (ictagerr_d1 | insterr_d1) & itlb_errtr_d1_l;

   // moved qualification with inst_vld_d1 to the dtu.

   assign  erb_dtu_ifeterr_d1 = erb_ifq_ifeterr_d1;

   //assign  erb_dtu_ifeterr_d1 = erb_ifq_ifeterr_d1 & fcl_erb_inst_vld_d1;

//   assign  icache_pa_err_d1 = {4{ictagerr_d1 | insterr_d1}} & thr_d1;

   // force a tlbmiss if there is a correctible tlb data parity error

   assign  erb_fcl_itlb_ce_d1 = tlb_fet_ce_d1;

   // take a precise trap if there is an uncorrectible error

   assign  erb_fcl_ifet_uevec_d1 = ({4{tlb_fet_ue_d1 & fcl_erb_inst_vld_d1}} &

                                                            thr_d1  |

                                                            {4{ifq_erb_l2_ue | ifq_erb_io_ue}} &