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[/] [sparc64soc/] [trunk/] [T1-CPU/] [ifu/] [sparc_ifu_errdp.v] - Blame information for rev 5

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
2
// 
3
// OpenSPARC T1 Processor File: sparc_ifu_errdp.v
4
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6
// 
7
// The above named program is free software; you can redistribute it and/or
8
// modify it under the terms of the GNU General Public
9
// License version 2 as published by the Free Software Foundation.
10
// 
11
// The above named program is distributed in the hope that it will be 
12
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
// General Public License for more details.
15
// 
16
// You should have received a copy of the GNU General Public
17
// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19
// 
20
// ========== Copyright Header End ============================================
21
////////////////////////////////////////////////////////////////////////
22
/*
23
//  Module Name:  sparc_ifu_errdp
24
*/
25
////////////////////////////////////////////////////////////////////////
26
// Global header file includes
27
////////////////////////////////////////////////////////////////////////
28
 
29
`include "lsu.h"
30
`include "ifu.h"
31
 
32
module sparc_ifu_errdp(/*AUTOARG*/
33
   // Outputs
34
   so, ifu_lsu_ldxa_data_w2, erb_dtu_imask, erd_erc_tlbt_pe_s1,
35
   erd_erc_tlbd_pe_s1, erd_erc_tagpe_s1, erd_erc_nirpe_s1,
36
   erd_erc_fetpe_s1, erd_erc_tte_pgsz,
37
   // Inputs
38
   rclk, se, si, erb_reset, itlb_rd_tte_data, itlb_rd_tte_tag,
39
   itlb_ifq_paddr_s, wsel_fdp_fetdata_s1, wsel_fdp_topdata_s1,
40
   wsel_erb_asidata_s, ict_itlb_tags_f, icv_itlb_valid_f,
41
   lsu_ifu_err_addr, spu_ifu_err_addr_w2, fdp_erb_pc_f,
42
   exu_ifu_err_reg_m, exu_ifu_err_synd_m, ffu_ifu_err_reg_w2,
43
   ffu_ifu_err_synd_w2, tlu_itlb_rw_index_g, erc_erd_pgsz_b0,
44
   erc_erd_pgsz_b1, erc_erd_erren_asidata, erc_erd_errstat_asidata,
45
   erc_erd_errinj_asidata, ifq_erb_asidata_i2, ifq_erb_wrtag_f,
46
   ifq_erb_wrindex_f, erc_erd_asiway_s1_l, fcl_erb_itlbrd_data_s,
47
   erc_erd_ld_imask, erc_erd_asisrc_sel_icd_s_l,
48
   erc_erd_asisrc_sel_misc_s_l, erc_erd_asisrc_sel_err_s_l,
49
   erc_erd_asisrc_sel_itlb_s_l, erc_erd_errasi_sel_en_l,
50
   erc_erd_errasi_sel_stat_l, erc_erd_errasi_sel_inj_l,
51
   erc_erd_errasi_sel_addr_l, erc_erd_miscasi_sel_ict_l,
52
   erc_erd_miscasi_sel_imask_l, erc_erd_miscasi_sel_other_l,
53
   erc_erd_asi_thr_l, erc_erd_eadr0_sel_irf_l,
54
   erc_erd_eadr0_sel_itlb_l, erc_erd_eadr0_sel_frf_l,
55
   erc_erd_eadr0_sel_lsu_l, erc_erd_eadr1_sel_pcd1_l,
56
   erc_erd_eadr1_sel_l1pa_l, erc_erd_eadr1_sel_l2pa_l,
57
   erc_erd_eadr1_sel_other_l, erc_erd_eadr2_sel_mx1_l,
58
   erc_erd_eadr2_sel_wrt_l, erc_erd_eadr2_sel_mx0_l,
59
   erc_erd_eadr2_sel_old_l
60
   );
61
 
62
   input       rclk,
63
               se,
64
               si,
65
               erb_reset;
66
 
67
   input [42:0] itlb_rd_tte_data;   // this is in s1
68
   input [58:0] itlb_rd_tte_tag;    // this is in s1
69
   input [39:10] itlb_ifq_paddr_s;
70
   input [33:0] wsel_fdp_fetdata_s1,
71
                            wsel_fdp_topdata_s1;
72
   input [33:0] wsel_erb_asidata_s;
73
 
74
   input [`IC_TAG_ALL_HI:0] ict_itlb_tags_f;
75
   input [3:0]              icv_itlb_valid_f;
76
 
77
   input [47:4]  lsu_ifu_err_addr;
78
   input [39:4]  spu_ifu_err_addr_w2;
79
   input [47:0]  fdp_erb_pc_f;
80
 
81
   input [7:0]   exu_ifu_err_reg_m;
82
   input [7:0]   exu_ifu_err_synd_m;
83
   input [5:0]   ffu_ifu_err_reg_w2;
84
   input [13:0]  ffu_ifu_err_synd_w2;
85
   input [5:0]   tlu_itlb_rw_index_g;
86
 
87
   input         erc_erd_pgsz_b0,
88
                 erc_erd_pgsz_b1;
89
 
90
   input [1:0]   erc_erd_erren_asidata;
91
   input [22:0]  erc_erd_errstat_asidata;
92
   input [31:0]  erc_erd_errinj_asidata;
93
   input [47:0]  ifq_erb_asidata_i2;
94
 
95
   input [`IC_TAG_SZ-1:0] ifq_erb_wrtag_f;
96
   input [`IC_IDX_HI:4]   ifq_erb_wrindex_f;
97
 
98
   // mux selects
99
   input [3:0]  erc_erd_asiway_s1_l;
100
   input        fcl_erb_itlbrd_data_s;
101
   input        erc_erd_ld_imask;
102
 
103
   input        erc_erd_asisrc_sel_icd_s_l,
104
                            erc_erd_asisrc_sel_misc_s_l,
105
                            erc_erd_asisrc_sel_err_s_l,
106
                            erc_erd_asisrc_sel_itlb_s_l;
107
 
108
   input        erc_erd_errasi_sel_en_l,
109
                            erc_erd_errasi_sel_stat_l,
110
                            erc_erd_errasi_sel_inj_l,
111
                            erc_erd_errasi_sel_addr_l;
112
 
113
   input        erc_erd_miscasi_sel_ict_l,
114
                            erc_erd_miscasi_sel_imask_l,
115
                            erc_erd_miscasi_sel_other_l;
116
 
117
   input [3:0]  erc_erd_asi_thr_l;
118
 
119
   input [3:0]  erc_erd_eadr0_sel_irf_l,
120
                            erc_erd_eadr0_sel_itlb_l,
121
                            erc_erd_eadr0_sel_frf_l,
122
                            erc_erd_eadr0_sel_lsu_l;
123
 
124
   input [3:0]  erc_erd_eadr1_sel_pcd1_l,
125
                            erc_erd_eadr1_sel_l1pa_l,
126
                            erc_erd_eadr1_sel_l2pa_l,
127
                            erc_erd_eadr1_sel_other_l;
128
 
129
   input [3:0]  erc_erd_eadr2_sel_mx1_l,
130
                            erc_erd_eadr2_sel_wrt_l,
131
                            erc_erd_eadr2_sel_mx0_l,
132
                            erc_erd_eadr2_sel_old_l;
133
 
134
 
135
   output       so;
136
   output [63:0] ifu_lsu_ldxa_data_w2;
137
   output [38:0] erb_dtu_imask;
138
//   output [9:0]  erb_ifq_paddr_s;
139
 
140
   output [1:0]  erd_erc_tlbt_pe_s1,
141
                             erd_erc_tlbd_pe_s1;
142
   output [3:0]  erd_erc_tagpe_s1;
143
   output        erd_erc_nirpe_s1,
144
                             erd_erc_fetpe_s1;
145
 
146
   output [2:0]  erd_erc_tte_pgsz;
147
 
148
 
149
//   
150
// local signals   
151
//
152
 
153
   wire [47:4]   lsu_err_addr;
154
 
155
   wire [`IC_TAG_ALL_HI:0]  ictags_s1;
156
   wire [3:0]               icv_data_s1;
157
   wire [31:0]              tag_asi_data;
158
 
159
   wire [47:4]              t0_eadr_mx0_out,
160
                                        t1_eadr_mx0_out,
161
                                        t2_eadr_mx0_out,
162
                                        t3_eadr_mx0_out,
163
                                        t0_eadr_mx1_out,
164
                                        t1_eadr_mx1_out,
165
                                        t2_eadr_mx1_out,
166
                                        t3_eadr_mx1_out;
167
 
168
   wire [47:4]              t0_err_addr_nxt,
169
                                        t0_err_addr,
170
                                        t1_err_addr_nxt,
171
                                        t1_err_addr,
172
                                        t2_err_addr_nxt,
173
                                        t2_err_addr,
174
                                        t3_err_addr_nxt,
175
                                        t3_err_addr;
176
 
177
   wire [47:4]              err_addr_asidata;
178
 
179
   wire [63:0]              formatted_tte_data,
180
                                        formatted_tte_tag,
181
                                        tlb_asi_data,
182
                                        misc_asi_data,
183
                                        err_asi_data,
184
                            ldxa_data_s,
185
                            ldxa_data_d;
186
 
187
   wire [39:4]              paddr_s1,
188
                                        paddr_d1;
189
 
190
   wire [39:4]              ifet_addr_f;
191
 
192
   wire [47:0]              pc_s1;
193
   wire [47:4]              pc_d1;
194
   wire [7:0]               irfaddr_w,
195
                            irfsynd_w;
196
   wire                     irfaddr_4_w;
197
   wire [5:0]               itlb_asi_index;
198
 
199
   wire [38:0]              imask_next;
200
 
201
   wire                     clk;
202
 
203
 
204
//
205
// Code Begins Here
206
//
207
   assign                   clk = rclk;
208
 
209
//-------------
210
// Tags
211
//-------------   
212
   dff_s #(`IC_TAG_ALL) tags_reg(.din (ict_itlb_tags_f),
213
                                           .q   (ictags_s1),
214
                                           .clk (clk),
215
                                           .se  (se), .si(), .so());
216
 
217
   dff_s #(4) vbits_reg(.din (icv_itlb_valid_f[3:0]),
218
                                  .q   (icv_data_s1),
219
                                  .clk (clk), .se(se), .si(), .so());
220
 
221
   // check parity
222
   sparc_ifu_par32  tag_par0(.in  ({3'b0, ictags_s1[`IC_TAG_SZ:0]}),
223
                                               .out (erd_erc_tagpe_s1[0]));
224
   sparc_ifu_par32  tag_par1(.in  ({3'b0, ictags_s1[((2*`IC_TAG_SZ) + 1):(`IC_TAG_SZ+1)]}),
225
                                               .out (erd_erc_tagpe_s1[1]));
226
   sparc_ifu_par32  tag_par2(.in  ({3'b0, ictags_s1[((3*`IC_TAG_SZ) + 2):(2*(`IC_TAG_SZ)+2)]}),
227
                                               .out (erd_erc_tagpe_s1[2]));
228
   sparc_ifu_par32  tag_par3(.in  ({3'b0, ictags_s1[((4*`IC_TAG_SZ) + 3):(3*(`IC_TAG_SZ)+3)]}),
229
                                               .out (erd_erc_tagpe_s1[3]));
230
 
231
   dp_mux4ds #(32) asitag_mux(.dout (tag_asi_data[31:0]),
232
                         .in0  ({icv_data_s1[0], 1'b0, ictags_s1[28], 1'b0, ictags_s1[27:0]}),
233
                         .in1  ({icv_data_s1[1], 1'b0, ictags_s1[57], 1'b0, ictags_s1[56:29]}),
234
                         .in2  ({icv_data_s1[2], 1'b0, ictags_s1[86], 1'b0, ictags_s1[85:58]}),
235
                         .in3  ({icv_data_s1[3], 1'b0, ictags_s1[115], 1'b0, ictags_s1[114:87]}),
236
                         .sel0_l (erc_erd_asiway_s1_l[0]),
237
                         .sel1_l (erc_erd_asiway_s1_l[1]),
238
                         .sel2_l (erc_erd_asiway_s1_l[2]),
239
                         .sel3_l (erc_erd_asiway_s1_l[3]));
240
 
241
//------------------
242
// Data
243
//------------------
244
   // parity check on instruction
245
   // This may have to be done in the next stage (at least partially)
246
 
247
   sparc_ifu_par34 nir_par(.in  (wsel_fdp_topdata_s1[33:0]),
248
                                             .out (erd_erc_nirpe_s1));
249
   sparc_ifu_par34 inst_par(.in  (wsel_fdp_fetdata_s1[33:0]),
250
                                              .out (erd_erc_fetpe_s1));
251
 
252
//----------------------------------------------------------------------
253
// TLB read data
254
//----------------------------------------------------------------------
255
 
256
//`ifdef SPARC_HPV_EN
257
   // don't include v(26) and u(24) bits in parity   
258
   sparc_ifu_par32 tt_tag_par0(.in  ({itlb_rd_tte_tag[33:27],
259
                                                              itlb_rd_tte_tag[25],
260
                                                              itlb_rd_tte_tag[23:0]}),
261
                                                 .out (erd_erc_tlbt_pe_s1[0]));
262
//`else
263
//   // don't include v(28) and u(26) bits in parity
264
//   sparc_ifu_par32 tt_tag_par0(.in  ({itlb_rd_tte_tag[33:29],
265
//                                                            itlb_rd_tte_tag[27],
266
//                                                            itlb_rd_tte_tag[25:0]}),
267
//                                               .out (erd_erc_tlbt_pe_s1[0]));
268
//`endif // !`ifdef SPARC_HPV_EN
269
 
270
 
271
   sparc_ifu_par32 tt_tag_par1(.in  ({7'b0, itlb_rd_tte_tag[58:34]}),
272
                                                 .out (erd_erc_tlbt_pe_s1[1]));
273
 
274
   sparc_ifu_par32 tt_data_par0(.in  (itlb_rd_tte_data[31:0]),
275
                                                        .out (erd_erc_tlbd_pe_s1[0]));
276
   sparc_ifu_par16 tt_data_par1(.in  ({5'b0, itlb_rd_tte_data[42:32]}),
277
                                                        .out (erd_erc_tlbd_pe_s1[1]));
278
 
279
//   assign erd_erc_tte_lock_s1 = itlb_rd_tte_data[`STLB_DATA_L];
280
 
281
 
282
//`ifdef        SPARC_HPV_EN
283
   assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[`STLB_DATA_27_22_SEL],
284
                                                           itlb_rd_tte_data[`STLB_DATA_21_16_SEL],
285
                                                           itlb_rd_tte_data[`STLB_DATA_15_13_SEL]};
286
 
287
   assign formatted_tte_tag[63:0] =
288
          {
289
//           `ifdef SUN4V_TAG_RD
290
           // implement this!
291
           itlb_rd_tte_tag[58:55],
292
//           `else
293
//         {4{itlb_rd_tte_tag[53]}},                                     // 4b
294
//           `endif
295
 
296
           itlb_rd_tte_tag[`STLB_TAG_PARITY],     // Parity                 1b
297
           itlb_rd_tte_tag[`STLB_TAG_VA_27_22_V], // mxsel2 - b27:22 vld    1b
298
           itlb_rd_tte_tag[`STLB_TAG_VA_21_16_V], // mxsel1 - b21:16 vld    1b
299
           itlb_rd_tte_tag[`STLB_TAG_VA_15_13_V], // mxsel0 - b15:13 vld    1b
300
 
301
           {8{itlb_rd_tte_tag[53]}},                                     // 8b
302
           itlb_rd_tte_tag[`STLB_TAG_VA_47_28_HI:`STLB_TAG_VA_47_28_LO], // 20b
303
           itlb_rd_tte_tag[`STLB_TAG_VA_27_22_HI:`STLB_TAG_VA_27_22_LO], // 6b
304
           itlb_rd_tte_tag[`STLB_TAG_VA_21_16_HI:`STLB_TAG_VA_21_16_LO], // 6b
305
           itlb_rd_tte_tag[`STLB_TAG_VA_15_13_HI:`STLB_TAG_VA_15_13_LO], // 3b
306
           itlb_rd_tte_tag[`STLB_TAG_CTXT_12_0_HI:`STLB_TAG_CTXT_12_0_LO]// 13b
307
           } ;
308
//`else
309
//   assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[`STLB_DATA_21_19_SEL],
310
//                                                         itlb_rd_tte_data[`STLB_DATA_18_16_SEL],
311
//                                                         itlb_rd_tte_data[`STLB_DATA_15_13_SEL]};
312
//
313
//   assign formatted_tte_tag[63:0] =
314
//          {
315
//           {16{itlb_rd_tte_tag[54]}},                                    // 16b
316
//           itlb_rd_tte_tag[`STLB_TAG_VA_47_22_HI:`STLB_TAG_VA_47_22_LO], // 26b
317
//           itlb_rd_tte_tag[`STLB_TAG_VA_21_20_HI:`STLB_TAG_VA_21_20_LO], // 3b
318
//           itlb_rd_tte_tag[`STLB_TAG_VA_19],
319
//           itlb_rd_tte_tag[`STLB_TAG_VA_18_17_HI:`STLB_TAG_VA_18_17_LO], // 3b
320
//           itlb_rd_tte_tag[`STLB_TAG_VA_16],
321
//           itlb_rd_tte_tag[`STLB_TAG_VA_15_14_HI:`STLB_TAG_VA_15_14_LO], // 3b
322
//           itlb_rd_tte_tag[`STLB_TAG_VA_13],
323
//           itlb_rd_tte_tag[`STLB_TAG_CTXT_12_7_HI:`STLB_TAG_CTXT_12_7_LO],//13b
324
//           itlb_rd_tte_tag[`STLB_TAG_CTXT_6_0_HI:`STLB_TAG_CTXT_6_0_LO]
325
//           } ;
326
//`endif // !`ifdef SPARC_HPV_EN
327
 
328
 
329
//`ifdef        SPARC_HPV_EN
330
   assign formatted_tte_data[63:0] =
331
          {
332
           itlb_rd_tte_tag[`STLB_TAG_V],           // V    (1b)
333
           erc_erd_pgsz_b1,                        // pg SZ msb 4m or 512k
334
           erc_erd_pgsz_b0,                        // pg sz lsb 4m or 64k
335
           itlb_rd_tte_data[`STLB_DATA_NFO],       // NFO  (1b)
336
           itlb_rd_tte_data[`STLB_DATA_IE],        // IE   (1b)
337
           10'b0,                                  // soft2 
338
           itlb_rd_tte_data[`STLB_DATA_27_22_SEL], // pgsz b2
339
           itlb_rd_tte_tag[`STLB_TAG_U],
340
 
341
           itlb_rd_tte_data[`STLB_DATA_PARITY],      // Parity   (1b)
342
           itlb_rd_tte_data[`STLB_DATA_27_22_SEL],   // mxsel2_l (1b)
343
           itlb_rd_tte_data[`STLB_DATA_21_16_SEL],   // mxsel1_l (1b)
344
           itlb_rd_tte_data[`STLB_DATA_15_13_SEL],   // mxsel0_l (1b)
345
 
346
           2'b0,                                   // unused diag 2b
347
           1'b0,                                   // ?? PA   (28b)
348
           itlb_rd_tte_data[`STLB_DATA_PA_39_28_HI:`STLB_DATA_PA_39_28_LO],
349
           itlb_rd_tte_data[`STLB_DATA_PA_27_22_HI:`STLB_DATA_PA_27_22_LO],
350
           itlb_rd_tte_data[`STLB_DATA_PA_21_16_HI:`STLB_DATA_PA_21_16_LO],
351
           itlb_rd_tte_data[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO],
352
           6'b0,                                   // ?? 12-7 (6b)
353
           itlb_rd_tte_data[`STLB_DATA_L],         // L    (1b)
354
           itlb_rd_tte_data[`STLB_DATA_CP],        // CP   (1b)
355
           itlb_rd_tte_data[`STLB_DATA_CV],        // CV   (1b)
356
           itlb_rd_tte_data[`STLB_DATA_E],         // E    (1b)
357
           itlb_rd_tte_data[`STLB_DATA_P],         // P    (1b)
358
           itlb_rd_tte_data[`STLB_DATA_W],         // W    (1b)
359
                 1'b0
360
        } ;
361
//`else // !`ifdef SPARC_HPV_EN
362
//
363
//   assign formatted_tte_data[63:0] =
364
//          {      
365
//           itlb_rd_tte_tag[`STLB_TAG_V],           // V    (1b)
366
//           erc_erd_pgsz_b1,                        // pg SZ msb 4m or 512k
367
//           erc_erd_pgsz_b0,                        // pg sz lsb 4m or 64k
368
//           itlb_rd_tte_data[`STLB_DATA_NFO],       // NFO  (1b)
369
//           itlb_rd_tte_data[`STLB_DATA_IE],        // IE   (1b)
370
//           9'b0,                                   // soft2 58-42 (17b)
371
//           8'b0,                                   // diag 8b
372
//               itlb_rd_tte_tag[`STLB_TAG_U],           // U    (1b)
373
//           1'b0,                                   // ?? PA   (28b)
374
//           itlb_rd_tte_data[`STLB_DATA_PA_39_22_HI:`STLB_DATA_PA_39_22_LO],
375
//           itlb_rd_tte_data[`STLB_DATA_PA_21_19_HI:`STLB_DATA_PA_21_19_LO],
376
//           itlb_rd_tte_data[`STLB_DATA_PA_18_16_HI:`STLB_DATA_PA_18_16_LO],
377
//           itlb_rd_tte_data[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO],
378
//           6'b0,                                   // ?? 12-7 (6b)
379
//           itlb_rd_tte_data[`STLB_DATA_L],         // L    (1b)
380
//           itlb_rd_tte_data[`STLB_DATA_CP],        // CP   (1b)
381
//           itlb_rd_tte_data[`STLB_DATA_CV],        // CV   (1b)
382
//           itlb_rd_tte_data[`STLB_DATA_E],         // E    (1b)
383
//           itlb_rd_tte_data[`STLB_DATA_P],         // P    (1b)
384
//           itlb_rd_tte_data[`STLB_DATA_W],         // W    (1b)
385
//           itlb_rd_tte_data[`STLB_DATA_G]          // G    (1b)
386
//        } ;
387
//`endif // !`ifdef SPARC_HPV_EN
388
 
389
 
390
 
391
   // mux in all asi values
392
   dp_mux2es #(64) itlbrd_mux(.dout (tlb_asi_data[63:0]),
393
                            .in0  (formatted_tte_tag[63:0]),
394
                            .in1  (formatted_tte_data[63:0]),
395
                            .sel  (fcl_erb_itlbrd_data_s));
396
 
397
   dp_mux4ds #(64) err_mux(.dout (err_asi_data[63:0]),
398
                         .in0  ({62'b0, erc_erd_erren_asidata}),
399
                         .in1  ({32'b0, erc_erd_errstat_asidata, 9'b0}),
400
                         .in2  ({32'b0, erc_erd_errinj_asidata}),
401
                         .in3  ({16'b0, err_addr_asidata, 4'b0}),
402
                         .sel0_l (erc_erd_errasi_sel_en_l),
403
                         .sel1_l (erc_erd_errasi_sel_stat_l),
404
                         .sel2_l (erc_erd_errasi_sel_inj_l),
405
                         .sel3_l (erc_erd_errasi_sel_addr_l));
406
 
407
   dp_mux3ds #(64) misc_asi_mux(.dout (misc_asi_data[63:0]),
408
                              .in0  ({29'b0,
409
                                            tag_asi_data[31:28],
410
                                            3'b0,
411
                                            tag_asi_data[27:0]}),
412
                              .in1  ({25'b0, erb_dtu_imask}),
413
                              .in2  (64'b0),
414
                              .sel0_l (erc_erd_miscasi_sel_ict_l),
415
                              .sel1_l (erc_erd_miscasi_sel_imask_l),
416
                              .sel2_l (erc_erd_miscasi_sel_other_l));
417
 
418
   // Final asi data
419
   // May need to add a flop to this mux output before sending it to the LSU
420
   dp_mux4ds #(64) final_asi_mux(.dout (ldxa_data_s),
421
                               .in0  (tlb_asi_data[63:0]),
422
                               .in1  (err_asi_data),
423
                               .in2  (misc_asi_data),
424
                               .in3  ({30'b0,
425
                                             wsel_erb_asidata_s[0],
426
                                             wsel_erb_asidata_s[33:1]}),
427
                               .sel0_l (erc_erd_asisrc_sel_itlb_s_l),
428
                               .sel1_l (erc_erd_asisrc_sel_err_s_l),
429
                               .sel2_l (erc_erd_asisrc_sel_misc_s_l),
430
                               .sel3_l (erc_erd_asisrc_sel_icd_s_l));
431
 
432
   dff_s #(64) ldxa_reg(.din (ldxa_data_s),
433
                      .q   (ldxa_data_d),
434
                      .clk (clk), .se(se), .si(), .so());
435
   assign ifu_lsu_ldxa_data_w2 = ldxa_data_d;
436
 
437
 
438
//----------------------------------------
439
// Error Address
440
//----------------------------------------   
441
 
442
   assign ifet_addr_f = {ifq_erb_wrtag_f[`IC_TAG_SZ-1:0],
443
                         ifq_erb_wrindex_f[`IC_IDX_HI:4]};
444
 
445
   // pc of latest access
446
   dff_s #(48) pcs1_reg(.din (fdp_erb_pc_f[47:0]),
447
                                  .q   (pc_s1[47:0]),
448
                                  .clk (clk), .se(se), .si(), .so());
449
 
450
   // Physical address
451
   assign paddr_s1[39:10] = itlb_ifq_paddr_s[39:10];
452
   assign paddr_s1[9:4]   = pc_s1[9:4];
453
   dff_s #(36) padd_reg(.din (paddr_s1[39:4]),
454
                                  .q   (paddr_d1[39:4]),
455
                                  .clk (clk), .se(se), .si(), .so());
456
 
457
//   assign erb_ifq_paddr_s[9:0] = pc_s1[9:0];
458
 
459
   // stage PC one more cycle
460
   dff_s #(44) pcd1_reg(.din (pc_s1[47:4]),
461
                                  .q   (pc_d1[47:4]),
462
                                  .clk (clk), .se(se), .si(), .so());
463
 
464
   // IRF address
465
   dff_s #(16) irf_reg(.din ({exu_ifu_err_reg_m[7:0],
466
                            exu_ifu_err_synd_m[7:0]}),
467
                                 .q   ({irfaddr_w[7:5],
468
                            irfaddr_4_w,
469
                            irfaddr_w[3:0],
470
                            irfsynd_w[7:0]}),
471
                                 .clk (clk), .se(se), .si(), .so());
472
 
473
   // fix for bug 5594
474
   // nand2 + xnor
475
   assign irfaddr_w[4] = irfaddr_4_w ^ (irfaddr_w[5] & irfaddr_w[3]);
476
 
477
   // itlb asi address
478
   dff_s #(6) itlbidx_reg(.din (tlu_itlb_rw_index_g),
479
                        .q   (itlb_asi_index),
480
                        .clk (clk), .se(se), .si(), .so());
481
 
482
 
483
   // lsu error address
484
   dff_s #(44) lsadr_reg(.din (lsu_ifu_err_addr),
485
                       .q   (lsu_err_addr),
486
                       .clk (clk), .se(se), .si(), .so());
487
 
488
 
489
   // mux in the different error addresses
490
   // thread 0
491
   dp_mux4ds #(44) t0_eadr_mx0(.dout  (t0_eadr_mx0_out),
492
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
493
                             .in1   ({38'b0, itlb_asi_index}),
494
                             .in2   ({17'b0, ffu_ifu_err_synd_w2[13:7],
495
                    1'b0, ffu_ifu_err_synd_w2[6:0],
496
                    6'b0, ffu_ifu_err_reg_w2[5:0]}),
497
                             .in3   (lsu_err_addr),
498
                             .sel0_l (erc_erd_eadr0_sel_irf_l[0]),
499
                             .sel1_l (erc_erd_eadr0_sel_itlb_l[0]),
500
                             .sel2_l (erc_erd_eadr0_sel_frf_l[0]),
501
                             .sel3_l (erc_erd_eadr0_sel_lsu_l[0]));
502
 
503
   dp_mux4ds #(44) t0_eadr_mx1(.dout  (t0_eadr_mx1_out),
504
                             .in0   (pc_d1[47:4]),
505
                             .in1   ({8'b0, paddr_d1[39:4]}),
506
                             .in2   ({8'b0, ifet_addr_f}),
507
                             .in3   ({8'b0, spu_ifu_err_addr_w2[39:4]}),
508
                             .sel0_l (erc_erd_eadr1_sel_pcd1_l[0]),
509
                             .sel1_l (erc_erd_eadr1_sel_l1pa_l[0]),
510
                             .sel2_l (erc_erd_eadr1_sel_l2pa_l[0]),
511
                             .sel3_l (erc_erd_eadr1_sel_other_l[0]));
512
 
513
   dp_mux4ds #(44) t0_eadr_mx2(.dout  (t0_err_addr_nxt),
514
                             .in0   (t0_eadr_mx0_out),
515
                             .in1   (t0_eadr_mx1_out),
516
                             .in2   (ifq_erb_asidata_i2[47:4]),
517
                             .in3   (t0_err_addr),
518
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[0]),
519
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[0]),
520
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[0]),
521
                             .sel3_l (erc_erd_eadr2_sel_old_l[0]));
522
 
523
   dff_s #(44) t0_eadr_reg(.din (t0_err_addr_nxt),
524
                       .q   (t0_err_addr),
525
                       .clk (clk), .se(se), .si(), .so());
526
 
527
`ifdef FPGA_SYN_1THREAD
528
        assign err_addr_asidata = t0_err_addr;
529
`else
530
   // thread 1
531
   dp_mux4ds #(44) t1_eadr_mx0(.dout  (t1_eadr_mx0_out),
532
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
533
                             .in1   ({38'b0, itlb_asi_index}),
534
                             .in2   ({17'b0, ffu_ifu_err_synd_w2[13:7],
535
                    1'b0, ffu_ifu_err_synd_w2[6:0],
536
                    6'b0, ffu_ifu_err_reg_w2[5:0]}),
537
                             .in3   (lsu_err_addr),
538
                             .sel0_l (erc_erd_eadr0_sel_irf_l[1]),
539
                             .sel1_l (erc_erd_eadr0_sel_itlb_l[1]),
540
                             .sel2_l (erc_erd_eadr0_sel_frf_l[1]),
541
                             .sel3_l (erc_erd_eadr0_sel_lsu_l[1]));
542
 
543
   dp_mux4ds #(44) t1_eadr_mx1(.dout  (t1_eadr_mx1_out),
544
                             .in0   (pc_d1[47:4]),
545
                             .in1   ({8'b0, paddr_d1[39:4]}),
546
                             .in2   ({8'b0, ifet_addr_f}),
547
                             .in3   ({8'b0, spu_ifu_err_addr_w2[39:4]}),
548
//                           .in3   ({44'b0}),
549
                             .sel0_l (erc_erd_eadr1_sel_pcd1_l[1]),
550
                             .sel1_l (erc_erd_eadr1_sel_l1pa_l[1]),
551
                             .sel2_l (erc_erd_eadr1_sel_l2pa_l[1]),
552
                             .sel3_l (erc_erd_eadr1_sel_other_l[1]));
553
 
554
   dp_mux4ds #(44) t1_eadr_mx2(.dout  (t1_err_addr_nxt),
555
                             .in0   (t1_eadr_mx0_out),
556
                             .in1   (t1_eadr_mx1_out),
557
                             .in2   (ifq_erb_asidata_i2[47:4]),
558
                             .in3   (t1_err_addr),
559
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[1]),
560
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[1]),
561
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[1]),
562
                             .sel3_l (erc_erd_eadr2_sel_old_l[1]));
563
 
564
   dff_s #(44) t1_eadr_reg(.din (t1_err_addr_nxt),
565
                       .q   (t1_err_addr),
566
                       .clk (clk), .se(se), .si(), .so());
567
 
568
   // thread 2
569
   dp_mux4ds #(44) t2_eadr_mx0(.dout  (t2_eadr_mx0_out),
570
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
571
                             .in1   ({38'b0, itlb_asi_index}),
572
                             .in2   ({17'b0, ffu_ifu_err_synd_w2[13:7],
573
                    1'b0, ffu_ifu_err_synd_w2[6:0],
574
                    6'b0, ffu_ifu_err_reg_w2[5:0]}),
575
                             .in3   (lsu_err_addr),
576
                             .sel0_l (erc_erd_eadr0_sel_irf_l[2]),
577
                             .sel1_l (erc_erd_eadr0_sel_itlb_l[2]),
578
                             .sel2_l (erc_erd_eadr0_sel_frf_l[2]),
579
                             .sel3_l (erc_erd_eadr0_sel_lsu_l[2]));
580
 
581
   dp_mux4ds #(44) t2_eadr_mx1(.dout  (t2_eadr_mx1_out),
582
                             .in0   (pc_d1[47:4]),
583
                             .in1   ({8'b0, paddr_d1[39:4]}),
584
                             .in2   ({8'b0, ifet_addr_f}),
585
                             .in3   ({8'b0, spu_ifu_err_addr_w2[39:4]}),
586
//                           .in3   ({44'b0}),
587
                             .sel0_l (erc_erd_eadr1_sel_pcd1_l[2]),
588
                             .sel1_l (erc_erd_eadr1_sel_l1pa_l[2]),
589
                             .sel2_l (erc_erd_eadr1_sel_l2pa_l[2]),
590
                             .sel3_l (erc_erd_eadr1_sel_other_l[2]));
591
 
592
   dp_mux4ds #(44) t2_eadr_mx2(.dout  (t2_err_addr_nxt),
593
                             .in0   (t2_eadr_mx0_out),
594
                             .in1   (t2_eadr_mx1_out),
595
                             .in2   (ifq_erb_asidata_i2[47:4]),
596
                             .in3   (t2_err_addr),
597
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[2]),
598
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[2]),
599
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[2]),
600
                             .sel3_l (erc_erd_eadr2_sel_old_l[2]));
601
 
602
   dff_s #(44) t2_eadr_reg(.din (t2_err_addr_nxt),
603
                       .q   (t2_err_addr),
604
                       .clk (clk), .se(se), .si(), .so());
605
 
606
   // thread 3
607
   dp_mux4ds #(44) t3_eadr_mx0(.dout  (t3_eadr_mx0_out),
608
                             .in0   ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
609
                             .in1   ({38'b0, itlb_asi_index}),
610
                             .in2   ({17'b0, ffu_ifu_err_synd_w2[13:7],
611
                    1'b0, ffu_ifu_err_synd_w2[6:0],
612
                    6'b0, ffu_ifu_err_reg_w2[5:0]}),
613
                             .in3   (lsu_err_addr),
614
                             .sel0_l (erc_erd_eadr0_sel_irf_l[3]),
615
                             .sel1_l (erc_erd_eadr0_sel_itlb_l[3]),
616
                             .sel2_l (erc_erd_eadr0_sel_frf_l[3]),
617
                             .sel3_l (erc_erd_eadr0_sel_lsu_l[3]));
618
 
619
   dp_mux4ds #(44) t3_eadr_mx1(.dout  (t3_eadr_mx1_out),
620
                             .in0   (pc_d1[47:4]),
621
                             .in1   ({8'b0, paddr_d1[39:4]}),
622
                             .in2   ({8'b0, ifet_addr_f}),
623
                             .in3   ({8'b0, spu_ifu_err_addr_w2[39:4]}),
624
//                           .in3   ({44'b0}),
625
                             .sel0_l (erc_erd_eadr1_sel_pcd1_l[3]),
626
                             .sel1_l (erc_erd_eadr1_sel_l1pa_l[3]),
627
                             .sel2_l (erc_erd_eadr1_sel_l2pa_l[3]),
628
                             .sel3_l (erc_erd_eadr1_sel_other_l[3]));
629
 
630
   dp_mux4ds #(44) t3_eadr_mx2(.dout  (t3_err_addr_nxt),
631
                             .in0   (t3_eadr_mx0_out),
632
                             .in1   (t3_eadr_mx1_out),
633
                             .in2   (ifq_erb_asidata_i2[47:4]),
634
                             .in3   (t3_err_addr),
635
                             .sel0_l (erc_erd_eadr2_sel_mx0_l[3]),
636
                             .sel1_l (erc_erd_eadr2_sel_mx1_l[3]),
637
                             .sel2_l (erc_erd_eadr2_sel_wrt_l[3]),
638
                             .sel3_l (erc_erd_eadr2_sel_old_l[3]));
639
 
640
   dff_s #(44) t3_eadr_reg(.din (t3_err_addr_nxt),
641
                       .q   (t3_err_addr),
642
                       .clk (clk), .se(se), .si(), .so());
643
 
644
 
645
   // asi read
646
   dp_mux4ds #(44) asi_eadr_mx(.dout (err_addr_asidata),
647
                             .in0  (t0_err_addr),
648
                             .in1  (t1_err_addr),
649
                             .in2  (t2_err_addr),
650
                             .in3  (t3_err_addr),
651
                             .sel0_l (erc_erd_asi_thr_l[0]),
652
                             .sel1_l (erc_erd_asi_thr_l[1]),
653
                             .sel2_l (erc_erd_asi_thr_l[2]),
654
                             .sel3_l (erc_erd_asi_thr_l[3]));
655
`endif
656
 
657
   // Instruction Mask
658
   dp_mux2es #(39) imask_en_mux(.dout (imask_next),
659
                              .in0  (erb_dtu_imask),
660
                              .in1  (ifq_erb_asidata_i2[38:0]),
661
                              .sel  (erc_erd_ld_imask));
662
 
663
   // need to reset top 7 bits only
664
   dffr_s #(39) imask_reg(.din (imask_next),
665
                      .q   (erb_dtu_imask),
666
                      .rst (erb_reset),
667
                      .clk (clk), .se(se), .si(), .so());
668
 
669
   sink #(4) s0(.in (pc_s1[3:0]));
670
 
671
endmodule // sparc_ifu_erb
672
 

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