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[/] [sparc64soc/] [trunk/] [T1-CPU/] [ifu/] [sparc_ifu_milfsm.v] - Blame information for rev 2

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
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// 
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// OpenSPARC T1 Processor File: sparc_ifu_milfsm.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
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// 
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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//  Module Name: sparc_ifu_ifqdp
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//  Description:
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//  The IFQ is the icache fill queue.  This communicates between the
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//  IFU and the outside world.  It handles icache misses and
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//  invalidate requests from the crossbar.
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*/
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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`include "ifu.h"
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//`define MILFSM_NULL   4'b0000
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//`define MILFSM_WAIT   4'b1000
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//`define MILFSM_REQ    4'b1100
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//`define MILFSM_FILL0  4'b1001
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//`define MILFSM_FILL1  4'b1011
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//`define MIL_V  3
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//`define MIL_R  2
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//`define MIL_A  1
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//`define MIL_F  0
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46
 
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module sparc_ifu_milfsm(/*AUTOARG*/
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   // Outputs
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   so, fsm_ifc_errreq, fsm_ifc_wrt_tir, fsm_ifc_comp_valid,
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   fsm_ifc_mil_valid, fsm_ifc_mil_cancel, fsm_ifc_thr_ready,
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   fsm_ifc_pred_rdy, fsm_ifc_pcxreq, fsm_ifc_addrbit4_i2,
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   fsm_ifc_milchld, fsm_ifc_milstate,
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   // Inputs
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   ifc_fsm_can_thisthr, ifc_fsm_fill_thisthr_i2,
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   ifc_fsm_wr_complete_f, ifqadv_i2, ifd_ifc_4bpkt_i2,
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   fcl_ifq_thr_s1, ifc_fsm_imiss_thisthr_s, ifc_fsm_milhit_s,
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   ifc_fsm_hiton_thismil_s, ifc_fsm_pcxaccept_thisthr,
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   ifc_fsm_miladdr4, clk, se, si, reset, ifc_fsm_err_thisthr
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   );
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   input       ifc_fsm_can_thisthr,
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                     ifc_fsm_fill_thisthr_i2;
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   input       ifc_fsm_wr_complete_f;
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   input       ifqadv_i2;
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   input       ifd_ifc_4bpkt_i2;
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   input [1:0] fcl_ifq_thr_s1;
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   input       ifc_fsm_imiss_thisthr_s;
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   input       ifc_fsm_milhit_s;
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         input       ifc_fsm_hiton_thismil_s,
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               ifc_fsm_pcxaccept_thisthr;
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   input       ifc_fsm_miladdr4;
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76
   input       clk,
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               se,
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               si,
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               reset;
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81
   input       ifc_fsm_err_thisthr;
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83
 
84
   output      so;
85
 
86
   output      fsm_ifc_errreq;
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   output      fsm_ifc_wrt_tir;
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89
   output      fsm_ifc_comp_valid,
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                     fsm_ifc_mil_valid,
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               fsm_ifc_mil_cancel,
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                     fsm_ifc_thr_ready;
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   output      fsm_ifc_pred_rdy,
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                     fsm_ifc_pcxreq,
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                     fsm_ifc_addrbit4_i2;
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   output [2:0] fsm_ifc_milchld;
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   output [3:0] fsm_ifc_milstate;
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101
 
102
//----------------------------------------------------------------------
103
// Declarations
104
//----------------------------------------------------------------------
105
 
106
 
107
   // local variables
108
   reg [3:0]     next_state;
109
 
110
   wire [3:0]    milstate;
111
 
112
   wire [2:0]   local_milchld;
113
 
114
   wire         milchld_valid;
115
 
116
   wire   fill_this16b;
117
 
118
 
119
   wire         cancel_mil,
120
                      cancel_next;
121
   wire         err_pending,
122
                      err_pending_next;
123
 
124
   wire         valid_d1,
125
                valid_i2;
126
 
127
   wire [2:0]    next_milchld;
128
 
129
 
130
   // Missed Instruction List State Machine
131
   // 3   - valid
132
   // 2   - req
133
   // 1   - addr for fill fill (1/0)
134
   // 0   - fill
135
   //
136
   // 2   - child valid
137
   // 1:0 - child thr ptr
138
   //
139
 
140
 
141
   always @(/*AUTOSENSE*/err_pending or ifc_fsm_err_thisthr
142
            or ifc_fsm_fill_thisthr_i2 or ifc_fsm_imiss_thisthr_s
143
            or ifc_fsm_milhit_s or ifc_fsm_pcxaccept_thisthr
144
            or ifc_fsm_wr_complete_f or ifd_ifc_4bpkt_i2 or ifqadv_i2
145
            or milstate)
146
     begin
147
              case (milstate)  //  synopsys parallel_case
148
                4'b0000: // null
149
                  begin
150
                     //ic_wrreq_i2 = 1'b0;             
151
                     //  orphan_chld = 1'b0;
152
               next_state[1:0] = 2'b0;
153
               if (ifc_fsm_err_thisthr | ifc_fsm_imiss_thisthr_s)
154
                             begin
155
                                next_state[`MIL_V] = 1'b1;
156
                                if (ifc_fsm_milhit_s & ~ifc_fsm_err_thisthr)
157
                                  next_state[`MIL_R] = 1'b0;  // MILFSM_WAIT
158
                                else
159
                                  next_state[`MIL_R] = 1'b1;  // MILFSM_REQ;
160
                             end
161
                     else
162
                             next_state = milstate;
163
                  end // case: begin...
164
 
165
                4'b1100:  // req
166
                  begin
167
                     // ic_wrreq_i2 = 1'b0;             
168
                     // if canthr=1, the request will not be sent out in this cycle.
169
               if ((ifc_fsm_pcxaccept_thisthr) &
170
                   ~(ifc_fsm_err_thisthr | err_pending))
171
                 // two requests are made when there is an error.
172
                 // one, with errbit=1 gets back in invalidate response, 
173
                 // the other, with errbit=0, gets the regular ifill 
174
                 // return
175
                             begin
176
                                // we invalidate the icache on detecting an error
177
                                // only if this wasn't an MIL hit as well.  If it
178
                                // was an MIL we would have gone to the wait state
179
                                // already and it is too late to invalidate the cache
180
                                next_state = `MILFSM_WAIT;
181
                    //              orphan_chld = 1'b0;             
182
                             end
183
//                   else if ((cancel_mil | ifc_fsm_can_thisthr) & 
184
//                        ~milchld_valid & ~ifc_fsm_hiton_thismil_s)
185
//                           begin
186
//                              next_state = `MILFSM_NULL;
187
//                           end
188
                     else
189
                             begin
190
                                next_state = milstate;
191
                    //              orphan_chld = 1'b0;
192
                             end
193
                  end // case: 4'b1100
194
 
195
                4'b1000: // wait
196
                  begin
197
               //              orphan_chld = 1'b0;
198
                     if (ifc_fsm_fill_thisthr_i2)
199
                             begin
200
                                // ic_wrreq_i2 = 1'b1;
201
                    if (ifd_ifc_4bpkt_i2 & ifqadv_i2) // 4B ifill from IOB
202
                      // don't want to advance too quickly and get fasle compl
203
                      next_state = `MILFSM_NULL;
204
                    else if (~ifd_ifc_4bpkt_i2)
205
                                  next_state = `MILFSM_FILL0;
206
                    else
207
                      next_state = milstate;
208
                             end
209
                     else
210
                             begin
211
                                next_state = milstate;
212
                                //ic_wrreq_i2 = 1'b0;               
213
                             end
214
                  end // case: 4'b1000
215
 
216
                4'b1001: // fill0
217
                  begin
218
               //              orphan_chld = 1'b0;
219
               if (ifc_fsm_wr_complete_f)
220
                             begin
221
                                next_state = `MILFSM_FILL1;
222
                                //ic_wrreq_i2 = 1'b1;
223
                             end
224
                     else
225
                             begin
226
                                next_state = milstate;
227
                                //ic_wrreq_i2 = 1'b1;
228
                             end
229
                  end // case: 4'b1001
230
 
231
                4'b1011: // fill1
232
                  // Do we really need this state??  yes, to start thr
233
                  begin
234
               //              orphan_chld = 1'b0;                  
235
                     if (ifc_fsm_wr_complete_f)
236
                             begin
237
                                //ic_wrreq_i2 = 1'b0;               
238
                    //              if (delay_mil | ifc_fsm_imiss_thisthr_s)
239
                    //                next_state = `MILFSM_REQ;
240
                    //              else
241
                                next_state = `MILFSM_NULL;
242
                             end
243
                     else
244
                             begin
245
                                //ic_wrreq_i2 = 1'b1;
246
                                next_state = milstate;
247
                             end // else: !if(ifc_fsm_wr_complete_f)
248
                  end // case: 4'b10001
249
 
250
                default:
251
                  begin
252
               // synopsys translate_off
253
                     // 0in <fire -message "MILSTATE, Error: SPARC/IFU/MILFSM: unknown state!"
254
`ifdef DEFINE_0IN
255
`else
256
               if ($time > (4* `CMP_CLK_PERIOD))
257
                 begin
258
                                `ifdef MODELSIM
259
                                          $display ("MILSTATE",
260
                            "Error: SPARC/IFU/MILFSM: unknown state! %b\n",milstate);
261
                                `else
262
                          $error ("MILSTATE",
263
                            "Error: SPARC/IFU/MILFSM: unknown state! %b\n",milstate);
264
                                `endif
265
                 end
266
`endif
267
               // synopsys translate_on               
268
                     next_state = milstate;
269
                     //ic_wrreq_i2 = 1'b0;                  
270
               //              orphan_chld = 1'b0;      
271
                  end // case: default
272
              endcase // casex(milstate)
273
     end // always @ (...
274
 
275
 
276
   // MIL state reg
277
   dffr_s #(4) milst_reg(.din  (next_state[3:0]),
278
                                   .q    (milstate[3:0]),
279
                                   .clk  (clk),
280
                                   .rst  (reset),
281
                                   .se   (se), .si(), .so());
282
 
283
   // Cancel - Delay state machine
284
   // -- not used anymore
285
   // C D
286
   // 0 0  - null
287
   // 1 0  - current thread cancelled but pending from L2
288
   // 1 1  - one ifill pending from L2, current thread will be sent
289
   //        out after that.
290
 
291
//   assign cancel_next = (ifc_fsm_can_thisthr | 
292
//                                         cancel_mil) & next_state[`MIL_V];    // reset wins
293
 
294
   assign cancel_next = (ifc_fsm_can_thisthr | cancel_mil) &
295
                          (milstate[`MIL_V] | ifc_fsm_imiss_thisthr_s |
296
                           ifc_fsm_err_thisthr);    // reset wins
297
 
298
   dffr_s #(1) can_ff(.din  (cancel_next),
299
                                .q    (cancel_mil),
300
                                .clk  (clk),
301
                                .rst  (reset),
302
                                .se   (se), .si(), .so());
303
 
304
   // track if we need to send out an error request
305
   assign err_pending_next = (ifc_fsm_err_thisthr &
306
                              (milstate[`MIL_R] | ~milstate[`MIL_V]) |
307
//                            err_pending & next_state[`MIL_V]) &       
308
                        err_pending & milstate[`MIL_V]) &
309
                              ~ifc_fsm_pcxaccept_thisthr;
310
                         // & ~ifc_fsm_can_thisthr;
311
 
312
   dffr_s #(1) err_ff(.din (err_pending_next),
313
                                .q   (err_pending),
314
                                .clk (clk),
315
                                .rst (reset), .se(se), .si(), .so());
316
   assign fsm_ifc_errreq = err_pending;
317
 
318
   // Track secondary hits
319
   assign next_milchld[2] = ifc_fsm_hiton_thismil_s |    // hit on MIL by
320
                                                             // someone else
321
                                    fsm_ifc_milchld[2] & milstate[`MIL_V]; // reset
322
 
323
   assign next_milchld[1:0] = ifc_fsm_hiton_thismil_s ? fcl_ifq_thr_s1 :
324
                                                                          fsm_ifc_milchld[1:0];
325
 
326
   dffr_s #(3) milchld_reg(.din  (next_milchld),
327
                                     .clk  (clk),
328
                                     .rst  (reset),
329
                                     .q    (local_milchld),
330
                                     .se   (se), .si(), .so());
331
 
332
   assign fsm_ifc_milchld[2] = local_milchld[2] & milstate[`MIL_V];
333
   assign fsm_ifc_milchld[1:0] = local_milchld[1:0];
334
 
335
   assign milchld_valid = local_milchld[2] & milstate[`MIL_V];
336
 
337
//   assign fsm_ifc_addrbit4_i2 = milstate[`MIL_F];
338
   assign fsm_ifc_addrbit4_i2 = milstate[`MIL_F] & milstate[`MIL_V] &
339
                                (milstate[`MIL_A] | ifc_fsm_wr_complete_f);
340
 
341
   // determine if we want to fill from the first pkt or second pkt
342
   assign fill_this16b = ~(milstate[`MIL_F] ^ ifc_fsm_miladdr4) |
343
                            ifd_ifc_4bpkt_i2;
344
 
345
   // write to thread inst reg (TIR)
346
//   assign fsm_ifc_wrt_tir =  (next_state[`MIL_F]) & ~cancel_mil & 
347
//                           ifc_fsm_fill_thisthr_i2;
348
   assign fsm_ifc_wrt_tir =  (milstate[`MIL_V] & ~milstate[`MIL_R]) &
349
                                                 ~(cancel_mil | ifc_fsm_can_thisthr) &
350
                               ifc_fsm_fill_thisthr_i2 &
351
                               fill_this16b;
352
 
353
   // write to Icache 
354
//   assign fsm_ifc_wrreq_i2 = ic_wrreq_i2;
355
   assign valid_i2 = milstate[`MIL_V] & ~fsm_ifc_thr_ready;
356
 
357
   dff_s vld_ff(.din (valid_i2),
358
                    .q   (valid_d1),
359
                    .clk (clk),
360
                    .se  (se), .si(), .so());
361
 
362
   // signal thread completion
363
   assign fsm_ifc_thr_ready = milstate[`MIL_V] & milstate[`MIL_F] &
364
                              milstate[`MIL_A] & ifc_fsm_wr_complete_f |
365
                              ~milstate[`MIL_V] & valid_d1;
366
 
367
   // predict ready assuming 2nd ifill happens in the next cycle
368
   assign fsm_ifc_pred_rdy =  milstate[`MIL_V] & milstate[`MIL_F] &
369
                              (ifc_fsm_wr_complete_f |
370
                               milstate[`MIL_A]); //  & ifc_fsm_fill_thisthr_i2
371
 
372
   // set compare valid for mil hit signal
373
   assign fsm_ifc_comp_valid = milstate[`MIL_V] &     // valid entry
374
                                     ~milstate[`MIL_F] &    // not f0 or f1
375
                               ~milchld_valid;        // no chld already
376
 
377
   assign fsm_ifc_mil_valid = milstate[`MIL_V];
378
   assign fsm_ifc_mil_cancel = cancel_mil;
379
 
380
   // In the request state or if we need to send an error invalidate, 
381
   // ask for bus from LSU. 
382
//   assign fsm_ifc_pcxreq = (milstate[`MIL_V] & milstate[`MIL_R] |
383
//                          err_pending | ifc_fsm_err_thisthr) & 
384
//                         ~ifc_fsm_pcxaccept_thisthr & 
385
//                            (milchld_valid | ~cancel_mil);
386
 
387
//   assign fsm_ifc_pcxreq = (milstate[`MIL_V] & milstate[`MIL_R] & 
388
//                                ~ifc_fsm_pcxaccept_thisthr & 
389
//                            (milchld_valid | ~cancel_mil));
390
 
391
   // removed pcx_accept from critical path
392
   assign fsm_ifc_pcxreq = milstate[`MIL_V] & milstate[`MIL_R];
393
 
394
   assign fsm_ifc_milstate = milstate;
395
 
396
 
397
endmodule

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