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// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_ifu_rndrob.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: sparc_ifu_rndrob
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// Description:
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// Round robin scheduler. Least priority to the last granted
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// customer. If no requests, the priority remains the same.
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//
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*/
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////////////////////////////////////////////////////////////////////////
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module sparc_ifu_rndrob(/*AUTOARG*/
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// Outputs
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grant_vec, so,
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// Inputs
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clk, reset, se, si, req_vec, advance, rst_tri_enable
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);
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input clk, reset, se, si;
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input [3:0] req_vec;
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input advance;
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input rst_tri_enable;
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output [3:0] grant_vec;
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output so;
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wire [3:0] next_pv,
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pv,
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gv,
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park_vec;
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assign pv = advance ? grant_vec :
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park_vec;
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assign next_pv[3:1] = pv[3:1] & {3{~reset}};
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assign next_pv[0] = pv[0] | reset;
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dff_s #4 park_reg(.din (next_pv),
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.clk (clk),
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.q (park_vec),
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.se (se), .si(), .so());
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// if noone requests, don't advance, otherwise we'll go back to 0
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// and will not be fair to other requestors
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assign gv[0] = park_vec[3] & req_vec[0] |
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park_vec[2] & ~req_vec[3] & req_vec[0] |
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park_vec[1] & ~req_vec[2] & ~req_vec[3] & req_vec[0] |
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~req_vec[1] & ~req_vec[2] & ~req_vec[3];
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assign gv[1] = park_vec[0] & req_vec[1] |
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park_vec[3] & ~req_vec[0] & req_vec[1] |
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park_vec[2] & ~req_vec[3] & ~req_vec[0] & req_vec[1] |
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req_vec[1] & ~req_vec[2] & ~req_vec[3] & ~req_vec[0];
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assign gv[2] = park_vec[1] & req_vec[2] |
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park_vec[0] & ~req_vec[1] & req_vec[2] |
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park_vec[3] & ~req_vec[0] & ~req_vec[1] & req_vec[2] |
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req_vec[2] & ~req_vec[3] & ~req_vec[0] & ~req_vec[1];
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assign gv[3] = park_vec[2] & req_vec[3] |
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park_vec[1] & ~req_vec[2] & req_vec[3] |
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park_vec[0] & ~req_vec[1] & ~req_vec[2] & req_vec[3] |
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req_vec[3] & ~req_vec[0] & ~req_vec[1] & ~req_vec[2];
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assign grant_vec[0] = gv[0] | rst_tri_enable;
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assign grant_vec[3:1] = gv[3:1] & {3{~rst_tri_enable}};
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endmodule // sparc_ifu_rndrob
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