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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: sparc_ifu_swl.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

////////////////////////////////////////////////////////////////////////

/*

//  Module Name: sparc_ifu_swl

//  Description:

//  The switch logic manages the 4 threads.  It schedules the next

//  thread to be executed.

*/

////////////////////////////////////////////////////////////////////////

`include "ifu.h"

module sparc_ifu_swl(/*AUTOARG*/

   // Outputs

   swl_sscan_thrstate, so, dtu_reset, swl_dec_mulbusy_e,

   swl_dec_divbusy_e, swl_dec_fpbusy_e, swl_dec_fp_enable_d,

   swl_dec_ibe_e, dtu_fcl_ntr_s, dtu_fcl_running_s,

   dtu_fcl_rollback_g, dtu_fcl_retract_d, dtu_fcl_thr_active,

   dtu_fcl_nextthr_bf, swl_dcl_thr_d, swl_dcl_thr_w2,

   dtu_fdp_thrconf_e,

   // Inputs

   rclk, se, si, gdbginit_l, arst_l, grst_l, ctu_sscan_tid,

   ifq_dtu_thrrdy, ifq_dtu_pred_rdy, ifu_tlu_inst_vld_w,

   ifu_tlu_ttype_vld_m, fcl_dtu_hprivmode_d, fcl_dtu_hprivmode_w2,

   tlu_ifu_flush_pipe_w, fcl_swl_flush_w, fcl_dtu_sync_intr_d,

   fcl_dtu_nuke_thr_w, fcl_dtu_rst_thr_w, fcl_dtu_resum_thr_w,

   fcl_dtu_thr_f, tlu_hpstate_ibe, lsu_ifu_ldsta_internal_e,

   tlu_ifu_trappc_vld_w1, dec_swl_ll_done_d, dec_swl_br_done_d,

   dec_swl_rdsr_sel_thr_d, dec_swl_std_inst_d, dec_swl_sta_inst_e,

   wsr_fixed_inst_w, dec_swl_ld_inst_d, dec_swl_mul_inst_d,

   dec_swl_div_inst_d, dec_swl_fpop_d, dec_swl_allfp_d,

   dec_swl_frf_upper_d, dec_swl_frf_lower_d, dec_swl_wrtfprs_w,

   dcl_swl_tcc_done_m, exu_ifu_longop_done_g, exu_ifu_spill_e,

   lsu_ifu_ldst_cmplt, lsu_ifu_dc_parity_error_w2, lsu_ifu_stbcnt0,

   lsu_ifu_stbcnt1, lsu_ifu_stbcnt2, lsu_ifu_stbcnt3,

   lsu_ifu_quad_asi_e, ffu_ifu_fpop_done_w2, ffu_ifu_tid_w2,

   ffu_ifu_fst_ce_w, tlu_ifu_trap_tid_w1, tlu_ifu_pstate_pef,

   lsu_ifu_ldst_miss_g, fcl_swl_int_activate_i3,

   fcl_swl_flush_wake_w, ifq_swl_stallreq, fcl_dtu_stall_bf,

   fcl_swl_swout_f, fcl_swl_swcvld_s, fdp_fcl_swc_s2,

   fcl_ifq_icmiss_s1, fcl_dtu_inst_vld_e, fcl_dtu_intr_vld_e,

   fcl_dtu_inst_vld_d, erb_dtu_ifeterr_d1, dtu_inst_anull_e,

   const_cpuid, thr_config_in_m, dec_swl_wrt_tcr_w,

   dec_swl_st_inst_d, extra_longlat_compl

   );

   input       rclk,

               se,

               si,

               gdbginit_l,

               arst_l,

               grst_l;

   input [3:0] ctu_sscan_tid;   // guaranteed one-hot by ctu

   input [3:0] ifq_dtu_thrrdy;         // ifq completion signals

   input [3:0] ifq_dtu_pred_rdy;     // ifq almost done

   input       ifu_tlu_inst_vld_w,    //

                     ifu_tlu_ttype_vld_m;

   input       fcl_dtu_hprivmode_d;

   input       fcl_dtu_hprivmode_w2;

   input       tlu_ifu_flush_pipe_w;  // flush after a trap

   input       fcl_swl_flush_w;

   input       fcl_dtu_sync_intr_d;   // interrupt

   input       fcl_dtu_nuke_thr_w;    // sync suspend

   input       fcl_dtu_rst_thr_w;    // 

   input       fcl_dtu_resum_thr_w;    // 

   input [3:0] fcl_dtu_thr_f;

   input [3:0] tlu_hpstate_ibe;

   input       lsu_ifu_ldsta_internal_e,// sta to local reg

                     tlu_ifu_trappc_vld_w1, // trap completion

                     dec_swl_ll_done_d,   // rdsr completion

               dec_swl_br_done_d,

                     dec_swl_rdsr_sel_thr_d,

                     dec_swl_std_inst_d,    //

                     dec_swl_sta_inst_e,    // state change

                     wsr_fixed_inst_w,      // wrspr completion

                     dec_swl_ld_inst_d;     // load hit/compl. speculation

   input       dec_swl_mul_inst_d,

                     dec_swl_div_inst_d;

   input       dec_swl_fpop_d,

                     dec_swl_allfp_d;

   input       dec_swl_frf_upper_d,

                     dec_swl_frf_lower_d,

                     dec_swl_wrtfprs_w;

   input       dcl_swl_tcc_done_m;

   input [3:0] exu_ifu_longop_done_g; // save, restore, div, mul compl.

   input       exu_ifu_spill_e;

   input [3:0] lsu_ifu_ldst_cmplt;

   input       lsu_ifu_dc_parity_error_w2;

   input [3:0] lsu_ifu_stbcnt0,

                     lsu_ifu_stbcnt1,

                     lsu_ifu_stbcnt2,

                     lsu_ifu_stbcnt3;

//   input [3:0] lsu_ifu_stq_busy;

   input       lsu_ifu_quad_asi_e;

   input       ffu_ifu_fpop_done_w2;

   input [1:0] ffu_ifu_tid_w2;

   input       ffu_ifu_fst_ce_w;

   input [1:0] tlu_ifu_trap_tid_w1;

   input [3:0] tlu_ifu_pstate_pef;

   input       lsu_ifu_ldst_miss_g;   // dcache hit or miss

   input [3:0] fcl_swl_int_activate_i3; // wake up thread on interrupt

   input       fcl_swl_flush_wake_w;

   // TBD: with the latest changes fcl_dtu_switch_s = dtu_fcl_ntr_s, so 

   // this input can be removed.

//   input       fcl_dtu_switch_s; // switch out curr, sw in next

   input       ifq_swl_stallreq;

   input       fcl_dtu_stall_bf,

               fcl_swl_swout_f,       // curr thread is stalled

                     fcl_swl_swcvld_s,

               fdp_fcl_swc_s2,        // thread stall condition

                     fcl_ifq_icmiss_s1;     // icache miss

   input       fcl_dtu_inst_vld_e,

               fcl_dtu_intr_vld_e,

                     fcl_dtu_inst_vld_d;

   input       erb_dtu_ifeterr_d1;

   input       dtu_inst_anull_e;      // anull delay slot

   input [3:0] const_cpuid;           // use 4 bits to allow future

                                      // expansion to 16 cores

   input [2:0] thr_config_in_m;       // write data to thread status reg

   input       dec_swl_wrt_tcr_w;     // write signal for thr status reg

   input       dec_swl_st_inst_d;

   input [3:0] extra_longlat_compl;   // spare signal, not used

   output [10:0] swl_sscan_thrstate;

   output        so;

   output      dtu_reset;

   output      swl_dec_mulbusy_e,

                     swl_dec_divbusy_e,

                     swl_dec_fpbusy_e,

                     swl_dec_fp_enable_d;

   output      swl_dec_ibe_e;

   // to fcl

   output      dtu_fcl_ntr_s,         // next thread ready

               dtu_fcl_running_s,

                     dtu_fcl_rollback_g,    // rollback on spec

                     dtu_fcl_retract_d;     // rollback on hw hazard

   output [3:0] dtu_fcl_thr_active;   // currently active threads

   output [3:0] dtu_fcl_nextthr_bf,   // thread to switch to when ntr=1

                            swl_dcl_thr_d,

                            swl_dcl_thr_w2;

   // to fdp

   output [40:0] dtu_fdp_thrconf_e;   // thread conf for RDSR inst

//----------------------------------------------------------

// Declarations

//----------------------------------------------------------

   // local signals

//   wire [3:0]    count_nxt,

//                     count;

//   wire          proc0;

//   wire          start_on_rst;

   wire          ibe_d,

                 ibe_e;

   wire [3:0]    completion,

                             wm_imiss,

                             wm_other,

                             spec_ld_d,

                             issue_spec_ld,

                             ldmiss,

                             ldhit_thr,

                             spec_ld_g,

                             imiss,

                             trap,

                 ldmiss_non_crit,

                 ldmiss_crit,

                             trp_no_retr,

//                           rb_thr_w,

                 rt_st_thr_d,

                 rt_st_thr_e,

                             schedule,

                             int_activate,

                             start_thread,

                 thaw_thread,

                             resum_thread,

                             nuke_thread,

                             rst_thread;

   wire          rollback_g,

                 rb_en_g,

                 rollback_g_l,

                 rollback_w2;

   wire          sched_nt;

   wire [3:0]    fixedop_done,

                             wsr_done_w3;

   wire          wsr_inst_w2,

                 wsr_inst_w3;

   wire          wsr_fixed_qual_w,

                 wsr_fixed_w2;

   wire          llinst_done_e;

   wire [3:0]    ll_done_e,

                 branch_done_d,

                 std_tcc_done_m;

   wire          sta_done_e,

                             killed_inst_done_e;

   wire [3:0]    killed_uniop_done_e;

   wire          uniop_d,

                             uniop_e;

//   wire          no_iftrap_m,

//                 no_iftrap_w;

   wire [3:0]    thr_s1,

                 thr_s2,

                             thr_f,

                             thr_d,

                             thr_e,

                             thr_m,

                             thr_w,

                 st_thr_w2,

                             st_thr_w3;

   wire          flush_pipe_w_nxt,

                 flush_all_w,

                 flush_pipe_w2,

                 flush_done_w,

                 fp_flush_done_w2,

                 fp_flush_done_w3,

                             flush_done_w2;

   wire          rbfor_fst_ce_w;

   wire [3:0]    flush_wake_w2,

                 fp_flush_wake_w3,

                 halt_thread;

   wire          wrt_spec_w,

                 wrt_spec_w2,

                 halt_w,

                 halt_w2,

                             en_spec_d,

                             en_spec_m,

                             en_spec_g,

                             spec_next;

   wire          ld_inst_e,

                             ld_inst_next_e,

                 ld_inst_qual_d,

                             ld_inst_m,

                             ld_inst_unq_w,

                             ld_inst_w,

                 ld_inst_w2;

   wire          switch_out,

                       sw_cond_s,

                       swc_d,

                       swc_next_d,

                       swc_e;

   wire          trp_noretr_d;

   wire [3:0]    all_stall;

   wire [3:0]    rdy,

                       sprdy_or_urdy;

   wire          running_s2,

                 atr_s;

   wire [4:0]    thr0_state,

                             thr1_state,

                             thr2_state,

                             thr3_state;

   wire          use_spec;

   wire [3:0]    wrt_tcr_w2;

   wire [1:0]    enc_thr_d;

   wire          rd_thract_d,

                             rd_thract_e;

   wire [51:0]   fmt_thrconf_e,

                 thrconf_out_e,

                 fmt_thrconf_adj;

   wire          hprivmode_e,

                 rdsr_sel_thr_e;

   wire [2:0]    rd_tid_spec_e;

   wire [3:0]    mul_busy_d,

                             mul_busy_e,

                             div_busy_d,

                             div_busy_e,

                             fp_busy_d,

                             fp_busy_e;

   wire          true_fpbusy_e,

                 fpbusy_local_e,

                 true_mulbusy_e,

                 true_divbusy_e;

   wire          fbusy_nxt_d,

                 fbusy_crit_e,

                 fbusy_d3,

                 fbusy_d0,

                 fbusy_d1,

                 fbusy_d2,

                 dbusy_d3,

                 dbusy_d0,

                 dbusy_d1,

                 dbusy_d2,

                 mbusy_d3,

                 mbusy_d0,

                 mbusy_d1,

                 mbusy_d2;

   wire [3:0]    mul_wait,

                             mul_wait_nxt,

                             div_wait,

                             div_wait_nxt,

                             fp_wait,

                             fp_wait_nxt;

   wire          mul_wait_any,

                             div_wait_any,

                             fp_wait_any;

   wire [3:0]    mul_wake,

                             div_wake,

                             fp_wake;

   wire [3:0]    exu_lop_done,

                             mul_done,

                             div_done,

                             fp_done;

   wire [3:0]    retr_thr_wakeup;

   wire [3:0]    trap_thrrdy,

                             trap_thr;

   wire [3:0]    fp_thr,

                             fp_thrrdy;

   wire          same_thr_de,

                             same_thr_dg,

                 same_thr_fd,

                 same_thr_fe,

                             same_thr_fm,

                             same_thr_fg;

   wire          st_thisthr_e;

   wire          st_inst_e,

                             st_inst_qual_d,

                             st_inst_qual_e,

                             st_inst_m,

                             st_inst_g;

   wire          pipe_st_cnt_ge1,

                             pipe_st_cnt_ge2,

                             pipe_st_cnt_ge3;

   wire          pipe_st_d,

                 pipe_st_e,

                             pipe_st_m,

                             pipe_st_g;

   wire          all_dst_ge1,

                             all_dst_ge2,

                             all_dst_ge3,

                             all_dst_eq4;

   wire          dst_cnt_ge1,

                             dst_cnt_ge2,

                             dst_cnt_ge3;

   wire [3:0]    stbcnt_s,

                             stbcnt_d;

   wire [3:0]    stb_stall,

                             stb_blocked,

                             stb_blocked_d1,

                             st_in_pipe,

                             stb_retry,

                             wm_stbwait,

                             stb_wait_nxt;

   wire          switch_store_d,

//                           retract_stall_d,

                             retract_store_e,

                 retract_st_next_d,

                             retract_store_d;

   wire          retract_iferr_d,

                 iferr_s,

                 iferr_d;

   wire          clear_wmo_e;

   wire          sw_st_e,

                             sw_st_m,

                             sw_st_g,

                             sw_st_w2;

   wire          std_inst_e;

//                           stq_inst_e,

//                           stq_inst_m,

//                           stq_inst_w,

//                           stq_inst_w2;

   wire          std_done_e;

   wire          std_done_m;

//   wire [3:0]    stq_busy,

//                           stq_in_pipe,

//                           stq_wait,

//                           stq_wait_next,

//                           stq_done_thr;

   wire [2:0]    fprs0,

                             fprs1,

                             fprs2,

                             fprs3,

                             fprs_d,

                             fprs_e,

                             fprs_wrt_data,

                 thr_config_in_w,

                 thr_config_in_w2,

                             fprs0_nxt,

                             fprs1_nxt,

                             fprs2_nxt,

                             fprs3_nxt;

   wire [1:0]    new_fprs;

   wire [3:0]    fprs_en_s,

                             fpen_vec_s;

   wire          wrt_fprs_w,

                 wrt_fprs_w2;

   wire [3:0]    sel_wrt,

                             fprs_sel_set,

                             fprs_sel_wrt,

                             fprs_sel_old;

   wire          fpen_s;

   wire [1:0]    trap_tid_w2;

   wire          trappc_vld_w2;

   wire          dtu_reset_l;

   wire          sched_reset;

   wire          clk;

   //

   // Code Begins Here

   //

   assign        clk = rclk;

   // reset buffer

   dffrl_async rstff(.din (grst_l),

                        .q   (dtu_reset_l),

                        .clk (clk), .se(se), .si(), .so(),

                        .rst_l (arst_l));

   assign       dtu_reset = ~dtu_reset_l;

   //---------------------------------------------

   // Start off thread on reset using this counter

   //---------------------------------------------

//   dffr #(4) thrrdy_ctr(.din (count_nxt),

//                                  .clk (clk),

//                                  .q   (count),

//                                  .rst (dtu_reset),

//                                  .se (se), .si(), .so());

//

//   // count_nxt = count + 1, sticky at 8 = 1111

//   assign count_nxt[0] = ~count[0] | count[3];

//   assign count_nxt[1] = (count[1] ^ count[0]) | count[3];

//   assign count_nxt[2] = (count[2] ^ (count[1] & count[0])) | count[3]; 

//   assign count_nxt[3] = (count[3] ^ (count[2] & count[1] & count[0])) |

//                             count[3]; 

//

//   assign proc0 = (const_cpuid == 4'b0000) ? 1'b1 : 1'b0;

//   assign start_on_rst = (~count[3] & count[2] & count[1] & count[0])

//                          & proc0;

//`ifdef IFU_SAT   

//   // temporary hack to start threads

//   reg [3:0]  auto_start;

//   always @ (posedge clk)

//     auto_start = 4'b0000;

//`endif

   //-----------------

   // completion logic

   //-----------------

   sparc_ifu_thrcmpl compl(

                           .reset       (dtu_reset),

                                             /*AUTOINST*/

                           // Outputs

                           .completion  (completion[3:0]),

                           .wm_imiss    (wm_imiss[3:0]),

                           .wm_other    (wm_other[3:0]),

                           // Inputs

                           .clk         (clk),

                           .se          (se),

                           .si          (si),

                           .fcl_ifq_icmiss_s1(fcl_ifq_icmiss_s1),

                           .erb_dtu_ifeterr_d1(erb_dtu_ifeterr_d1),

                           .sw_cond_s   (sw_cond_s),

                           .en_spec_g   (en_spec_g),

                           .atr_s       (atr_s),

                           .dtu_fcl_thr_active(dtu_fcl_thr_active[3:0]),

                           .ifq_dtu_thrrdy(ifq_dtu_thrrdy[3:0]),

                           .ifq_dtu_pred_rdy(ifq_dtu_pred_rdy[3:0]),

                           .exu_lop_done(exu_lop_done[3:0]),

                           .branch_done_d(branch_done_d[3:0]),

                           .fixedop_done(fixedop_done[3:0]),

                           .ldmiss      (ldmiss[3:0]),

                           .spec_ld_d   (spec_ld_d[3:0]),

                           .trap        (trap[3:0]),

                           .retr_thr_wakeup(retr_thr_wakeup[3:0]),

                           .flush_wake_w2(flush_wake_w2[3:0]),

                           .ldhit_thr   (ldhit_thr[3:0]),

                           .spec_ld_g   (spec_ld_g[3:0]),

                           .clear_wmo_e (clear_wmo_e),

                           .wm_stbwait  (wm_stbwait[3:0]),

                           .stb_retry   (stb_retry[3:0]),

                           .rst_thread  (rst_thread[3:0]),

                           .trap_thrrdy (trap_thrrdy[3:0]),

                           .thr_s2      (thr_s2[3:0]),

                           .thr_e       (thr_e[3:0]),

                           .thr_s1      (thr_s1[3:0]),

                           .fp_thrrdy   (fp_thrrdy[3:0]),

                           .lsu_ifu_ldst_cmplt(lsu_ifu_ldst_cmplt[3:0]),

                           .sta_done_e  (sta_done_e),

                           .killed_inst_done_e(killed_inst_done_e));

   //------------

   // Thread Pipe

   //------------

   assign thr_f = fcl_dtu_thr_f;

//   assign thr_dec_f[0] = thr_f[0] | rst_tri_en;

//   assign thr_dec_f[3:1] = thr_f[3:1] & {3{~rst_tri_en}};

//   assign thr_dec_d[0] = thr_d[0] | rst_tri_en;

//   assign thr_dec_d[3:1] = thr_d[3:1] & {3{~rst_tri_en}};

   dff_s #(4) thrd_reg(.din  (thr_f[3:0]),

                   .clk  (clk),

                   .q    (thr_d[3:0]),

                   .se   (se), .si(), .so());

   assign     swl_dcl_thr_d = thr_d;

   dff_s #(4) thre_reg(.din  (thr_d),

                   .clk  (clk),

                   .q    (thr_e),

                   .se   (se), .si(), .so());

   dff_s #(4) thrm_reg(.din  (thr_e),

                   .clk  (clk),

                   .q    (thr_m),

                   .se   (se), .si(), .so());

   dff_s #(4) thrw_reg(.din  (thr_m),

                   .clk  (clk),

                   .q    (thr_w),

                   .se   (se), .si(), .so());

   dff_s #(4) thrw2_reg(.din  (thr_w),

                    .clk  (clk),

                    .q    (st_thr_w2),

                    .se   (se), .si(), .so());

   dff_s #(4) thrw3_reg(.din  (st_thr_w2),

                    .clk  (clk),

                    .q    (st_thr_w3),

                    .se   (se), .si(), .so());

   assign     swl_dcl_thr_w2 = st_thr_w2;

   // send ibe of curr thread to dec

   assign ibe_d = (thr_d[0] & tlu_hpstate_ibe[0] |

                   thr_d[1] & tlu_hpstate_ibe[1] |

                   thr_d[2] & tlu_hpstate_ibe[2] |

                   thr_d[3] & tlu_hpstate_ibe[3]);

   dff_s #(1) ibee_ff(.din (ibe_d),

                    .q   (ibe_e),

                    .clk (clk), .se(se), .si(), .so());

   assign swl_dec_ibe_e = ibe_e;

//----------------------------------------------------------------------

// Track Thread Execution

//----------------------------------------------------------------------

   // track instructions

   dff_s #(1) lle_ff(.din (dec_swl_ll_done_d),

                   .q   (llinst_done_e),

                   .clk (clk), .se (se), .si(), .so());

   assign ll_done_e = thr_e & {4{llinst_done_e & fcl_dtu_inst_vld_e &

                                 ~exu_ifu_spill_e}};

   assign std_tcc_done_m = thr_m & {4{dcl_swl_tcc_done_m | std_done_m}};

   assign wsr_fixed_qual_w  = wsr_fixed_inst_w & ifu_tlu_inst_vld_w &

                              ~fcl_swl_flush_w;

   dff_s #(1) wsrw2_ff(.din (wsr_fixed_qual_w),

                     .q   (wsr_fixed_w2),

                     .clk (clk), .se(se), .si(), .so());

   assign wsr_inst_w2  = wsr_fixed_w2 & ~flush_pipe_w2;

   // delay one cycle to allow tlu to finish

   dff_s #(1) wsw3_ff(.din (wsr_inst_w2),

                    .q   (wsr_inst_w3),

                    .clk (clk), .se(se), .si(), .so());

   assign wsr_done_w3 = {4{wsr_inst_w3}} & st_thr_w3;

   assign fixedop_done = (ll_done_e | wsr_done_w3 | std_tcc_done_m |

                                wrt_tcr_w2 | extra_longlat_compl);

   assign branch_done_d = thr_d & {4{dec_swl_br_done_d & fcl_dtu_inst_vld_d}};

   assign sta_done_e = dec_swl_sta_inst_e & fcl_dtu_inst_vld_e &

                       ~lsu_ifu_ldsta_internal_e;

   assign ld_inst_qual_d = dec_swl_ld_inst_d & fcl_dtu_inst_vld_d &

                           ~iferr_d;

   dff_s #(1) lde_ff(.din  (ld_inst_qual_d),

                               .clk  (clk),

                               .q    (ld_inst_e),

                               .se   (se), .si(), .so());

   assign ld_inst_next_e = ld_inst_e;

//                         & ~dtu_inst_anull_e &    

//                           ~(lsu_ifu_ldsta_internal_e & 

//                             ifu_lsu_alt_space_e &

//                             fcl_dtu_inst_vld_e);

//   assign ld_inst_internal_e = ~dtu_inst_anull_e & ld_inst_e &

//                               (fcl_dtu_inst_vld_e & 

//                                lsu_ifu_ldsta_internal_e & 

//                                ifu_lsu_alt_space_e);

   dff_s #(1) ldm_ff(.din  (ld_inst_next_e),

                               .clk  (clk),

                               .q    (ld_inst_m),

                               .se   (se), .si(), .so());

   dff_s #(1) ldw_ff(.din  (ld_inst_m),