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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_ifu_swpla.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: sparc_ifu_lfsr5
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// Description:
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// The IFQ is the icache input queue. This communicates between the
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// IFU and the outside world. It handles icache misses and
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// invalidate requests from the crossbar.
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*/
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////////////////////////////////////////////////////////////////////////
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module sparc_ifu_swpla(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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input [31:0] in;
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output out;
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wire [31:0] in;
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reg out;
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always @ (in)
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begin
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if (in[31:30] == 2'b01) // call
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out = 1'b1;
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else if (in[31:30] == 2'b00) // branch, sethi, nop
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begin
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if (in[24:22] == 3'b100) // nop/sethi
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out = 1'b0;
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else // branch
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out = 1'b1;
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end // if (in[31:30] == 2'b00)
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else if (in[31:30] == 2'b10) // arith, shift, mem#, mov
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begin
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if (in[24:23] == 2'b11) // wrpr, vis, save, jmpl
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out = 1'b1;
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else if (in[24] == 1'b0) // arith
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begin
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if (in[22] == 1'b0) // alu op
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out = 1'b0;
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else if ((in[22] == 1'b1) && (in[20:19] == 2'b00))
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// subc or addc
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out = 1'b0;
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else // mul, div
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out = 1'b1;
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end // if (in[24] == 1'b0)
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else // if (in[24:23] == 2'b10) shft, mov, rdpr, tag
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begin
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if (in[22:19] == 4'h4) // mulscc
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out = 1'b1;
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else if (in[22] == 1'b0) // shft, tag
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out = 1'b0;
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else if ((in[22:19] == 4'hc) || (in[22:19] == 4'hf)) // mov
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out = 1'b0;
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// else if (in[22:19] == 4'ha) // rdpr
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// out = 1'b0;
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else // rdsr, mem#, popc, flushw, rdpr
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out = 1'b1;
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end // if ((in[24] == 1'b1) && (in[23] == 1'b0))
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end // if (in[31:30] == 2'b10)
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else // ld st
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begin
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// if (in[24] & in[22] & in[21] & ~in[20] & in[19]) // prefetch
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// out = 1'b0;
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if (in[24] | in[23] | ~in[21]) // fp, alt space or ld
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out = 1'b1;
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// else if (in[24]) // FP and CAS
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// out = 1'b1;
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// else if (in[23] & in[20] & in[19]) // stda
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// out = 1'b1;
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else if ((~in[23]) && (in[22:19] == 4'he)) // stx
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out = 1'b0;
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else if (in[22:21] == 2'b01) // other st
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out = 1'b0;
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else // other atomic
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out = 1'b1;
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end // else: !if(in[31:30] == 2'b10)
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end // always @ (in)
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sink #(32) s0(.in (in));
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endmodule // sparc_ifu_swpla
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