1 |
2 |
dmitryr |
// ========== Copyright Header Begin ==========================================
|
2 |
|
|
//
|
3 |
|
|
// OpenSPARC T1 Processor File: sparc_ifu_thrcmpl.v
|
4 |
|
|
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
5 |
|
|
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
6 |
|
|
//
|
7 |
|
|
// The above named program is free software; you can redistribute it and/or
|
8 |
|
|
// modify it under the terms of the GNU General Public
|
9 |
|
|
// License version 2 as published by the Free Software Foundation.
|
10 |
|
|
//
|
11 |
|
|
// The above named program is distributed in the hope that it will be
|
12 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
|
|
// General Public License for more details.
|
15 |
|
|
//
|
16 |
|
|
// You should have received a copy of the GNU General Public
|
17 |
|
|
// License along with this work; if not, write to the Free Software
|
18 |
|
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
19 |
|
|
//
|
20 |
|
|
// ========== Copyright Header End ============================================
|
21 |
|
|
////////////////////////////////////////////////////////////////////////
|
22 |
|
|
/*
|
23 |
|
|
// Module Name: sparc_ifu_thrcmpl
|
24 |
|
|
// Description:
|
25 |
|
|
// The thread completion block processes the completion signals fomr
|
26 |
|
|
// the different cpu blocks and generates a unified completion
|
27 |
|
|
// signal.
|
28 |
|
|
*/
|
29 |
|
|
|
30 |
|
|
module sparc_ifu_thrcmpl(/*AUTOARG*/
|
31 |
|
|
// Outputs
|
32 |
|
|
completion, wm_imiss, wm_other,
|
33 |
|
|
// Inputs
|
34 |
|
|
clk, se, si, reset, fcl_ifq_icmiss_s1, erb_dtu_ifeterr_d1,
|
35 |
|
|
sw_cond_s, en_spec_g, atr_s, dtu_fcl_thr_active, ifq_dtu_thrrdy,
|
36 |
|
|
ifq_dtu_pred_rdy, exu_lop_done, branch_done_d, fixedop_done,
|
37 |
|
|
ldmiss, spec_ld_d, trap, retr_thr_wakeup, flush_wake_w2,
|
38 |
|
|
ldhit_thr, spec_ld_g, clear_wmo_e, wm_stbwait, stb_retry,
|
39 |
|
|
rst_thread, trap_thrrdy, thr_s2, thr_e, thr_s1, fp_thrrdy,
|
40 |
|
|
lsu_ifu_ldst_cmplt, sta_done_e, killed_inst_done_e
|
41 |
|
|
);
|
42 |
|
|
|
43 |
|
|
input clk, se, si, reset;
|
44 |
|
|
|
45 |
|
|
input fcl_ifq_icmiss_s1;
|
46 |
|
|
input erb_dtu_ifeterr_d1;
|
47 |
|
|
|
48 |
|
|
input sw_cond_s;
|
49 |
|
|
input en_spec_g;
|
50 |
|
|
input atr_s;
|
51 |
|
|
|
52 |
|
|
input [3:0] dtu_fcl_thr_active;
|
53 |
|
|
input [3:0] ifq_dtu_thrrdy, // I$ miss completion
|
54 |
|
|
ifq_dtu_pred_rdy,
|
55 |
|
|
exu_lop_done, // mul, div, wrpr, sav, rest
|
56 |
|
|
branch_done_d,
|
57 |
|
|
fixedop_done; // br, rdsr, wrs/pr,
|
58 |
|
|
input [3:0] ldmiss,
|
59 |
|
|
spec_ld_d,
|
60 |
|
|
trap,
|
61 |
|
|
retr_thr_wakeup,
|
62 |
|
|
flush_wake_w2,
|
63 |
|
|
ldhit_thr,
|
64 |
|
|
spec_ld_g;
|
65 |
|
|
|
66 |
|
|
input clear_wmo_e;
|
67 |
|
|
input [3:0] wm_stbwait,
|
68 |
|
|
stb_retry;
|
69 |
|
|
|
70 |
|
|
input [3:0] rst_thread,
|
71 |
|
|
trap_thrrdy;
|
72 |
|
|
|
73 |
|
|
input [3:0] thr_s2,
|
74 |
|
|
thr_e,
|
75 |
|
|
thr_s1;
|
76 |
|
|
|
77 |
|
|
input [3:0] fp_thrrdy;
|
78 |
|
|
|
79 |
|
|
input [3:0] lsu_ifu_ldst_cmplt; // sta local, ld and atomic done
|
80 |
|
|
|
81 |
|
|
input sta_done_e,
|
82 |
|
|
killed_inst_done_e; // long lat op was killed
|
83 |
|
|
|
84 |
|
|
// .. Other completion signals needed
|
85 |
|
|
// 1. STA completion from LSU -- real mem done 10/03, local TBD
|
86 |
|
|
// 2. Atomic completion -- done
|
87 |
|
|
// 3. membar completion (lsu) -- done
|
88 |
|
|
// 4. flush completion (lsu)
|
89 |
|
|
// 5. FP op completion (ffu)
|
90 |
|
|
//
|
91 |
|
|
|
92 |
|
|
output [3:0] completion;
|
93 |
|
|
output [3:0] wm_imiss;
|
94 |
|
|
output [3:0] wm_other;
|
95 |
|
|
|
96 |
|
|
// local signals
|
97 |
|
|
wire [3:0] wm_imiss,
|
98 |
|
|
wm_other,
|
99 |
|
|
wmi_nxt,
|
100 |
|
|
wmo_nxt;
|
101 |
|
|
|
102 |
|
|
wire [3:0] clr_wmo_thr_e;
|
103 |
|
|
|
104 |
|
|
wire [3:0] ldst_thrrdy,
|
105 |
|
|
ld_thrrdy,
|
106 |
|
|
sta_thrrdy,
|
107 |
|
|
killed_thrrdy,
|
108 |
|
|
fp_thrrdy,
|
109 |
|
|
pred_ifq_rdy,
|
110 |
|
|
imiss_thrrdy,
|
111 |
|
|
other_thrrdy;
|
112 |
|
|
// wire [3:0] can_imiss;
|
113 |
|
|
|
114 |
|
|
//----------------------------------------------------------------------
|
115 |
|
|
// Code begins here
|
116 |
|
|
//----------------------------------------------------------------------
|
117 |
|
|
|
118 |
|
|
// Thread completion
|
119 |
|
|
// Since an imiss can overlap with anything else, have to make sure
|
120 |
|
|
// the imiss condition has been cleared.
|
121 |
|
|
// Imiss itself has to make sure ALL OTHER conditions have been
|
122 |
|
|
// cleared. In this code, I am not checking for branches being
|
123 |
|
|
// cleared, since Imiss is assumed to take much longer than a branch.
|
124 |
|
|
// -- may not be a valid assumption, since milhits could be faster
|
125 |
|
|
|
126 |
|
|
// assign can_imiss = fcl_ifq_canthr;
|
127 |
|
|
// & (wm_imiss | ({4{fcl_ifq_icmiss_s1}} & thr_s1));
|
128 |
|
|
|
129 |
|
|
dffr_s #(4) wmi_ff(.din (wmi_nxt),
|
130 |
|
|
.clk (clk),
|
131 |
|
|
.q (wm_imiss),
|
132 |
|
|
.rst (reset),
|
133 |
|
|
.se (se), .si(), .so());
|
134 |
|
|
|
135 |
|
|
dffr_s #(4) wmo_ff(.din (wmo_nxt),
|
136 |
|
|
.clk (clk),
|
137 |
|
|
.q (wm_other),
|
138 |
|
|
.rst (reset),
|
139 |
|
|
.se (se), .si(), .so());
|
140 |
|
|
|
141 |
|
|
assign wmi_nxt = ({4{fcl_ifq_icmiss_s1}} & thr_s1) | // set
|
142 |
|
|
({4{erb_dtu_ifeterr_d1}} & thr_e) |
|
143 |
|
|
(wm_imiss & ~imiss_thrrdy); // reset
|
144 |
|
|
|
145 |
|
|
// clear wm_other when we have a retracted store
|
146 |
|
|
assign clr_wmo_thr_e = {4{clear_wmo_e}} & thr_e;
|
147 |
|
|
|
148 |
|
|
assign wmo_nxt = (({4{sw_cond_s}} & thr_s2 & ~clr_wmo_thr_e) |
|
149 |
|
|
trap | ldmiss) & dtu_fcl_thr_active |
|
150 |
|
|
rst_thread | // set
|
151 |
|
|
wm_other & dtu_fcl_thr_active &
|
152 |
|
|
~(other_thrrdy | spec_ld_d | clr_wmo_thr_e); // reset
|
153 |
|
|
|
154 |
|
|
// A load hit signal is always for the load which is being filled
|
155 |
|
|
// to the RF. If speculation is enabled, the load would have
|
156 |
|
|
// completed even before the hit signal. So need to suppress the
|
157 |
|
|
// completions signal.
|
158 |
|
|
|
159 |
|
|
// load miss, st buf hit, ld/st alternate completion
|
160 |
|
|
assign ldst_thrrdy = lsu_ifu_ldst_cmplt & ~spec_ld_g;
|
161 |
|
|
assign ld_thrrdy = ldhit_thr & {4{~en_spec_g}};
|
162 |
|
|
assign sta_thrrdy = thr_e & {4{sta_done_e}};
|
163 |
|
|
assign killed_thrrdy = thr_e & {4{killed_inst_done_e}};
|
164 |
|
|
|
165 |
|
|
// everthing else
|
166 |
|
|
assign other_thrrdy = (ldst_thrrdy | // ld, sta local, atomic
|
167 |
|
|
branch_done_d | // br
|
168 |
|
|
ld_thrrdy | // load hit without spec
|
169 |
|
|
exu_lop_done | // mul, div, win mgmt
|
170 |
|
|
fixedop_done | // rdsr, wrspr
|
171 |
|
|
killed_thrrdy | // ll op was anulled
|
172 |
|
|
retr_thr_wakeup | // retract cond compl
|
173 |
|
|
flush_wake_w2 | // wake up after ecc
|
174 |
|
|
fp_thrrdy | // fp completion
|
175 |
|
|
sta_thrrdy | // sta to real memory
|
176 |
|
|
trap_thrrdy); // trap
|
177 |
|
|
|
178 |
|
|
// Imiss predicted ready
|
179 |
|
|
assign pred_ifq_rdy = ifq_dtu_pred_rdy & {4{~atr_s}} & dtu_fcl_thr_active;
|
180 |
|
|
assign imiss_thrrdy = pred_ifq_rdy | ifq_dtu_thrrdy;
|
181 |
|
|
|
182 |
|
|
// assign completion = imiss_thrrdy & (~(wm_other | wm_stbwait) |
|
183 |
|
|
// other_thrrdy) | //see C1
|
184 |
|
|
// other_thrrdy & (~(wm_imiss | wmi_nxt));
|
185 |
|
|
|
186 |
|
|
// assign completion = (imiss_thrrdy & ~(wm_other | wm_stbwait) |
|
187 |
|
|
// other_thrrdy & ~(wm_stbwait | wm_imiss) |
|
188 |
|
|
// stb_retry & ~(wm_other | wm_imiss) |
|
189 |
|
|
// imiss_thrrdy & other_thrrdy & ~wm_stbwait |
|
190 |
|
|
// imiss_thrrdy & stb_retry & ~wm_other |
|
191 |
|
|
// stb_retry & other_thrrdy & ~wm_imiss);
|
192 |
|
|
|
193 |
|
|
assign completion = ((imiss_thrrdy | ~wm_imiss) &
|
194 |
|
|
(other_thrrdy | ~wm_other) &
|
195 |
|
|
(stb_retry | ~wm_stbwait) &
|
196 |
|
|
(wm_imiss | wm_other | wm_stbwait));
|
197 |
|
|
|
198 |
|
|
// C1: should we do ~(wm_other | wmo_nxt)??
|
199 |
|
|
// When an imiss is pending, we cannot be doing another fetch, so I
|
200 |
|
|
// don't think so. It seems nice and symmetric to put it in
|
201 |
|
|
// though, unfortunately this results in a timing problem on swc_s
|
202 |
|
|
// and trap
|
203 |
|
|
|
204 |
|
|
endmodule // sparc_ifu_thrcmpl
|