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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_ifu_thrfsm.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: sparc_ifu_swlthrfsm
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// Description:
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// The switch logithrfsm contains the thread state machine.
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*/
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`include "ifu.h"
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module sparc_ifu_thrfsm(/*AUTOARG*/
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// Outputs
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so, thr_state,
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// Inputs
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completion, schedule, spec_ld, ldhit, stall, int_activate,
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start_thread, thaw_thread, nuke_thread, rst_thread, switch_out,
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halt_thread, sw_cond, clk, se, si, reset
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);
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// thread specific input
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input completion, // the op this thread was waiting for is complete
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schedule, // this thread was just switched in
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spec_ld, // speculative switch in
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ldhit, // speculation was correct
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stall, // stall thread for ldmiss, imiss or trap
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int_activate, // activate this thread
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halt_thread,
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start_thread, // wake up this thread from dead state
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nuke_thread,
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thaw_thread,
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rst_thread; // reset this thread
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// common inputs
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input switch_out, // this thread was just switched out
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sw_cond; // wait until completion signal is received
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input clk, se, si, reset;
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output so;
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output [4:0] thr_state;
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// local signals
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reg [4:0] next_state;
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//
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// Code Begins Here
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//
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// assign spec_rdy = thr_state[`TCR_READY];
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always @ (/*AUTOSENSE*/ completion
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or halt_thread or int_activate or ldhit or nuke_thread
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or rst_thread or schedule or spec_ld or stall
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or start_thread or sw_cond or switch_out or thaw_thread
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or thr_state)
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begin
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case (thr_state[4:0])
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`THRFSM_IDLE: // 5'b00000
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begin
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if (rst_thread | thaw_thread)
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next_state = `THRFSM_WAIT;
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else if (start_thread)
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next_state = `THRFSM_RDY;
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else // all other interrupts ignored
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next_state = thr_state[4:0];
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end
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`THRFSM_HALT: // 5'b00010
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begin
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if (nuke_thread)
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next_state = `THRFSM_IDLE;
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else if (rst_thread | thaw_thread)
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next_state = `THRFSM_WAIT;
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else if (int_activate | start_thread)
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next_state = `THRFSM_RDY;
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else
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next_state = thr_state[4:0];
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end
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`THRFSM_RDY: // 5'b11001
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begin
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if (stall)
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// trap also kills inst_s2 and nir
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// Ldmiss should not happen in this state
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next_state = `THRFSM_WAIT;
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else if (schedule)
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next_state = `THRFSM_RUN;
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else
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next_state = thr_state[4:0];
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end // case: `THRFSM_RDY
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`THRFSM_RUN: // 5'b00101
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begin
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if (stall | sw_cond)
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// trap also kills inst_s2 and nir
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// ldmiss should not happen in this state
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next_state = `THRFSM_WAIT;
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else if (switch_out)
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// on an interrupt or thread stall, the fcl has to
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// switch out the thread and inform the fsm
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next_state = `THRFSM_RDY;
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else
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next_state = thr_state[4:0];
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end // case: `THRFSM_RUN
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`THRFSM_WAIT: // 5'b00001
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begin
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if (nuke_thread)
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next_state = `THRFSM_IDLE;
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else if (halt_thread) // exclusive with above
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next_state = `THRFSM_HALT;
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else if (stall) // excl. with above
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next_state = `THRFSM_WAIT;
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else if (spec_ld) // exclusive with above
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next_state = `THRFSM_SPEC_RDY;
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else if (completion & ~halt_thread)
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next_state = `THRFSM_RDY;
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else
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next_state = thr_state[4:0];
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end // case: `THRFSM_WAIT
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`THRFSM_SPEC_RDY: // 5'b10011
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begin
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if (stall)
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next_state = `THRFSM_WAIT;
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else if (schedule & ~ldhit) // exclusive
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next_state = `THRFSM_SPEC_RUN;
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else if (schedule & ldhit) // exclusive
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next_state = `THRFSM_RUN;
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else if (ldhit)
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next_state = `THRFSM_RDY;
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else
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next_state = thr_state[4:0];
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end // case: `THRFSM_SPEC_RDY
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`THRFSM_SPEC_RUN: // 5'b00111
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begin
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if (stall | sw_cond)
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next_state = `THRFSM_WAIT;
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else if ((ldhit) & switch_out)
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next_state = `THRFSM_RDY;
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else if ((ldhit) & ~switch_out)
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next_state = `THRFSM_RUN;
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else if (~(ldhit) & switch_out)
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next_state = `THRFSM_SPEC_RDY;
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// on an interrupt or thread stall, the fcl has to
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// switch out the thread and inform the fsm
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else
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next_state = thr_state[4:0];
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end // case: `THRFSM_SPEC_RUN
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//VCS coverage off
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default:
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begin
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// synopsys translate_off
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// 0in <fire -message "thrfsm.v: Error! Invalid State"
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`ifdef DEFINE_0IN
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`else
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`ifdef MODELSIM
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$display("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
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`else
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$error("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
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`endif
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`endif
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// synopsys translate_on
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if (rst_thread)
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next_state = `THRFSM_WAIT;
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else if (nuke_thread)
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next_state = `THRFSM_IDLE;
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else
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next_state = thr_state[4:0];
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end
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//VCS coverage on
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endcase // casex({thr_state[4:0]})
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end // always @ (...
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// thread config register (tcr)
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dffr_s #(5) tcr(.din (next_state),
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.clk (clk),
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.q (thr_state),
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.rst (reset),
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.se (se), .so(), .si());
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endmodule
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