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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: lsu_dctl.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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/////////////////////////////////////////////////////////////////
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/*
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// Description: LSU Data Cache Control and Minor Datapath
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// - Tag Comparison - hit/miss.
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*/
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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`include "sys.h" // system level definition file which contains the
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// time scale definition
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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`include "lsu.h"
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module lsu_dctl ( /*AUTOARG*/
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// Outputs
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lsu_tlu_nucleus_ctxt_m, lsu_quad_word_access_g, so, dctl_rst_l,
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lsu_tlu_wsr_inst_e, lsu_l2fill_fpld_e, dva_vld_m_bf,
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lsu_no_spc_pref, ifu_tlu_flush_fd_w, ifu_tlu_flush_fd2_w,
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ifu_tlu_flush_fd3_w, ifu_lsu_flush_w, lsu_tlu_thrid_d,
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lsu_diagnstc_data_sel, lsu_diagnstc_va_sel, lsu_err_addr_sel,
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dva_bit_wr_en_e, dva_wr_adr_e, lsu_exu_ldst_miss_w2,
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lsu_exu_dfill_vld_w2, lsu_ffu_ld_vld, lsu_ld_miss_wb,
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lsu_dtlb_bypass_e, ld_pcx_pkt_g, tlb_ldst_cam_vld, ldxa_internal,
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lsu_ifu_ldsta_internal_e, lsu_ifu_ldst_cmplt, lsu_ifu_itlb_en,
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lsu_ifu_icache_en, lmq_byp_data_en_w2, lmq_byp_data_fmx_sel,
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lmq_byp_data_mxsel0, lmq_byp_data_mxsel1, lmq_byp_data_mxsel2,
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lmq_byp_data_mxsel3, lmq_byp_ldxa_mxsel0, lmq_byp_ldxa_mxsel1,
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lmq_byp_ldxa_mxsel2, lmq_byp_ldxa_mxsel3, lsu_ld_thrd_byp_sel_e,
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dcache_byte_wr_en_e, lsu_dcache_wr_vld_e, lsu_ldstub_g,
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lsu_swap_g, lsu_tlu_dtlb_done, lsu_exu_thr_m, merge7_sel_byte0_m,
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merge7_sel_byte7_m, merge6_sel_byte1_m, merge6_sel_byte6_m,
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merge5_sel_byte2_m, merge5_sel_byte5_m, merge4_sel_byte3_m,
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merge4_sel_byte4_m, merge3_sel_byte0_m, merge3_sel_byte3_m,
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merge3_sel_byte4_m, merge3_sel_byte7_default_m, merge3_sel_byte_m,
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merge2_sel_byte1_m, merge2_sel_byte2_m, merge2_sel_byte5_m,
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merge2_sel_byte6_default_m, merge2_sel_byte_m, merge0_sel_byte0_m,
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merge0_sel_byte1_m, merge0_sel_byte2_m,
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merge0_sel_byte3_default_m, merge0_sel_byte4_m,
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merge0_sel_byte5_m, merge0_sel_byte6_m,
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merge0_sel_byte7_default_m, merge1_sel_byte0_m,
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merge1_sel_byte1_m, merge1_sel_byte2_m,
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merge1_sel_byte3_default_m, merge1_sel_byte4_m,
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merge1_sel_byte5_m, merge1_sel_byte6_m,
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merge1_sel_byte7_default_m, merge0_sel_byte_1h_m,
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merge1_sel_byte_1h_m, merge1_sel_byte_2h_m, lsu_dtlb_cam_real_e,
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lsu_dtagv_wr_vld_e, lsu_dtag_wrreq_x_e, lsu_dtag_index_sel_x_e,
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lsu_dtlb_wr_vld_e, lsu_dtlb_tag_rd_e, lsu_dtlb_data_rd_e,
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lsu_dtlb_dmp_vld_e, lsu_dtlb_dmp_all_e, lsu_dtlb_rwindex_vld_e,
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lsu_dtlb_invalid_all_l_m, lsu_tlu_tlb_ld_inst_m,
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lsu_tlu_tlb_st_inst_m, lsu_tlu_tlb_access_tid_m,
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lsu_tlb_data_rd_vld_g, lsu_tlb_st_sel_m, lsu_va_wtchpt0_wr_en_l,
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lsu_va_wtchpt1_wr_en_l, lsu_va_wtchpt2_wr_en_l,
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lsu_va_wtchpt3_wr_en_l, thread0_m, thread1_m, thread2_m,
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thread3_m, lsu_dctldp_thread0_m, lsu_dctldp_thread1_m,
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lsu_dctldp_thread2_m, lsu_dctldp_thread3_m, thread0_g, thread1_g,
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thread2_g, thread3_g, lsu_tlu_nonalt_ldst_m,
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lsu_tlu_xslating_ldst_m, lsu_tlu_ctxt_sel_m, lsu_tlu_write_op_m,
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lsu_dtlb_addr_mask_l_e, dva_din_e,
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lsu_diagnstc_dtagv_prty_invrt_e, lsu_ifu_asi_load,
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lsu_ifu_asi_thrid, lsu_ifu_asi_vld, lsu_quad_asi_e,
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lsu_local_ldxa_sel_g, lsu_dtag_rsel_m, lsu_tlbop_force_swo,
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lsu_atomic_pkt2_bsel_g, lsu_dcache_tag_perror_g,
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lsu_dcache_data_perror_g, lsu_ifu_l2_unc_error,
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lsu_ifu_l2_corr_error, lsu_ifu_dcache_data_perror,
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lsu_ifu_dcache_tag_perror, lsu_ifu_error_tid, lsu_ifu_io_error,
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lsu_tlu_squash_va_oor_m, lsu_squash_va_oor_m, tlb_cam_hit_g,
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lsu_st_hw_le_g, lsu_st_w_or_dbl_le_g, lsu_st_x_le_g,
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lsu_swap_sel_default_g, lsu_swap_sel_default_byte_7_2_g,
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lsu_st_rmo_m, lsu_bst_in_pipe_m, lsu_snap_blk_st_m, lsu_blk_st_m,
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lsu_blkst_pgnum_m, lsu_ffu_blk_asi_e, lsu_blk_asi_m,
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lsu_nonalt_nucl_access_m, dcache_alt_mx_sel_e,
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dcache_alt_mx_sel_e_bf, dcache_rvld_e, lsu_dc_iob_access_e,
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lsu_ifu_ldst_miss_w, lsu_ifu_dc_parity_error_w2,
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lsu_ldst_inst_vld_e, lsu_local_ldxa_tlbrd_sel_g,
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lsu_local_diagnstc_tagrd_sel_g, lsu_va_wtchpt_sel_g,
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asi_state_wr_thrd, thread0_d, thread1_d, thread2_d, thread3_d,
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tlu_lsu_asi_update_g, pctxt_state_wr_thrd, sctxt_state_wr_thrd,
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thread_pctxt, thread_sctxt, thread_actxt, thread_default,
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thread0_ctxt, thread1_ctxt, thread2_ctxt, thread3_ctxt,
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pid_state_wr_en, thread0_e, thread1_e, thread2_e, thread3_e,
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dfture_tap_wr_mx_sel, lctl_rst, lsu_ctl_state_wr_en,
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lsuctl_ctlbits_wr_en, dfture_tap_rd_en, bist_tap_wr_en,
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bistctl_wr_en, bist_ctl_reg_wr_en, mrgn_tap_wr_en, ldiagctl_wr_en,
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misc_ctl_sel_din, lsu_asi_sel_fmx1, lsu_asi_sel_fmx2,
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tlb_access_en0_g, tlb_access_en1_g, tlb_access_en2_g,
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tlb_access_en3_g, tlb_access_sel_thrd0, tlb_access_sel_thrd1,
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tlb_access_sel_thrd2, tlb_access_sel_default, mrgnctl_wr_en,
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hpv_priv_m, hpstate_en_m, dcache_arry_data_sel_m, dtlb_bypass_m,
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lsu_alt_space_m, atomic_m, ldst_dbl_m, fp_ldst_m, lda_internal_m,
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sta_internal_m, cam_real_m, data_rd_vld_g, tag_rd_vld_g,
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ldst_sz_m, asi_internal_m, rd_only_ltlb_asi_e, wr_only_ltlb_asi_e,
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dfill_tlb_asi_e, ifill_tlb_asi_e, nofault_asi_m, as_if_user_asi_m,
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atomic_asi_m, phy_use_ec_asi_m, phy_byp_ec_asi_m, quad_asi_m,
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binit_quad_asi_m, blk_asi_m, recognized_asi_m, strm_asi_m,
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mmu_rd_only_asi_m, rd_only_asi_m, wr_only_asi_m, unimp_asi_m,
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va_wtchpt_cmp_en_m, lsu_tlu_async_ttype_vld_w2,
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lsu_tlu_async_ttype_w2, lsu_tlu_async_tid_w2, async_tlb_index,
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l2fill_vld_m, ld_thrd_byp_mxsel_m, morphed_addr_m,
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signed_ldst_byte_m, signed_ldst_hw_m, signed_ldst_w_m,
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lsu_tlb_asi_data_perr_g, lsu_tlb_asi_tag_perr_g, lsu_sscan_data,
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lsu_ld_inst_vld_g, lsu_dcache_rand, lsu_encd_way_hit,
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lsu_way_hit_or, lsu_memref_m, lsu_flsh_inst_m,
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lsu_ifu_asi_data_en_l, lsu_dcache_fill_addr_e,
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lsu_dcache_fill_addr_e_err, lsu_thread_g, lmq_ldd_vld,
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lsu_bist_rsel_way_e, lsu_dcache_fill_way_e, lmq_ld_addr_b3,
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lsu_outstanding_rmo_st_max, lsu_dcfill_data_mx_sel_e,
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// Inputs
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si, se, sehold, rst_tri_en, rclk, grst_l, arst_l,
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lsu_diag_va_prty_invrt, dva_svld_e, dva_snp_bit_wr_en_e,
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dva_snp_addr_e, lsu_tte_data_cp_g, lsu_l2fill_vld, ld_inst_vld_e,
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st_inst_vld_e, ifu_lsu_ldst_fp_e, ldst_sz_e,
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lsu_ldst_va_b12_b11_m, lsu_ldst_va_b7_b0_m, ifu_lsu_rd_e,
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tlb_cam_hit, ifu_tlu_sraddr_d, ifu_tlu_wsr_inst_d,
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ifu_lsu_alt_space_d, tlu_lsu_int_ldxa_vld_w2,
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tlu_lsu_int_ld_ill_va_w2, tlu_lsu_ldxa_tid_w2,
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ifu_lsu_ldxa_data_vld_w2, ifu_lsu_ldxa_illgl_va_w2,
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ifu_lsu_ldxa_tid_w2, ifu_lsu_asi_rd_unc, tlu_lsu_tl_zero,
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ifu_lsu_thrid_s, ifu_lsu_ldst_dbl_e, ld_stb_full_raw_w2,
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ld_sec_active, ifu_tlu_inst_vld_m, lsu_l2fill_bendian_m,
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lmq0_l2fill_fpld, lmq1_l2fill_fpld, lmq2_l2fill_fpld,
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lmq3_l2fill_fpld, cache_way_hit_buf1, cache_hit, lmq0_byp_misc_sz,
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lmq1_byp_misc_sz, lmq2_byp_misc_sz, lmq3_byp_misc_sz,
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lsu_l2fill_sign_extend_m, lsu_l1hit_sign_extend_e,
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tlu_lsu_pstate_cle, tlu_lsu_pstate_am, tlb_pgnum, tlb_demap_nctxt,
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tlb_demap_pctxt, tlb_demap_sctxt, tlb_demap_actxt,
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tlb_demap_thrid, ifu_lsu_casa_e, ifu_lsu_ldstub_e, ifu_lsu_swap_e,
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lsu_atm_st_cmplt_e, lsu_cpx_pkt_atm_st_cmplt,
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spu_lsu_ldxa_data_vld_w2, spu_lsu_ldxa_illgl_va_w2,
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spu_lsu_ldxa_tid_w2, spu_lsu_stxa_ack_tid, spu_lsu_stxa_ack,
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spu_lsu_unc_error_w2, spu_lsu_int_w2, tlu_lsu_stxa_ack,
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tlu_lsu_stxa_ack_tid, lsu_tlb_invert_endian_g, lmq0_ncache_ld,
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lmq1_ncache_ld, lmq2_ncache_ld, lmq3_ncache_ld, ifu_tlu_mb_inst_e,
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ifu_tlu_flsh_inst_e, lsu_stb_empty, tlu_dtlb_tag_rd_g,
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tlu_dtlb_data_rd_g, tlu_dtlb_dmp_vld_g, tlu_dtlb_dmp_all_g,
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tlu_dtlb_rw_index_vld_g, tlu_dtlb_invalidate_all_g,
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lsu_st_wr_dcache, tlu_lsu_asi_update_m, tlu_lsu_tid_m,
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lsu_rd_dtag_parity_g, dcache_rparity_err_wb,
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lsu_diagnstc_wr_data_b0, lsu_byp_ldd_oddrd_m, tlu_lsu_redmode,
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tlu_lsu_redmode_rst_d1, dva_vld_m, lsu_dfill_tid_e,
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ifu_lsu_asi_ack, lsu_intrpt_cmplt, lsu_iobrdge_tap_rq_type_b8,
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lsu_iobrdge_tap_rq_type_b6_b3, lsu_iobrdge_tap_rq_type_b1_b0,
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lsu_iobrdge_fwd_pkt_vld, lsu_cpx_ld_dtag_perror_e,
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lsu_cpx_ld_dcache_perror_e, lsu_cpx_pkt_ld_err, ifu_lsu_nceen,
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tlu_lsu_ldxa_async_data_vld, tlu_lsu_hpv_priv, tlu_lsu_hpstate_en,
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ifu_lsu_memref_d, ifu_lsu_pref_inst_e, lsu_pref_pcx_req,
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lsu_cpx_pkt_prefetch2, lsu_ld_pcx_rq_sel_d2,
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lsu_pcx_req_squash_d1, lsu_bld_helper_cmplt_m, lsu_bld_cnt_m,
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lsu_bld_reset, ffu_lsu_blk_st_e, lsu_stb_rmo_st_issue,
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lsu_cpx_rmo_st_ack, lsu_dfq_flsh_cmplt, stb_cam_hit,
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ifu_tlu_flush_m, ctu_sscan_tid, tte_data_perror_unc,
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asi_tte_data_perror, asi_tte_tag_perror, tlu_dtlb_rw_index_g,
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lsu_local_early_flush_g, lsu_dfq_vld, gdbginit_l, dc_direct_map,
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asi_d, lsu_dctl_asi_state_m, lsu_ldst_va_g, lsu_ifu_err_addr_b39,
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lsu_dp_ctl_reg0, lsu_dp_ctl_reg1, lsu_dp_ctl_reg2,
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lsu_dp_ctl_reg3, ldd_in_dfq_out, dcache_iob_addr_e,
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mbist_dcache_index, mbist_dcache_word, lsu_diagnstc_wr_addr_e,
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st_dcfill_addr, lsu_dfq_ld_vld, lsu_dfq_st_vld, lmq0_ldd_vld,
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lmq1_ldd_vld, lmq2_ldd_vld, lmq3_ldd_vld, lsu_dfq_byp_tid,
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dfq_byp_ff_en, lsu_dcache_iob_way_e, mbist_dcache_way,
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lsu_diagnstc_wr_way_e, lsu_st_way_e, lmq0_pcx_pkt_way,
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lmq1_pcx_pkt_way, lmq2_pcx_pkt_way, lmq3_pcx_pkt_way,
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lmq0_ld_rq_type, lmq1_ld_rq_type, lmq2_ld_rq_type,
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lmq3_ld_rq_type, lmq0_pcx_pkt_addr, lmq1_pcx_pkt_addr,
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lmq2_pcx_pkt_addr, lmq3_pcx_pkt_addr, lsu_ttype_vld_m2,
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tlu_early_flush_pipe2_w, lsu_st_dcfill_size_e, mbist_dcache_write,
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mbist_dcache_read
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) ;
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output lsu_tlu_nucleus_ctxt_m ;// access is nucleus context
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output lsu_quad_word_access_g ; // 128b ld request.
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input si;
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input se;
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input sehold ;
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input rst_tri_en ;
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output so;
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input rclk ;
|
203 |
|
|
input grst_l;
|
204 |
|
|
input arst_l;
|
205 |
|
|
output dctl_rst_l;
|
206 |
|
|
|
207 |
|
|
input lsu_diag_va_prty_invrt ;
|
208 |
|
|
|
209 |
|
|
input dva_svld_e ;
|
210 |
|
|
input [15:0] dva_snp_bit_wr_en_e;
|
211 |
|
|
input [4:0] dva_snp_addr_e;
|
212 |
|
|
|
213 |
|
|
input lsu_tte_data_cp_g ; // cp bit from tlb
|
214 |
|
|
input lsu_l2fill_vld ; // fill from dfq to d$.
|
215 |
|
|
input ld_inst_vld_e ; // load accesses d$.
|
216 |
|
|
input st_inst_vld_e ; // load accesses d$.
|
217 |
|
|
input ifu_lsu_ldst_fp_e ; // fp load or store
|
218 |
|
|
input [1:0] ldst_sz_e ; // sz of ld/st xsaction.
|
219 |
|
|
|
220 |
|
|
|
221 |
|
|
input [12:11] lsu_ldst_va_b12_b11_m;
|
222 |
|
|
input [7:0] lsu_ldst_va_b7_b0_m;
|
223 |
|
|
|
224 |
|
|
input [4:0] ifu_lsu_rd_e; // primary rd of ld
|
225 |
|
|
input tlb_cam_hit ; // xlation hits in tlb.
|
226 |
|
|
// Read/Write Privileged State Register Access.
|
227 |
|
|
input [6:0] ifu_tlu_sraddr_d ; // addr of sr(st/pr)
|
228 |
|
|
|
229 |
|
|
input ifu_tlu_wsr_inst_d ; // valid wr sr(st/pr)
|
230 |
|
|
output lsu_tlu_wsr_inst_e ; // valid wr sr(st/pr)
|
231 |
|
|
|
232 |
|
|
input ifu_lsu_alt_space_d; // alternate space ld/st
|
233 |
|
|
|
234 |
|
|
input tlu_lsu_int_ldxa_vld_w2 ; // tlu ldxa data is valid (intrpt/scpd)
|
235 |
|
|
input tlu_lsu_int_ld_ill_va_w2 ; // tlu ldxa'va is invalid (intrpt/scpd)
|
236 |
|
|
|
237 |
|
|
input [1:0] tlu_lsu_ldxa_tid_w2 ; // thread id for tlu ldxa data.
|
238 |
|
|
|
239 |
|
|
input ifu_lsu_ldxa_data_vld_w2 ; // ifu ldxa data is valid
|
240 |
|
|
input ifu_lsu_ldxa_illgl_va_w2 ; // ifu ldxa with illgl va
|
241 |
|
|
input [1:0] ifu_lsu_ldxa_tid_w2 ; // thread id for ifu ldxa data.
|
242 |
|
|
input ifu_lsu_asi_rd_unc ; // unc error for tlb rd
|
243 |
|
|
|
244 |
|
|
input [3:0] tlu_lsu_tl_zero ; // trap level is zero.
|
245 |
|
|
input [1:0] ifu_lsu_thrid_s ; // thread id
|
246 |
|
|
input ifu_lsu_ldst_dbl_e ; // ldd, atomic quad.
|
247 |
|
|
|
248 |
|
|
input ld_stb_full_raw_w2 ; // full raw for load-thread0
|
249 |
|
|
input ld_sec_active ; // secondary bypassing
|
250 |
|
|
input ifu_tlu_inst_vld_m ; // inst vld in w stage
|
251 |
|
|
|
252 |
|
|
input lsu_l2fill_bendian_m ;
|
253 |
|
|
|
254 |
|
|
//input lsu_l2fill_fpld_e ; // fp load
|
255 |
|
|
output lsu_l2fill_fpld_e ; // fp load
|
256 |
|
|
input lmq0_l2fill_fpld ; // fp load
|
257 |
|
|
input lmq1_l2fill_fpld ; // fp load
|
258 |
|
|
input lmq2_l2fill_fpld ; // fp load
|
259 |
|
|
input lmq3_l2fill_fpld ; // fp load
|
260 |
|
|
|
261 |
|
|
input [3:0] cache_way_hit_buf1 ; // hit in set of cache.
|
262 |
|
|
input cache_hit;
|
263 |
|
|
|
264 |
|
|
//input [3:0] lsu_byp_misc_addr_m ; // lower 3bits of addr for ldxa/raw etc
|
265 |
|
|
|
266 |
|
|
input [1:0] lmq0_byp_misc_sz ; // size for ldxa/raw etc
|
267 |
|
|
input [1:0] lmq1_byp_misc_sz ; // size for ldxa/raw etc
|
268 |
|
|
input [1:0] lmq2_byp_misc_sz ; // size for ldxa/raw etc
|
269 |
|
|
input [1:0] lmq3_byp_misc_sz ; // size for ldxa/raw etc
|
270 |
|
|
|
271 |
|
|
input lsu_l2fill_sign_extend_m ; // l2fill requires sign-extension
|
272 |
|
|
input lsu_l1hit_sign_extend_e ; // l1hit requires sign-extension
|
273 |
|
|
input [3:0] tlu_lsu_pstate_cle ; // current little endian
|
274 |
|
|
input [3:0] tlu_lsu_pstate_am ; // address mask
|
275 |
|
|
input [39:10] tlb_pgnum ;
|
276 |
|
|
input tlb_demap_nctxt; // demap with nctxt
|
277 |
|
|
input tlb_demap_pctxt; // demap with pctxt
|
278 |
|
|
input tlb_demap_sctxt; // demap with sctxt
|
279 |
|
|
input tlb_demap_actxt; // demap w autodemap ctxt
|
280 |
|
|
input [1:0] tlb_demap_thrid; // demap thrid
|
281 |
|
|
|
282 |
|
|
input ifu_lsu_casa_e ; // compare-swap instr
|
283 |
|
|
input ifu_lsu_ldstub_e ; // ldstub
|
284 |
|
|
input ifu_lsu_swap_e ; // swap
|
285 |
|
|
|
286 |
|
|
|
287 |
|
|
input lsu_atm_st_cmplt_e ; // atm st ack will restart thread
|
288 |
|
|
input lsu_cpx_pkt_atm_st_cmplt ; // applies to atomic ld also.
|
289 |
|
|
|
290 |
|
|
input spu_lsu_ldxa_data_vld_w2 ; // ldxa data from spu is valid
|
291 |
|
|
input spu_lsu_ldxa_illgl_va_w2 ; // ldxa data from spu with illgl va
|
292 |
|
|
input [1:0] spu_lsu_ldxa_tid_w2 ; // ldxa data from spu is valid
|
293 |
|
|
input [1:0] spu_lsu_stxa_ack_tid ; // stxa data from spu is valid
|
294 |
|
|
input spu_lsu_stxa_ack ; // write to sdata reg complete
|
295 |
|
|
input spu_lsu_unc_error_w2 ;
|
296 |
|
|
input spu_lsu_int_w2 ; // spu disrupting trap.
|
297 |
|
|
|
298 |
|
|
input tlu_lsu_stxa_ack ; // for mmu reads/writes/demaps
|
299 |
|
|
input [1:0] tlu_lsu_stxa_ack_tid ; // for mmu reads/writes/demaps - tid
|
300 |
|
|
|
301 |
|
|
input lsu_tlb_invert_endian_g ;
|
302 |
|
|
//input lsu_ncache_ld_e ; // non-cacheable ld from dfq
|
303 |
|
|
input lmq0_ncache_ld;
|
304 |
|
|
input lmq1_ncache_ld;
|
305 |
|
|
input lmq2_ncache_ld;
|
306 |
|
|
input lmq3_ncache_ld;
|
307 |
|
|
|
308 |
|
|
|
309 |
|
|
input ifu_tlu_mb_inst_e ; // membar instruction
|
310 |
|
|
input ifu_tlu_flsh_inst_e ; // flush instruction
|
311 |
|
|
|
312 |
|
|
input [3:0] lsu_stb_empty ; // thread's stb is empty
|
313 |
|
|
|
314 |
|
|
//input tlu_dtlb_wr_vld_g ;
|
315 |
|
|
input tlu_dtlb_tag_rd_g ;
|
316 |
|
|
input tlu_dtlb_data_rd_g ;
|
317 |
|
|
input tlu_dtlb_dmp_vld_g ;
|
318 |
|
|
input tlu_dtlb_dmp_all_g ;
|
319 |
|
|
input tlu_dtlb_rw_index_vld_g ;
|
320 |
|
|
input tlu_dtlb_invalidate_all_g ;
|
321 |
|
|
|
322 |
|
|
input lsu_st_wr_dcache ;
|
323 |
|
|
|
324 |
|
|
input tlu_lsu_asi_update_m ; // update asi
|
325 |
|
|
input [1:0] tlu_lsu_tid_m ; // thread for asi update
|
326 |
|
|
input [3:0] lsu_rd_dtag_parity_g; // calculated tag parity
|
327 |
|
|
|
328 |
|
|
input dcache_rparity_err_wb; // calculated tag parity
|
329 |
|
|
|
330 |
|
|
input lsu_diagnstc_wr_data_b0 ;
|
331 |
|
|
input lsu_byp_ldd_oddrd_m ; // rd fill for non-alt ldd
|
332 |
|
|
|
333 |
|
|
input [3:0] tlu_lsu_redmode ; // redmode
|
334 |
|
|
input [3:0] tlu_lsu_redmode_rst_d1 ; // redmode
|
335 |
|
|
//input [2:0] const_cpuid ; // cpu's id
|
336 |
|
|
input [3:0] dva_vld_m ; // valid bits for cache.
|
337 |
|
|
output [3:0] dva_vld_m_bf;
|
338 |
|
|
|
339 |
|
|
input [1:0] lsu_dfill_tid_e ; // thread id
|
340 |
|
|
input ifu_lsu_asi_ack; // asi ack from ifu
|
341 |
|
|
|
342 |
|
|
input [3:0] lsu_intrpt_cmplt ; // intrpt can restart thread
|
343 |
|
|
//input [8:0] lsu_iobrdge_tap_rq_type ;
|
344 |
|
|
input [8:8] lsu_iobrdge_tap_rq_type_b8 ;
|
345 |
|
|
input [6:3] lsu_iobrdge_tap_rq_type_b6_b3 ;
|
346 |
|
|
input [1:0] lsu_iobrdge_tap_rq_type_b1_b0 ;
|
347 |
|
|
|
348 |
|
|
input lsu_iobrdge_fwd_pkt_vld ;
|
349 |
|
|
|
350 |
|
|
input lsu_cpx_ld_dtag_perror_e ; // dtag parity error on issue
|
351 |
|
|
input lsu_cpx_ld_dcache_perror_e ;// dcache parity error on issue
|
352 |
|
|
//input [1:1] lsu_cpx_atm_st_err ; // atomic st error field
|
353 |
|
|
input [1:0] lsu_cpx_pkt_ld_err ; // err field - cpx ld pkt
|
354 |
|
|
input [3:0] ifu_lsu_nceen ; // uncorrectible error enable
|
355 |
|
|
input tlu_lsu_ldxa_async_data_vld ; // tlu_lsu_ldxa_data_vld is for async op.
|
356 |
|
|
input [3:0] tlu_lsu_hpv_priv ; // hypervisor privilege modified
|
357 |
|
|
input [3:0] tlu_lsu_hpstate_en ; // enable bit from hpstate
|
358 |
|
|
|
359 |
|
|
input ifu_lsu_memref_d;
|
360 |
|
|
input ifu_lsu_pref_inst_e ; // prefetch inst
|
361 |
|
|
input lsu_pref_pcx_req ; // pref sent to pcx
|
362 |
|
|
|
363 |
|
|
input lsu_cpx_pkt_prefetch2 ; // ld is prefetch
|
364 |
|
|
|
365 |
|
|
// pref counter
|
366 |
|
|
input [3:0] lsu_ld_pcx_rq_sel_d2 ;
|
367 |
|
|
input lsu_pcx_req_squash_d1;
|
368 |
|
|
|
369 |
|
|
input lsu_bld_helper_cmplt_m ; // bld helper completes.
|
370 |
|
|
input [2:0] lsu_bld_cnt_m ;
|
371 |
|
|
input lsu_bld_reset ;
|
372 |
|
|
|
373 |
|
|
output [3:0] lsu_no_spc_pref;
|
374 |
|
|
|
375 |
|
|
input ffu_lsu_blk_st_e ; // blk st helper signalled by ffu
|
376 |
|
|
input [3:0] lsu_stb_rmo_st_issue ; // thread's stb issues rmo st
|
377 |
|
|
input [3:0] lsu_cpx_rmo_st_ack ; // rmo ack clears
|
378 |
|
|
|
379 |
|
|
input [3:0] lsu_dfq_flsh_cmplt ;
|
380 |
|
|
|
381 |
|
|
input stb_cam_hit ;
|
382 |
|
|
|
383 |
|
|
input ifu_tlu_flush_m;
|
384 |
|
|
|
385 |
|
|
output ifu_tlu_flush_fd_w;
|
386 |
|
|
output ifu_tlu_flush_fd2_w;
|
387 |
|
|
output ifu_tlu_flush_fd3_w;
|
388 |
|
|
output ifu_lsu_flush_w;
|
389 |
|
|
|
390 |
|
|
input [3:0] ctu_sscan_tid ;
|
391 |
|
|
|
392 |
|
|
//input tte_data_perror_corr ;
|
393 |
|
|
input tte_data_perror_unc ;
|
394 |
|
|
input asi_tte_data_perror ;
|
395 |
|
|
input asi_tte_tag_perror ;
|
396 |
|
|
|
397 |
|
|
input [5:0] tlu_dtlb_rw_index_g ;
|
398 |
|
|
|
399 |
|
|
input lsu_local_early_flush_g ;
|
400 |
|
|
|
401 |
|
|
//input lsu_error_pa_b39_m ;
|
402 |
|
|
|
403 |
|
|
input lsu_dfq_vld;
|
404 |
|
|
|
405 |
|
|
input gdbginit_l ;
|
406 |
|
|
input dc_direct_map ;
|
407 |
|
|
|
408 |
|
|
output [1:0] lsu_tlu_thrid_d ;
|
409 |
|
|
|
410 |
|
|
output [3:0] lsu_diagnstc_data_sel ;
|
411 |
|
|
output [3:0] lsu_diagnstc_va_sel ;
|
412 |
|
|
|
413 |
|
|
output [2:0] lsu_err_addr_sel ;
|
414 |
|
|
|
415 |
|
|
output [15:0] dva_bit_wr_en_e;
|
416 |
|
|
output [10:6] dva_wr_adr_e;
|
417 |
|
|
|
418 |
|
|
output lsu_exu_ldst_miss_w2 ; // load misses in d$.
|
419 |
|
|
//output [3:0] lsu_way_hit ; // ld/st access hits in d$.
|
420 |
|
|
output lsu_exu_dfill_vld_w2 ; // data fill to irf(exu).
|
421 |
|
|
output lsu_ffu_ld_vld ; // fp load writes to frf
|
422 |
|
|
output lsu_ld_miss_wb ; // load misses in d$.
|
423 |
|
|
//output lsu_ld_hit_wb ; // load hits in d$.
|
424 |
|
|
|
425 |
|
|
output lsu_dtlb_bypass_e ; // dtlb is bypassed
|
426 |
|
|
|
427 |
|
|
output [`LMQ_WIDTH-1:40] ld_pcx_pkt_g ; // ld miss pkt for thread.
|
428 |
|
|
output tlb_ldst_cam_vld ;
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
//output stxa_internal ; // internal stxa, stg g
|
432 |
|
|
output ldxa_internal ; // internal ldxa, stg g
|
433 |
|
|
|
434 |
|
|
output lsu_ifu_ldsta_internal_e ; // any internal asi
|
435 |
|
|
output [3:0] lsu_ifu_ldst_cmplt ;
|
436 |
|
|
output [3:0] lsu_ifu_itlb_en ;
|
437 |
|
|
output [3:0] lsu_ifu_icache_en ;
|
438 |
|
|
|
439 |
|
|
|
440 |
|
|
output [3:0] lmq_byp_data_en_w2 ;
|
441 |
|
|
|
442 |
|
|
output [3:0] lmq_byp_data_fmx_sel ; // final data sel for lmq byp
|
443 |
|
|
output [3:0] lmq_byp_data_mxsel0 ; // ldxa vs stb bypass data sel.
|
444 |
|
|
output [3:0] lmq_byp_data_mxsel1 ; // ldxa vs stb bypass data sel.
|
445 |
|
|
output [3:0] lmq_byp_data_mxsel2 ; // ldxa vs stb bypass data sel.
|
446 |
|
|
output [3:0] lmq_byp_data_mxsel3 ; // ldxa vs stb bypass data sel.
|
447 |
|
|
output [2:0] lmq_byp_ldxa_mxsel0 ; // ldxa data sel - thread0
|
448 |
|
|
output [2:0] lmq_byp_ldxa_mxsel1 ; // ldxa data sel - thread1
|
449 |
|
|
output [2:0] lmq_byp_ldxa_mxsel2 ; // ldxa data sel - thread2
|
450 |
|
|
output [2:0] lmq_byp_ldxa_mxsel3 ; // ldxa data sel - thread3
|
451 |
|
|
output [2:0] lsu_ld_thrd_byp_sel_e ;
|
452 |
|
|
|
453 |
|
|
output [15:0] dcache_byte_wr_en_e ; // 16-byte write enable mask.
|
454 |
|
|
|
455 |
|
|
output lsu_dcache_wr_vld_e ; // write to dcache.
|
456 |
|
|
|
457 |
|
|
output lsu_ldstub_g ; // ldstub(a) instruction
|
458 |
|
|
output lsu_swap_g ; // swap(a) instruction
|
459 |
|
|
output lsu_tlu_dtlb_done; // dtlb rd/dmp/wr cmplt
|
460 |
|
|
output [1:0] lsu_exu_thr_m ;
|
461 |
|
|
|
462 |
|
|
output merge7_sel_byte0_m;
|
463 |
|
|
output merge7_sel_byte7_m;
|
464 |
|
|
|
465 |
|
|
output merge6_sel_byte1_m;
|
466 |
|
|
output merge6_sel_byte6_m;
|
467 |
|
|
|
468 |
|
|
output merge5_sel_byte2_m;
|
469 |
|
|
output merge5_sel_byte5_m;
|
470 |
|
|
|
471 |
|
|
output merge4_sel_byte3_m;
|
472 |
|
|
output merge4_sel_byte4_m;
|
473 |
|
|
|
474 |
|
|
output merge3_sel_byte0_m;
|
475 |
|
|
output merge3_sel_byte3_m;
|
476 |
|
|
output merge3_sel_byte4_m;
|
477 |
|
|
output merge3_sel_byte7_default_m;
|
478 |
|
|
output merge3_sel_byte_m ;
|
479 |
|
|
|
480 |
|
|
output merge2_sel_byte1_m;
|
481 |
|
|
output merge2_sel_byte2_m;
|
482 |
|
|
output merge2_sel_byte5_m;
|
483 |
|
|
output merge2_sel_byte6_default_m;
|
484 |
|
|
output merge2_sel_byte_m ;
|
485 |
|
|
|
486 |
|
|
output merge0_sel_byte0_m, merge0_sel_byte1_m;
|
487 |
|
|
output merge0_sel_byte2_m, merge0_sel_byte3_default_m;
|
488 |
|
|
|
489 |
|
|
output merge0_sel_byte4_m, merge0_sel_byte5_m;
|
490 |
|
|
output merge0_sel_byte6_m, merge0_sel_byte7_default_m;
|
491 |
|
|
|
492 |
|
|
output merge1_sel_byte0_m, merge1_sel_byte1_m;
|
493 |
|
|
output merge1_sel_byte2_m, merge1_sel_byte3_default_m;
|
494 |
|
|
output merge1_sel_byte4_m, merge1_sel_byte5_m;
|
495 |
|
|
output merge1_sel_byte6_m, merge1_sel_byte7_default_m;
|
496 |
|
|
|
497 |
|
|
output merge0_sel_byte_1h_m ;
|
498 |
|
|
|
499 |
|
|
output merge1_sel_byte_1h_m, merge1_sel_byte_2h_m ;
|
500 |
|
|
|
501 |
|
|
output lsu_dtlb_cam_real_e ;
|
502 |
|
|
output lsu_dtagv_wr_vld_e ;
|
503 |
|
|
|
504 |
|
|
output lsu_dtag_wrreq_x_e ;
|
505 |
|
|
output lsu_dtag_index_sel_x_e ;
|
506 |
|
|
|
507 |
|
|
output lsu_dtlb_wr_vld_e ;
|
508 |
|
|
output lsu_dtlb_tag_rd_e ;
|
509 |
|
|
output lsu_dtlb_data_rd_e ;
|
510 |
|
|
output lsu_dtlb_dmp_vld_e ;
|
511 |
|
|
output lsu_dtlb_dmp_all_e ;
|
512 |
|
|
output lsu_dtlb_rwindex_vld_e ;
|
513 |
|
|
output lsu_dtlb_invalid_all_l_m ;
|
514 |
|
|
output lsu_tlu_tlb_ld_inst_m ;
|
515 |
|
|
output lsu_tlu_tlb_st_inst_m ;
|
516 |
|
|
output [1:0] lsu_tlu_tlb_access_tid_m ;
|
517 |
|
|
output lsu_tlb_data_rd_vld_g ;
|
518 |
|
|
|
519 |
|
|
|
520 |
|
|
output [3:0] lsu_tlb_st_sel_m ;
|
521 |
|
|
|
522 |
|
|
output lsu_va_wtchpt0_wr_en_l;
|
523 |
|
|
output lsu_va_wtchpt1_wr_en_l;
|
524 |
|
|
output lsu_va_wtchpt2_wr_en_l;
|
525 |
|
|
output lsu_va_wtchpt3_wr_en_l;
|
526 |
|
|
|
527 |
|
|
output thread0_m;
|
528 |
|
|
output thread1_m;
|
529 |
|
|
output thread2_m;
|
530 |
|
|
output thread3_m;
|
531 |
|
|
|
532 |
|
|
output lsu_dctldp_thread0_m;
|
533 |
|
|
output lsu_dctldp_thread1_m;
|
534 |
|
|
output lsu_dctldp_thread2_m;
|
535 |
|
|
output lsu_dctldp_thread3_m;
|
536 |
|
|
|
537 |
|
|
output thread0_g;
|
538 |
|
|
output thread1_g;
|
539 |
|
|
output thread2_g;
|
540 |
|
|
output thread3_g;
|
541 |
|
|
|
542 |
|
|
output lsu_tlu_nonalt_ldst_m ; // non-alternate load or store
|
543 |
|
|
output lsu_tlu_xslating_ldst_m ;// xslating ldst,atomic etc
|
544 |
|
|
|
545 |
|
|
output [2:0] lsu_tlu_ctxt_sel_m; // context selected:0-p,1-s,2-n
|
546 |
|
|
output lsu_tlu_write_op_m; // fault occurs for data write operation
|
547 |
|
|
|
548 |
|
|
output lsu_dtlb_addr_mask_l_e ; // address mask applies
|
549 |
|
|
|
550 |
|
|
|
551 |
|
|
output dva_din_e;
|
552 |
|
|
|
553 |
|
|
output lsu_diagnstc_dtagv_prty_invrt_e ;
|
554 |
|
|
|
555 |
|
|
output lsu_ifu_asi_load; // asi load to ifu
|
556 |
|
|
output [1:0] lsu_ifu_asi_thrid; // asi event thrid to ifu
|
557 |
|
|
output lsu_ifu_asi_vld; // asi event vld - ld+st
|
558 |
|
|
output lsu_quad_asi_e ;
|
559 |
|
|
//output lsu_tlu_64kpg_hit_g ; // 64k page page accessed
|
560 |
|
|
|
561 |
|
|
output lsu_local_ldxa_sel_g;
|
562 |
|
|
output [3:0] lsu_dtag_rsel_m ; // dtag way sel
|
563 |
|
|
|
564 |
|
|
output lsu_tlbop_force_swo ;
|
565 |
|
|
output [2:0] lsu_atomic_pkt2_bsel_g ;
|
566 |
|
|
output lsu_dcache_tag_perror_g ; // dcache tag parity error
|
567 |
|
|
output lsu_dcache_data_perror_g ; // dcache data parity error
|
568 |
|
|
|
569 |
|
|
output lsu_ifu_l2_unc_error ; // l2 uncorrectible error
|
570 |
|
|
output lsu_ifu_l2_corr_error ; // l2 correctible error
|
571 |
|
|
output lsu_ifu_dcache_data_perror ; // dcache data parity error
|
572 |
|
|
output lsu_ifu_dcache_tag_perror ; // dcache tag parity error
|
573 |
|
|
output [1:0] lsu_ifu_error_tid ; // thread id for error
|
574 |
|
|
output lsu_ifu_io_error ; // error on io ld
|
575 |
|
|
//output [1:0] lsu_tlu_derr_tid_g ; // daccess error tid
|
576 |
|
|
|
577 |
|
|
output lsu_tlu_squash_va_oor_m ; // squash va_oor for mem-op.
|
578 |
|
|
output lsu_squash_va_oor_m ; // squash va_oor for mem-op.
|
579 |
|
|
|
580 |
|
|
output tlb_cam_hit_g ; // xlation hits in tlb.
|
581 |
|
|
|
582 |
|
|
output lsu_st_hw_le_g;
|
583 |
|
|
output lsu_st_w_or_dbl_le_g;
|
584 |
|
|
output lsu_st_x_le_g;
|
585 |
|
|
output lsu_swap_sel_default_g;
|
586 |
|
|
output lsu_swap_sel_default_byte_7_2_g;
|
587 |
|
|
|
588 |
|
|
output lsu_st_rmo_m ; // rmo store in m stage
|
589 |
|
|
output lsu_bst_in_pipe_m ; // 1st helper for bst.
|
590 |
|
|
output lsu_snap_blk_st_m ; // snap blk st state
|
591 |
|
|
output lsu_blk_st_m ; // blk st in m
|
592 |
|
|
output [39:10] lsu_blkst_pgnum_m ;
|
593 |
|
|
output lsu_ffu_blk_asi_e ; // blk
|
594 |
|
|
output lsu_blk_asi_m ;
|
595 |
|
|
|
596 |
|
|
output lsu_nonalt_nucl_access_m ;
|
597 |
|
|
|
598 |
|
|
//output [3:0] lsu_spu_stb_empty ;
|
599 |
|
|
|
600 |
|
|
output dcache_alt_mx_sel_e;
|
601 |
|
|
output dcache_alt_mx_sel_e_bf;
|
602 |
|
|
output dcache_rvld_e;
|
603 |
|
|
|
604 |
|
|
output lsu_dc_iob_access_e ; // dcache iob access
|
605 |
|
|
|
606 |
|
|
output lsu_ifu_ldst_miss_w ;
|
607 |
|
|
|
608 |
|
|
output lsu_ifu_dc_parity_error_w2;
|
609 |
|
|
|
610 |
|
|
output lsu_ldst_inst_vld_e;
|
611 |
|
|
|
612 |
|
|
output lsu_local_ldxa_tlbrd_sel_g;
|
613 |
|
|
output lsu_local_diagnstc_tagrd_sel_g;
|
614 |
|
|
output lsu_va_wtchpt_sel_g;
|
615 |
|
|
|
616 |
|
|
|
617 |
|
|
input [7:0] asi_d;
|
618 |
|
|
input [7:0] lsu_dctl_asi_state_m;
|
619 |
|
|
|
620 |
|
|
output [3:0] asi_state_wr_thrd;
|
621 |
|
|
output thread0_d;
|
622 |
|
|
output thread1_d;
|
623 |
|
|
output thread2_d;
|
624 |
|
|
output thread3_d;
|
625 |
|
|
output tlu_lsu_asi_update_g;
|
626 |
|
|
|
627 |
|
|
output [3:0] pctxt_state_wr_thrd ;
|
628 |
|
|
output [3:0] sctxt_state_wr_thrd ;
|
629 |
|
|
|
630 |
|
|
output thread_pctxt;
|
631 |
|
|
output thread_sctxt;
|
632 |
|
|
|
633 |
|
|
output thread_actxt;
|
634 |
|
|
output thread_default;
|
635 |
|
|
|
636 |
|
|
output thread0_ctxt;
|
637 |
|
|
output thread1_ctxt;
|
638 |
|
|
output thread2_ctxt;
|
639 |
|
|
output thread3_ctxt;
|
640 |
|
|
|
641 |
|
|
output [3:0] pid_state_wr_en;
|
642 |
|
|
output thread0_e;
|
643 |
|
|
output thread1_e;
|
644 |
|
|
output thread2_e;
|
645 |
|
|
output thread3_e;
|
646 |
|
|
|
647 |
|
|
output dfture_tap_wr_mx_sel;
|
648 |
|
|
output [3:0] lctl_rst;
|
649 |
|
|
output [3:0] lsu_ctl_state_wr_en;
|
650 |
|
|
output [3:0] lsuctl_ctlbits_wr_en;
|
651 |
|
|
output [3:0] dfture_tap_rd_en;
|
652 |
|
|
|
653 |
|
|
output bist_tap_wr_en;
|
654 |
|
|
output bistctl_wr_en;
|
655 |
|
|
output bist_ctl_reg_wr_en;
|
656 |
|
|
output mrgn_tap_wr_en;
|
657 |
|
|
|
658 |
|
|
output ldiagctl_wr_en;
|
659 |
|
|
|
660 |
|
|
output [3:0] misc_ctl_sel_din ;
|
661 |
|
|
|
662 |
|
|
output [2:0] lsu_asi_sel_fmx1;
|
663 |
|
|
output [2:0] lsu_asi_sel_fmx2;
|
664 |
|
|
|
665 |
|
|
|
666 |
|
|
output tlb_access_en0_g;
|
667 |
|
|
output tlb_access_en1_g;
|
668 |
|
|
output tlb_access_en2_g;
|
669 |
|
|
output tlb_access_en3_g;
|
670 |
|
|
|
671 |
|
|
output tlb_access_sel_thrd0;
|
672 |
|
|
output tlb_access_sel_thrd1;
|
673 |
|
|
output tlb_access_sel_thrd2;
|
674 |
|
|
output tlb_access_sel_default;
|
675 |
|
|
|
676 |
|
|
input [7:0] lsu_ldst_va_g;
|
677 |
|
|
|
678 |
|
|
output mrgnctl_wr_en;
|
679 |
|
|
|
680 |
|
|
input lsu_ifu_err_addr_b39;
|
681 |
|
|
|
682 |
|
|
input [5:0] lsu_dp_ctl_reg0;
|
683 |
|
|
input [5:0] lsu_dp_ctl_reg1;
|
684 |
|
|
input [5:0] lsu_dp_ctl_reg2;
|
685 |
|
|
input [5:0] lsu_dp_ctl_reg3;
|
686 |
|
|
|
687 |
|
|
input ldd_in_dfq_out; //from qctl2
|
688 |
|
|
|
689 |
|
|
|
690 |
|
|
output hpv_priv_m;
|
691 |
|
|
output hpstate_en_m;
|
692 |
|
|
|
693 |
|
|
output dcache_arry_data_sel_m;
|
694 |
|
|
|
695 |
|
|
output dtlb_bypass_m;
|
696 |
|
|
|
697 |
|
|
output lsu_alt_space_m;
|
698 |
|
|
output atomic_m;
|
699 |
|
|
|
700 |
|
|
output ldst_dbl_m;
|
701 |
|
|
output fp_ldst_m;
|
702 |
|
|
|
703 |
|
|
output lda_internal_m;
|
704 |
|
|
output sta_internal_m;
|
705 |
|
|
output cam_real_m;
|
706 |
|
|
|
707 |
|
|
output data_rd_vld_g;
|
708 |
|
|
output tag_rd_vld_g;
|
709 |
|
|
output [1:0] ldst_sz_m;
|
710 |
|
|
output asi_internal_m;
|
711 |
|
|
|
712 |
|
|
// output ld_inst_vld_unflushed;
|
713 |
|
|
// output st_inst_vld_unflushed;
|
714 |
|
|
|
715 |
|
|
output rd_only_ltlb_asi_e;
|
716 |
|
|
output wr_only_ltlb_asi_e;
|
717 |
|
|
output dfill_tlb_asi_e;
|
718 |
|
|
output ifill_tlb_asi_e;
|
719 |
|
|
|
720 |
|
|
output nofault_asi_m;
|
721 |
|
|
output as_if_user_asi_m;
|
722 |
|
|
|
723 |
|
|
output atomic_asi_m;
|
724 |
|
|
output phy_use_ec_asi_m;
|
725 |
|
|
output phy_byp_ec_asi_m;
|
726 |
|
|
|
727 |
|
|
output quad_asi_m;
|
728 |
|
|
output binit_quad_asi_m;
|
729 |
|
|
output blk_asi_m;
|
730 |
|
|
|
731 |
|
|
output recognized_asi_m;
|
732 |
|
|
output strm_asi_m;
|
733 |
|
|
output mmu_rd_only_asi_m;
|
734 |
|
|
output rd_only_asi_m;
|
735 |
|
|
output wr_only_asi_m;
|
736 |
|
|
output unimp_asi_m;
|
737 |
|
|
|
738 |
|
|
output va_wtchpt_cmp_en_m;
|
739 |
|
|
|
740 |
|
|
output lsu_tlu_async_ttype_vld_w2 ; // daccess error - asynchronous
|
741 |
|
|
output [6:0] lsu_tlu_async_ttype_w2 ;
|
742 |
|
|
output [1:0] lsu_tlu_async_tid_w2 ; // asynchronous trap - thread
|
743 |
|
|
|
744 |
|
|
output [5:0] async_tlb_index ;
|
745 |
|
|
|
746 |
|
|
//=========================================
|
747 |
|
|
//dc_fill CP
|
748 |
|
|
//=========================================
|
749 |
|
|
output l2fill_vld_m; //to qdp1
|
750 |
|
|
output [3:0] ld_thrd_byp_mxsel_m ; //to qdp1
|
751 |
|
|
output [7:0] morphed_addr_m; //to dcdp
|
752 |
|
|
|
753 |
|
|
|
754 |
|
|
output signed_ldst_byte_m; //to dcdp
|
755 |
|
|
// output unsigned_ldst_byte_m; //to dcdp
|
756 |
|
|
output signed_ldst_hw_m; //to dcdp
|
757 |
|
|
// output unsigned_ldst_hw_m; //to dcdp
|
758 |
|
|
output signed_ldst_w_m; //to dcdp
|
759 |
|
|
// output unsigned_ldst_w_m; //to dcdp
|
760 |
|
|
|
761 |
|
|
output lsu_tlb_asi_data_perr_g ;
|
762 |
|
|
output lsu_tlb_asi_tag_perr_g ;
|
763 |
|
|
|
764 |
|
|
output [14:13] lsu_sscan_data ;
|
765 |
|
|
|
766 |
|
|
output [3:0] lsu_ld_inst_vld_g ;
|
767 |
|
|
|
768 |
|
|
output [1:0] lsu_dcache_rand;
|
769 |
|
|
output [1:0] lsu_encd_way_hit;
|
770 |
|
|
output lsu_way_hit_or;
|
771 |
|
|
// output lsu_quad_asi_g;
|
772 |
|
|
|
773 |
|
|
output lsu_memref_m ;
|
774 |
|
|
output lsu_flsh_inst_m ;
|
775 |
|
|
|
776 |
|
|
output lsu_ifu_asi_data_en_l ;
|
777 |
|
|
|
778 |
|
|
|
779 |
|
|
//dcfill_addr [10:0]
|
780 |
|
|
input [7:0] dcache_iob_addr_e;
|
781 |
|
|
input [6:0] mbist_dcache_index;
|
782 |
|
|
input mbist_dcache_word;
|
783 |
|
|
input [10:0] lsu_diagnstc_wr_addr_e;
|
784 |
|
|
input [10:0] st_dcfill_addr;
|
785 |
|
|
output [10:3] lsu_dcache_fill_addr_e;
|
786 |
|
|
output [10:4] lsu_dcache_fill_addr_e_err;
|
787 |
|
|
|
788 |
|
|
input lsu_dfq_ld_vld;
|
789 |
|
|
input lsu_dfq_st_vld;
|
790 |
|
|
|
791 |
|
|
output [3:0] lsu_thread_g;
|
792 |
|
|
|
793 |
|
|
//=========================================
|
794 |
|
|
//LMQ thread sel
|
795 |
|
|
//=========================================
|
796 |
|
|
input lmq0_ldd_vld; //from qdp1
|
797 |
|
|
input lmq1_ldd_vld;
|
798 |
|
|
input lmq2_ldd_vld;
|
799 |
|
|
input lmq3_ldd_vld;
|
800 |
|
|
output lmq_ldd_vld; //to qctl2
|
801 |
|
|
|
802 |
|
|
input [1:0] lsu_dfq_byp_tid; //from qdp2
|
803 |
|
|
input dfq_byp_ff_en; //from qctl2
|
804 |
|
|
|
805 |
|
|
input [1:0] lsu_dcache_iob_way_e; //from qdp2
|
806 |
|
|
|
807 |
|
|
input [1:0] mbist_dcache_way;
|
808 |
|
|
output [3:0] lsu_bist_rsel_way_e;
|
809 |
|
|
|
810 |
|
|
input [1:0] lsu_diagnstc_wr_way_e ; //from dctldp
|
811 |
|
|
|
812 |
|
|
input [1:0] lsu_st_way_e; //from qdp2
|
813 |
|
|
|
814 |
|
|
input [1:0] lmq0_pcx_pkt_way; //from qctl1
|
815 |
|
|
input [1:0] lmq1_pcx_pkt_way;
|
816 |
|
|
input [1:0] lmq2_pcx_pkt_way;
|
817 |
|
|
input [1:0] lmq3_pcx_pkt_way;
|
818 |
|
|
output [3:0] lsu_dcache_fill_way_e;
|
819 |
|
|
|
820 |
|
|
|
821 |
|
|
input [2:0] lmq0_ld_rq_type ; // for identifying atomic ld.
|
822 |
|
|
input [2:0] lmq1_ld_rq_type ; // for identifying atomic ld.
|
823 |
|
|
input [2:0] lmq2_ld_rq_type ; // for identifying atomic ld.
|
824 |
|
|
input [2:0] lmq3_ld_rq_type ; // for identifying atomic ld.
|
825 |
|
|
|
826 |
|
|
input [10:0] lmq0_pcx_pkt_addr;
|
827 |
|
|
input [10:0] lmq1_pcx_pkt_addr;
|
828 |
|
|
input [10:0] lmq2_pcx_pkt_addr;
|
829 |
|
|
input [10:0] lmq3_pcx_pkt_addr;
|
830 |
|
|
|
831 |
|
|
output lmq_ld_addr_b3;
|
832 |
|
|
|
833 |
|
|
output [3:0] lsu_outstanding_rmo_st_max;
|
834 |
|
|
|
835 |
|
|
input lsu_ttype_vld_m2;
|
836 |
|
|
input tlu_early_flush_pipe2_w;
|
837 |
|
|
input [1:0] lsu_st_dcfill_size_e;
|
838 |
|
|
|
839 |
|
|
input mbist_dcache_write;
|
840 |
|
|
input mbist_dcache_read;
|
841 |
|
|
|
842 |
|
|
output lsu_dcfill_data_mx_sel_e;
|
843 |
|
|
|
844 |
|
|
wire [3:0] ld_thrd_byp_sel_e ;
|
845 |
|
|
wire ifu_asi_vld,ifu_asi_vld_d1 ;
|
846 |
|
|
wire [1:0] dcache_wr_size_e ;
|
847 |
|
|
wire lsu_ncache_ld_e;
|
848 |
|
|
wire lsu_diagnstc_wr_src_sel_e ; // dcache/dtag/v write - diag
|
849 |
|
|
|
850 |
|
|
wire dctl_flush_pipe_w ; // flush pipe due to error
|
851 |
|
|
wire dctl_early_flush_w;
|
852 |
|
|
|
853 |
|
|
wire [10:0] lmq_pcx_pkt_addr;
|
854 |
|
|
wire [2:0] lmq_ld_rq_type_e;
|
855 |
|
|
|
856 |
|
|
wire [10:0] dcache_fill_addr_e;
|
857 |
|
|
wire [2:0] dcache_wr_addr_e ;
|
858 |
|
|
wire lsuctl_dtlb_byp_e ;
|
859 |
|
|
|
860 |
|
|
wire cam_perr_unc0,asi_data_perr0,asi_tag_perr0,ifu_unc_err0 ;
|
861 |
|
|
wire cam_perr_unc1,asi_data_perr1,asi_tag_perr1,ifu_unc_err1 ;
|
862 |
|
|
wire cam_perr_unc2,asi_data_perr2,asi_tag_perr2,ifu_unc_err2 ;
|
863 |
|
|
wire cam_perr_unc3,asi_data_perr3,asi_tag_perr3,ifu_unc_err3 ;
|
864 |
|
|
wire cam_perr_unc_e, asi_data_perr_e,asi_tag_perr_e,ifu_unc_err_e ;
|
865 |
|
|
wire cam_perr_unc_m, asi_data_perr_m,asi_tag_perr_m,ifu_unc_err_m ;
|
866 |
|
|
wire cam_perr_unc_g, asi_data_perr_g,asi_tag_perr_g,ifu_unc_err_g ;
|
867 |
|
|
//wire cam_real_err_e, cam_real_err_m ;
|
868 |
|
|
wire [3:0] squash_byp_cmplt,squash_byp_cmplt_m, squash_byp_cmplt_g ;
|
869 |
|
|
wire ld_inst_vld_m,ld_inst_vld_g ;
|
870 |
|
|
wire st_inst_vld_m,st_inst_vld_g ;
|
871 |
|
|
wire fp_ldst_m,fp_ldst_g,fp_ldst_w2 ;
|
872 |
|
|
wire lsu_ld_hit_wb, lsu_ld_miss_wb ;
|
873 |
|
|
wire [3:0] lsu_way_hit ;
|
874 |
|
|
wire [1:0] ldst_sz_m,ldst_sz_g ;
|
875 |
|
|
wire [4:0] ld_rd_m, ld_rd_g ;
|
876 |
|
|
wire lsu_dtlb_bypass_g,dtlb_bypass_e,dtlb_bypass_m ;
|
877 |
|
|
wire [6:0] lsu_sraddr_e ;
|
878 |
|
|
//wire lsu_rsr_inst_e,lsu_rsr_inst_m, lsu_rsr_inst_w ;
|
879 |
|
|
wire lsu_wsr_inst_e;
|
880 |
|
|
wire pctxt_state_en, sctxt_state_en ;
|
881 |
|
|
wire asi_state_wr_en ;
|
882 |
|
|
//wire [3:0] pctxt_state_rd_en, sctxt_state_rd_en ;
|
883 |
|
|
wire lsu_alt_space_m,lsu_alt_space_g ;
|
884 |
|
|
wire ldxa_internal, stxa_internal ;
|
885 |
|
|
wire lsu_ctl_state_en;
|
886 |
|
|
//wire [3:0] lsu_ctl_state_rd_en;
|
887 |
|
|
wire [3:0] lsu_ctl_state_wr_en ;
|
888 |
|
|
//wire [7:0] imm_asi_e,imm_asi_m,imm_asi_g ;
|
889 |
|
|
//wire imm_asi_vld_e,imm_asi_vld_m,imm_asi_vld_g;
|
890 |
|
|
//wire [7:0] asi_state0,asi_state1,asi_state2,asi_state3 ;
|
891 |
|
|
|
892 |
|
|
wire ldsta_internal_e,sta_internal_e,lda_internal_e;
|
893 |
|
|
wire sta_internal_m,lda_internal_m;
|
894 |
|
|
wire [7:0] asi_d ;
|
895 |
|
|
wire [1:0] thrid_d,thrid_e,thrid_m, thrid_g, thrid_w2, thrid_w3, ldxa_thrid_w2 ;
|
896 |
|
|
wire stxa_internal_d1, stxa_internal_d2 ;
|
897 |
|
|
wire ld_pcx_pkt_vld_e ;
|
898 |
|
|
wire ld_pcx_pkt_vld_m ;
|
899 |
|
|
wire ld_pcx_pkt_vld_g ;
|
900 |
|
|
wire ldst_dbl_m, ldst_dbl_g;
|
901 |
|
|
wire ldd_force_l2access_w2, ldd_force_l2access_w3;
|
902 |
|
|
|
903 |
|
|
//wire ld_stb_full_raw_w2 ;
|
904 |
|
|
wire ld_stb_full_raw_w3 ;
|
905 |
|
|
|
906 |
|
|
wire ldbyp0_vld_rst, ldbyp0_vld_en, ldbyp0_fpld ;
|
907 |
|
|
wire ldbyp1_vld_rst, ldbyp1_vld_en, ldbyp1_fpld ;
|
908 |
|
|
wire ldbyp2_vld_rst, ldbyp2_vld_en, ldbyp2_fpld ;
|
909 |
|
|
wire ldbyp3_vld_rst, ldbyp3_vld_en, ldbyp3_fpld ;
|
910 |
|
|
//wire ldbyp0_vld_en_d1,ldbyp1_vld_en_d1,ldbyp2_vld_en_d1,ldbyp3_vld_en_d1 ;
|
911 |
|
|
|
912 |
|
|
wire thread0_e,thread1_e,thread2_e,thread3_e;
|
913 |
|
|
wire thread0_d,thread1_d,thread2_d,thread3_d;
|
914 |
|
|
wire thread0_m,thread1_m,thread2_m,thread3_m;
|
915 |
|
|
wire thread0_g,thread1_g,thread2_g,thread3_g;
|
916 |
|
|
wire thread0_w2,thread1_w2,thread2_w2,thread3_w2;
|
917 |
|
|
wire thread0_w3,thread1_w3,thread2_w3,thread3_w3;
|
918 |
|
|
wire tlu_stxa_thread0_w2,tlu_stxa_thread1_w2 ;
|
919 |
|
|
wire tlu_stxa_thread2_w2,tlu_stxa_thread3_w2 ;
|
920 |
|
|
wire tlu_ldxa_thread0_w2,tlu_ldxa_thread1_w2 ;
|
921 |
|
|
wire tlu_ldxa_thread2_w2,tlu_ldxa_thread3_w2 ;
|
922 |
|
|
wire spu_ldxa_thread0_w2,spu_ldxa_thread1_w2 ;
|
923 |
|
|
wire spu_ldxa_thread2_w2,spu_ldxa_thread3_w2 ;
|
924 |
|
|
wire spu_stxa_thread0,spu_stxa_thread1 ;
|
925 |
|
|
wire spu_stxa_thread2,spu_stxa_thread3 ;
|
926 |
|
|
wire ifu_ldxa_thread0_w2,ifu_ldxa_thread1_w2 ;
|
927 |
|
|
wire ifu_ldxa_thread2_w2,ifu_ldxa_thread3_w2 ;
|
928 |
|
|
wire ifu_stxa_thread0_w2,ifu_stxa_thread1_w2 ;
|
929 |
|
|
wire ifu_stxa_thread2_w2,ifu_stxa_thread3_w2 ;
|
930 |
|
|
wire ldbyp0_vld, ldbyp1_vld, ldbyp2_vld, ldbyp3_vld ;
|
931 |
|
|
//wire ld_any_byp_data_vld ;
|
932 |
|
|
wire [3:0] asi_state_wr_thrd;
|
933 |
|
|
wire [3:0] pctxt_state_wr_thrd ;
|
934 |
|
|
wire [3:0] sctxt_state_wr_thrd ;
|
935 |
|
|
wire tlb_cam_hit_g ;
|
936 |
|
|
wire ld_inst_vld_unflushed ;
|
937 |
|
|
wire st_inst_vld_unflushed ;
|
938 |
|
|
|
939 |
|
|
wire [7:0] baddr_m ;
|
940 |
|
|
wire [15:0] byte_wr_enable ;
|
941 |
|
|
//wire [1:0] st_size ;
|
942 |
|
|
//wire l2fill_bendian_g ;
|
943 |
|
|
wire ldst_byte,ldst_hword,ldst_word,ldst_dword;
|
944 |
|
|
wire byte_m,hword_m,word_m,dword_m;
|
945 |
|
|
wire tlb_invert_endian_g ;
|
946 |
|
|
//wire [7:0] l2fill_bytes_msb_m, l2fill_bytes_msb_g ;
|
947 |
|
|
//wire byte_g, hword_g, word_g ;
|
948 |
|
|
|
949 |
|
|
wire signed_ldst_m ;
|
950 |
|
|
//wire unsigned_ldst_m ;
|
951 |
|
|
//wire sign_bit_g ;
|
952 |
|
|
//wire [7:0] align_bytes_msb ;
|
953 |
|
|
|
954 |
|
|
wire l2fill_vld_m, l2fill_vld_g ;
|
955 |
|
|
wire l2fill_fpld_e, l2fill_fpld_m, l2fill_fpld_g ;
|
956 |
|
|
wire pstate_cle_e, pstate_cle_m, pstate_cle_g ;
|
957 |
|
|
wire l1hit_lendian_g ;
|
958 |
|
|
wire l1hit_sign_extend_m, l1hit_sign_extend_g ;
|
959 |
|
|
wire demap_thread0, demap_thread1, demap_thread2, demap_thread3 ;
|
960 |
|
|
|
961 |
|
|
wire misc_byte_m,misc_hword_m,misc_word_m,misc_dword_m;
|
962 |
|
|
wire byp_word_g;
|
963 |
|
|
//wire [15:0] byp_baddr_g ;
|
964 |
|
|
//wire ld_stb_hit_g ;
|
965 |
|
|
wire atomic_ld_squash_e ;
|
966 |
|
|
wire atomic_m,atomic_g,atomic_w2, atomic_w3 ;
|
967 |
|
|
wire [2:0] ld_rq_type ;
|
968 |
|
|
wire ncache_pcx_rq_g ;
|
969 |
|
|
wire lmq_pkt_vld_g ;
|
970 |
|
|
wire tlb_lng_ltncy_asi_d,tlb_lng_ltncy_asi_e, tlb_lng_ltncy_asi_m,tlb_lng_ltncy_asi_g ;
|
971 |
|
|
wire recognized_asi_d,recognized_asi_e,recognized_asi_m,recognized_asi_g,recognized_asi_tmp ;
|
972 |
|
|
wire asi_internal_d, asi_internal_e ;
|
973 |
|
|
wire asi_internal_m, asi_internal_g ;
|
974 |
|
|
wire dcache_byp_asi_d, dcache_byp_asi_e ;
|
975 |
|
|
wire dcache_byp_asi_m, dcache_byp_asi_g ;
|
976 |
|
|
wire phy_use_ec_asi_d,phy_use_ec_asi_e,phy_use_ec_asi_m;
|
977 |
|
|
wire phy_byp_ec_asi_d,phy_byp_ec_asi_e,phy_byp_ec_asi_m;
|
978 |
|
|
wire lendian_asi_d, lendian_asi_e;
|
979 |
|
|
wire lendian_asi_m, lendian_asi_g;
|
980 |
|
|
wire intrpt_disp_asi_d,intrpt_disp_asi_e,intrpt_disp_asi_m,intrpt_disp_asi_g ;
|
981 |
|
|
wire nofault_asi_d, nofault_asi_e, nofault_asi_m ;
|
982 |
|
|
wire nucleus_asi_d, nucleus_asi_e ;
|
983 |
|
|
wire primary_asi_d, primary_asi_e ;
|
984 |
|
|
wire quad_asi_d,quad_asi_e,quad_asi_m,quad_asi_g;
|
985 |
|
|
wire binit_quad_asi_d,binit_quad_asi_e,binit_quad_asi_m,binit_quad_asi_g ;
|
986 |
|
|
wire secondary_asi_d, secondary_asi_e ;
|
987 |
|
|
wire tlb_byp_asi_d, tlb_byp_asi_e;
|
988 |
|
|
wire thread0_ctxt, thread1_ctxt ;
|
989 |
|
|
wire thread2_ctxt, thread3_ctxt ;
|
990 |
|
|
|
991 |
|
|
|
992 |
|
|
wire altspace_ldst_e, non_altspace_ldst_e ;
|
993 |
|
|
wire altspace_ldst_m, altspace_ldst_g ;
|
994 |
|
|
wire non_altspace_ldst_m, non_altspace_ldst_g ;
|
995 |
|
|
wire thread_pctxt, thread_sctxt, thread_nctxt, thread_actxt ;
|
996 |
|
|
wire ncache_asild_rq_g ;
|
997 |
|
|
//SC wire pstate_priv, pstate_priv_m ;
|
998 |
|
|
//SC wire priv_pg_usr_mode ;
|
999 |
|
|
//SC wire nonwr_pg_st_access ;
|
1000 |
|
|
//SC wire nfo_pg_nonnfo_asi ;
|
1001 |
|
|
//wire daccess_excptn ;
|
1002 |
|
|
wire mbar_inst_m,flsh_inst_m ;
|
1003 |
|
|
wire mbar_inst_g,flsh_inst_g ;
|
1004 |
|
|
wire bsync0_reset,bsync1_reset;
|
1005 |
|
|
wire bsync2_reset,bsync3_reset ;
|
1006 |
|
|
wire bsync0_en,bsync1_en ;
|
1007 |
|
|
wire bsync2_en,bsync3_en ;
|
1008 |
|
|
wire flush_inst0_g,mbar_inst0_g ;
|
1009 |
|
|
wire flush_inst1_g,mbar_inst1_g ;
|
1010 |
|
|
wire flush_inst2_g,mbar_inst2_g ;
|
1011 |
|
|
wire flush_inst3_g,mbar_inst3_g ;
|
1012 |
|
|
wire dfill_thread0,dfill_thread1;
|
1013 |
|
|
wire dfill_thread2,dfill_thread3;
|
1014 |
|
|
wire mbar_vld0, flsh_vld0 ;
|
1015 |
|
|
wire mbar_vld1, flsh_vld1 ;
|
1016 |
|
|
wire mbar_vld2, flsh_vld2 ;
|
1017 |
|
|
wire mbar_vld3, flsh_vld3 ;
|
1018 |
|
|
wire [1:0] dfq_tid_m,dfq_tid_g;
|
1019 |
|
|
|
1020 |
|
|
wire [1:0] ldbyp_tid_m ;
|
1021 |
|
|
wire stxa_stall_asi_g ;
|
1022 |
|
|
wire stxa_stall_wr_cmplt0, stxa_stall_wr_cmplt1 ;
|
1023 |
|
|
wire stxa_stall_wr_cmplt2, stxa_stall_wr_cmplt3 ;
|
1024 |
|
|
wire stxa_stall_wr_cmplt0_d1, stxa_stall_wr_cmplt1_d1 ;
|
1025 |
|
|
wire stxa_stall_wr_cmplt2_d1, stxa_stall_wr_cmplt3_d1 ;
|
1026 |
|
|
wire dtlb_done ;
|
1027 |
|
|
wire tag_rd_vld_m, tag_rd_vld_g ;
|
1028 |
|
|
wire data_rd_vld_m, data_rd_vld_g ;
|
1029 |
|
|
wire tlb_demap_vld ;
|
1030 |
|
|
wire dtlb_done_d1 ;
|
1031 |
|
|
wire dtlb_done_d2 ;
|
1032 |
|
|
|
1033 |
|
|
|
1034 |
|
|
wire tlu_lsu_asi_update_g ;
|
1035 |
|
|
wire [1:0] tlu_lsu_tid_g ;
|
1036 |
|
|
wire tsa_update_asi0,tsa_update_asi1;
|
1037 |
|
|
wire tsa_update_asi2,tsa_update_asi3;
|
1038 |
|
|
wire tlb_ld_inst0,tlb_ld_inst1,tlb_ld_inst2,tlb_ld_inst3 ;
|
1039 |
|
|
wire tlb_st_inst0,tlb_st_inst1,tlb_st_inst2,tlb_st_inst3 ;
|
1040 |
|
|
wire tlb_access_en0_e,tlb_access_en1_e,tlb_access_en2_e,tlb_access_en3_e ;
|
1041 |
|
|
wire tlb_access_en0_m,tlb_access_en1_m,tlb_access_en2_m,tlb_access_en3_m ;
|
1042 |
|
|
wire tlb_access_en0_tmp,tlb_access_en1_tmp,tlb_access_en2_tmp,tlb_access_en3_tmp ;
|
1043 |
|
|
wire tlb_access_en0_g,tlb_access_en1_g,tlb_access_en2_g,tlb_access_en3_g ;
|
1044 |
|
|
wire tlb_access_en0_unflushed,tlb_access_en1_unflushed,tlb_access_en2_unflushed,tlb_access_en3_unflushed ;
|
1045 |
|
|
wire tlb_access_rst0,tlb_access_rst1,tlb_access_rst2,tlb_access_rst3 ;
|
1046 |
|
|
wire tlb_access_sel_thrd0,tlb_access_sel_thrd1;
|
1047 |
|
|
wire tlb_access_sel_thrd2,tlb_access_sel_thrd3;
|
1048 |
|
|
wire tlb_access_blocked ;
|
1049 |
|
|
wire tlb_access_pending ;
|
1050 |
|
|
wire tlb_access_initiated ;
|
1051 |
|
|
//wire tlb_pending_access_rst ;
|
1052 |
|
|
|
1053 |
|
|
wire vw_wtchpt_cmp_en_m,vr_wtchpt_cmp_en_m ;
|
1054 |
|
|
|
1055 |
|
|
|
1056 |
|
|
//wire va_b12_3_match_m,va_b47_40_match_m ;
|
1057 |
|
|
//wire va_b12_3_match_g,va_b47_40_match_g ;
|
1058 |
|
|
//wire wtchpt_msk_match_m,wtchpt_msk_match_g ;
|
1059 |
|
|
|
1060 |
|
|
wire as_if_user_asi_d,as_if_user_asi_e,as_if_user_asi_m;
|
1061 |
|
|
//SC wire as_if_usr_priv_pg ;
|
1062 |
|
|
//SC wire priv_action,priv_action_m ;
|
1063 |
|
|
//SC wire stdf_maddr_not_align, lddf_maddr_not_align ;
|
1064 |
|
|
//wire [8:0] early_ttype_m,early_ttype_g ;
|
1065 |
|
|
//wire early_trap_vld_m, early_trap_vld_g ;
|
1066 |
|
|
//SC wire atm_access_w_nc, atm_access_unsup_asi ;
|
1067 |
|
|
wire atomic_asi_d,atomic_asi_e,atomic_asi_m ;
|
1068 |
|
|
//wire dflush_asi_d,dflush_asi_e,dflush_asi_m,dflush_asi_g;
|
1069 |
|
|
wire blk_asi_d,blk_asi_e,blk_asi_m, blk_asi_g ;
|
1070 |
|
|
|
1071 |
|
|
wire fpld_byp_data_vld ;
|
1072 |
|
|
//wire [7:0] dcache_rd_parity ;
|
1073 |
|
|
wire dcache_rd_parity_error ;
|
1074 |
|
|
//SC wire tte_data_parity_error ;
|
1075 |
|
|
|
1076 |
|
|
wire [3:0] dtag_parity_error;
|
1077 |
|
|
//wire dtag_mtag_parity_error ;
|
1078 |
|
|
//wire daccess_error ;
|
1079 |
|
|
//SC wire dmmu_miss_g ;
|
1080 |
|
|
wire [2:0] ctxt_sel_e ;
|
1081 |
|
|
wire dc_diagnstc_asi_d, dc_diagnstc_asi_e ;
|
1082 |
|
|
wire dc_diagnstc_asi_m, dc_diagnstc_asi_g ;
|
1083 |
|
|
wire dtagv_diagnstc_asi_d, dtagv_diagnstc_asi_e ;
|
1084 |
|
|
wire dtagv_diagnstc_asi_m, dtagv_diagnstc_asi_g ;
|
1085 |
|
|
//wire dc_diagnstc_wr_e,dtagv_diagnstc_wr_e ;
|
1086 |
|
|
//wire dside_diagnstc_wr_e ;
|
1087 |
|
|
wire dc_diagnstc_wr_en,dtagv_diagnstc_wr_en ;
|
1088 |
|
|
|
1089 |
|
|
wire dtagv_diagnstc_rd_g ;
|
1090 |
|
|
wire dc0_diagnstc_asi,dtagv0_diagnstc_asi;
|
1091 |
|
|
wire dc1_diagnstc_asi,dtagv1_diagnstc_asi;
|
1092 |
|
|
wire dc2_diagnstc_asi,dtagv2_diagnstc_asi;
|
1093 |
|
|
wire dc3_diagnstc_asi,dtagv3_diagnstc_asi;
|
1094 |
|
|
//wire [3:0] lngltncy_st_go ;
|
1095 |
|
|
wire [3:0] tlb_st_data_sel_m ;
|
1096 |
|
|
wire dc0_diagnstc_wr_en, dc1_diagnstc_wr_en, dc2_diagnstc_wr_en, dc3_diagnstc_wr_en ;
|
1097 |
|
|
wire dtagv0_diagnstc_wr_en, dtagv1_diagnstc_wr_en, dtagv2_diagnstc_wr_en, dtagv3_diagnstc_wr_en ;
|
1098 |
|
|
//wire merge2_sel_byte7, merge3_sel_byte7 ;
|
1099 |
|
|
//SC wire hw_align_addr,wd_align_addr,dw_align_addr;
|
1100 |
|
|
wire hw_size,wd_size,dw_size;
|
1101 |
|
|
//SC wire mem_addr_not_align ;
|
1102 |
|
|
|
1103 |
|
|
wire wr_only_asi_d,wr_only_asi_e,wr_only_asi_m ;
|
1104 |
|
|
wire rd_only_asi_d,rd_only_asi_e,rd_only_asi_m ;
|
1105 |
|
|
wire mmu_rd_only_asi_d,mmu_rd_only_asi_e,mmu_rd_only_asi_m ;
|
1106 |
|
|
wire unimp_asi_d,unimp_asi_e,unimp_asi_m;
|
1107 |
|
|
wire dmmu_asi58_d,dmmu_asi58_e,dmmu_asi58_m;
|
1108 |
|
|
wire immu_asi50_d,immu_asi50_e,immu_asi50_m;
|
1109 |
|
|
|
1110 |
|
|
wire ifu_asi_store ;
|
1111 |
|
|
wire nontlb_asi0, nontlb_asi1, nontlb_asi2, nontlb_asi3 ;
|
1112 |
|
|
//wire stxa_stall_reset ;
|
1113 |
|
|
wire ifu_nontlb0_asi,ifu_nontlb1_asi,ifu_nontlb2_asi,ifu_nontlb3_asi;
|
1114 |
|
|
wire ifu_nontlb_asi_d, ifu_nontlb_asi_e,ifu_nontlb_asi_m,ifu_nontlb_asi_g ;
|
1115 |
|
|
wire [2:0] lsu_asi_sel_fmx1 ;
|
1116 |
|
|
wire [2:0] lsu_asi_sel_fmx2;
|
1117 |
|
|
wire lsu_asi_rd_en, lsu_asi_rd_en_w2 ;
|
1118 |
|
|
//wire [12:0] pctxt_state ;
|
1119 |
|
|
//wire [12:0] sctxt_state ;
|
1120 |
|
|
|
1121 |
|
|
//wire [1:0] dcache_rand,dcache_rand_new ;
|
1122 |
|
|
wire dtlb_inv_all_e,dtlb_inv_all_m ;
|
1123 |
|
|
wire dtlb_wr_vld_d1,dtlb_tag_rd_d1,dtlb_data_rd_d1,dtlb_dmp_vld_d1,dtlb_inv_all_d1 ;
|
1124 |
|
|
wire ldst_in_pipe ;
|
1125 |
|
|
wire tlbop_init, tlbop_init_d1, tlbop_init_d2 ;
|
1126 |
|
|
wire tlbop_init_d3, tlbop_init_d4, tlbop_init_d5 ;
|
1127 |
|
|
wire [3:0] ldxa_illgl_va_cmplt,ldxa_illgl_va_cmplt_d1 ;
|
1128 |
|
|
|
1129 |
|
|
wire lsuctl_va_vld ;
|
1130 |
|
|
wire lsuctl_illgl_va ;
|
1131 |
|
|
wire sctxt_va_vld;
|
1132 |
|
|
//wire scxt_ldxa_illgl_va ;
|
1133 |
|
|
wire pctxt_va_vld;
|
1134 |
|
|
|
1135 |
|
|
wire pscxt_ldxa_illgl_va ;
|
1136 |
|
|
wire lsu_asi_illgl_va ;
|
1137 |
|
|
wire [3:0] lsu_asi_illgl_va_cmplt,lsu_asi_illgl_va_cmplt_w2 ;
|
1138 |
|
|
wire bistctl_va_vld,mrgnctl_va_vld,ldiagctl_va_vld ;
|
1139 |
|
|
wire bistctl_state_en,mrgnctl_state_en,ldiagctl_state_en ;
|
1140 |
|
|
wire mrgnctl_illgl_va ;
|
1141 |
|
|
wire asi42_illgl_va ;
|
1142 |
|
|
|
1143 |
|
|
wire [3:0] tap_thread ;
|
1144 |
|
|
wire mrgn_tap_wr_en ;
|
1145 |
|
|
wire bist_tap_wr_en ;
|
1146 |
|
|
|
1147 |
|
|
wire [3:0] dfture_tap_rd_d1;
|
1148 |
|
|
wire [3:0] dfture_tap_wr_en;
|
1149 |
|
|
|
1150 |
|
|
//wire dfture_tap_rd_sel ;
|
1151 |
|
|
|
1152 |
|
|
wire misc_asi_rd_en ;
|
1153 |
|
|
|
1154 |
|
|
wire [3:0] lsuctl_ctlbits_wr_en ;
|
1155 |
|
|
wire bistctl_wr_en;
|
1156 |
|
|
wire mrgnctl_wr_en;
|
1157 |
|
|
//wire ldiagctl_rd_en,ldiagctl_wr_en;
|
1158 |
|
|
wire casa_m, casa_g ;
|
1159 |
|
|
wire tte_data_perror_unc ;
|
1160 |
|
|
wire asi_tte_data_perror,asi_tte_tag_perror ;
|
1161 |
|
|
|
1162 |
|
|
wire [1:0] dfill_tid_m,dfill_tid_g ;
|
1163 |
|
|
wire dtag_error_m,dcache_error_m;
|
1164 |
|
|
wire dtag_error_g,dcache_error_g;
|
1165 |
|
|
wire dtag_error_w2,dcache_error_w2;
|
1166 |
|
|
wire l2_unc_error_e,l2_corr_error_e;
|
1167 |
|
|
wire l2_unc_error_m,l2_corr_error_m;
|
1168 |
|
|
wire l2_unc_error_g,l2_corr_error_g;
|
1169 |
|
|
wire l2_unc_error_w2,l2_corr_error_w2;
|
1170 |
|
|
wire unc_err_trap_e,unc_err_trap_m,unc_err_trap_g ;
|
1171 |
|
|
//wire corr_err_trap_e, corr_err_trap_m, corr_err_trap_g ;
|
1172 |
|
|
wire dtag_perror_g ;
|
1173 |
|
|
|
1174 |
|
|
|
1175 |
|
|
wire ifill_tlb_asi_d,dfill_tlb_asi_d,rd_only_ltlb_asi_d,wr_only_ltlb_asi_d ;
|
1176 |
|
|
wire ifill_tlb_asi_e,dfill_tlb_asi_e,rd_only_ltlb_asi_e,wr_only_ltlb_asi_e ;
|
1177 |
|
|
//SC wire tlb_daccess_excptn_e,tlb_daccess_error_e ;
|
1178 |
|
|
//SC wire tlb_daccess_excptn_m,tlb_daccess_error_m ;
|
1179 |
|
|
//SC wire tlb_daccess_excptn_g,tlb_daccess_error_g ;
|
1180 |
|
|
wire thread_tl_zero ;
|
1181 |
|
|
wire pid_va_vld, pid_state_en ;
|
1182 |
|
|
wire [3:0] pid_state_wr_en ;
|
1183 |
|
|
|
1184 |
|
|
//wire [3:0] pid_state_rd_en ;
|
1185 |
|
|
//wire [2:0] pid_state ;
|
1186 |
|
|
wire [3:0] intld_byp_cmplt ;
|
1187 |
|
|
|
1188 |
|
|
//wire hpv_priv,hpstate_en ;
|
1189 |
|
|
wire hpv_priv_m,hpstate_en_m ;
|
1190 |
|
|
wire hpv_priv_e,hpstate_en_e ;
|
1191 |
|
|
wire blkst_m, blkst_g ;
|
1192 |
|
|
//wire dc_direct_map ;
|
1193 |
|
|
wire spubyp_trap_active_e,spubyp_trap_active_m, spubyp_trap_active_g ;
|
1194 |
|
|
wire [6:0] spubyp_ttype ;
|
1195 |
|
|
wire spu_trap ;
|
1196 |
|
|
wire spu_trap0, spu_trap1, spu_trap2, spu_trap3 ;
|
1197 |
|
|
wire [6:0] spu_ttype ;
|
1198 |
|
|
wire spubyp0_trap,spubyp1_trap,spubyp2_trap,spubyp3_trap;
|
1199 |
|
|
wire [6:0] spubyp0_ttype,spubyp1_ttype,spubyp2_ttype,spubyp3_ttype;
|
1200 |
|
|
wire bendian_g ;
|
1201 |
|
|
//wire va_wtchpt_rd_en, pa_wtchpt_rd_en;
|
1202 |
|
|
//wire lsu_bendian_access_g;
|
1203 |
|
|
wire lsu_tlb_tag_rd_vld_g ;
|
1204 |
|
|
wire lsu_dtlb_invalid_all_m ;
|
1205 |
|
|
|
1206 |
|
|
wire [3:0] dva_vld_g;
|
1207 |
|
|
wire lsu_diagnstc_asi_rd_en;
|
1208 |
|
|
wire [3:0] ld_thrd_byp_sel_g ;
|
1209 |
|
|
wire [3:0] lmq_byp_data_sel0 ; // ldxa vs stb bypass data sel.
|
1210 |
|
|
wire [3:0] lmq_byp_data_sel1 ; // ldxa vs stb bypass data sel.
|
1211 |
|
|
wire [3:0] lmq_byp_data_sel2 ; // ldxa vs stb bypass data sel.
|
1212 |
|
|
wire [3:0] lmq_byp_data_sel3 ; // ldxa vs stb bypass data sel.
|
1213 |
|
|
wire [2:0] lmq_byp_ldxa_sel0 ; // ldxa data sel - thread0
|
1214 |
|
|
wire [2:0] lmq_byp_ldxa_sel1 ; // ldxa data sel - thread1
|
1215 |
|
|
wire [2:0] lmq_byp_ldxa_sel2 ; // ldxa data sel - thread2
|
1216 |
|
|
wire [2:0] lmq_byp_ldxa_sel3 ; // ldxa data sel - thread3
|
1217 |
|
|
wire endian_mispred_g ;
|
1218 |
|
|
|
1219 |
|
|
wire ld_inst_vld_w2, ld_inst_vld_w3;
|
1220 |
|
|
|
1221 |
|
|
wire [3:0] lmq_byp_data_raw_sel_d1;
|
1222 |
|
|
wire [3:0] lmq_byp_data_raw_sel_d2;
|
1223 |
|
|
|
1224 |
|
|
wire asi_st_vld_g ;
|
1225 |
|
|
wire ignore_fill;
|
1226 |
|
|
|
1227 |
|
|
wire [3:0] pend_atm_ld_ue ;
|
1228 |
|
|
|
1229 |
|
|
wire [2:0] lsu_byp_misc_addr_m ; // lower 3bits of addr for ldxa/raw etc
|
1230 |
|
|
wire [1:0] lsu_byp_misc_sz_m ; // size for ldxa/raw etc
|
1231 |
|
|
|
1232 |
|
|
//==========================================================
|
1233 |
|
|
//RESET, CLK
|
1234 |
|
|
//==========================================================
|
1235 |
|
|
wire reset;
|
1236 |
|
|
|
1237 |
|
|
// assign reset = ~rst_l;
|
1238 |
|
|
wire dbb_reset_l;
|
1239 |
|
|
wire clk;
|
1240 |
|
|
|
1241 |
|
|
dffrl_async rstff(.din (grst_l),
|
1242 |
|
|
.q (dbb_reset_l),
|
1243 |
|
|
.clk (clk), .se(se), .si(), .so(),
|
1244 |
|
|
.rst_l (arst_l));
|
1245 |
|
|
|
1246 |
|
|
assign reset = ~dbb_reset_l;
|
1247 |
|
|
assign dctl_rst_l = dbb_reset_l;
|
1248 |
|
|
assign clk = rclk;
|
1249 |
|
|
|
1250 |
|
|
wire lsu_bist_wvld_e ; // bist writes to cache
|
1251 |
|
|
wire lsu_bist_rvld_e ; // bist reads dcache
|
1252 |
|
|
|
1253 |
|
|
dff_s #(2) mbist_stge (
|
1254 |
|
|
.din ({mbist_dcache_write, mbist_dcache_read}),
|
1255 |
|
|
.q ({lsu_bist_wvld_e, lsu_bist_rvld_e }),
|
1256 |
|
|
.clk (clk),
|
1257 |
|
|
.se (se), .si (), .so ()
|
1258 |
|
|
);
|
1259 |
|
|
|
1260 |
|
|
//===========================================================
|
1261 |
|
|
//from lsu_excpctl
|
1262 |
|
|
//wire lsu_flush_pipe_w ; // flush - local to lsu
|
1263 |
|
|
|
1264 |
|
|
// assign lsu_flush_pipe_w = dctl_flush_pipe_w;
|
1265 |
|
|
|
1266 |
|
|
//===========================================================
|
1267 |
|
|
//
|
1268 |
|
|
assign lsu_ldst_inst_vld_e = ld_inst_vld_e | st_inst_vld_e;
|
1269 |
|
|
|
1270 |
|
|
//wire lsu_l2fill_bendian_g;
|
1271 |
|
|
|
1272 |
|
|
wire memref_e;
|
1273 |
|
|
|
1274 |
|
|
dff_s #(1) stge_ad_e (
|
1275 |
|
|
.din (ifu_lsu_memref_d),
|
1276 |
|
|
.q (memref_e),
|
1277 |
|
|
.clk (clk),
|
1278 |
|
|
.se (se), .si (), .so ()
|
1279 |
|
|
);
|
1280 |
|
|
|
1281 |
|
|
//=================================================================================================
|
1282 |
|
|
// SHADOW SCAN
|
1283 |
|
|
//=================================================================================================
|
1284 |
|
|
|
1285 |
|
|
wire sscan_data_13, sscan_data_14 ;
|
1286 |
|
|
// stb status - this monitors the stb state
|
1287 |
|
|
assign sscan_data_13 =
|
1288 |
|
|
ctu_sscan_tid[0] & lsu_stb_empty[0] |
|
1289 |
|
|
ctu_sscan_tid[1] & lsu_stb_empty[1] |
|
1290 |
|
|
ctu_sscan_tid[2] & lsu_stb_empty[2] |
|
1291 |
|
|
ctu_sscan_tid[3] & lsu_stb_empty[3] ;
|
1292 |
|
|
|
1293 |
|
|
|
1294 |
|
|
// Monitors outstanding long-latency asi transactions - hangs thread. Doesn't cover all asi.
|
1295 |
|
|
assign sscan_data_14 =
|
1296 |
|
|
ctu_sscan_tid[0] & (tlb_ld_inst0 | tlb_st_inst0) |
|
1297 |
|
|
ctu_sscan_tid[1] & (tlb_ld_inst1 | tlb_st_inst1) |
|
1298 |
|
|
ctu_sscan_tid[2] & (tlb_ld_inst2 | tlb_st_inst2) |
|
1299 |
|
|
ctu_sscan_tid[3] & (tlb_ld_inst3 | tlb_st_inst3) ;
|
1300 |
|
|
|
1301 |
|
|
|
1302 |
|
|
dff_s #(2) stg_d1 (
|
1303 |
|
|
.din ({sscan_data_14,sscan_data_13}),
|
1304 |
|
|
.q (lsu_sscan_data[14:13]),
|
1305 |
|
|
.clk (clk),
|
1306 |
|
|
.se (se), .si (), .so ()
|
1307 |
|
|
);
|
1308 |
|
|
|
1309 |
|
|
//=========================================================================================
|
1310 |
|
|
// INST_VLD_W GENERATION
|
1311 |
|
|
//=========================================================================================
|
1312 |
|
|
|
1313 |
|
|
wire flush_w_inst_vld_m ;
|
1314 |
|
|
wire lsu_inst_vld_w ;
|
1315 |
|
|
assign flush_w_inst_vld_m =
|
1316 |
|
|
ifu_tlu_inst_vld_m &
|
1317 |
|
|
~(dctl_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
|
1318 |
|
|
|
1319 |
|
|
dff_s stgw_ivld (
|
1320 |
|
|
.din (flush_w_inst_vld_m),
|
1321 |
|
|
.q (lsu_inst_vld_w),
|
1322 |
|
|
.clk (clk),
|
1323 |
|
|
.se (se), .si (), .so ()
|
1324 |
|
|
);
|
1325 |
|
|
|
1326 |
|
|
|
1327 |
|
|
// Specifically for qctl2. Does not include flush-pipe, but does include ifu's flush.
|
1328 |
|
|
wire ld_vld ;
|
1329 |
|
|
|
1330 |
|
|
wire ifu_lsu_flush_w;
|
1331 |
|
|
|
1332 |
|
|
wire ifu_tlu_flush_fd_w_q, ifu_tlu_flush_fd2_w_q, ifu_tlu_flush_fd3_w_q;
|
1333 |
|
|
|
1334 |
|
|
dff_s #(4) ifu_tlu_flush_stgw (
|
1335 |
|
|
.din ({ifu_tlu_flush_m,ifu_tlu_flush_m, ifu_tlu_flush_m, ifu_tlu_flush_m} ),
|
1336 |
|
|
.q ({ifu_lsu_flush_w,ifu_tlu_flush_fd_w_q,ifu_tlu_flush_fd2_w_q,ifu_tlu_flush_fd3_w_q}),
|
1337 |
|
|
.clk (clk),
|
1338 |
|
|
.se (se), .si (), .so ()
|
1339 |
|
|
);
|
1340 |
|
|
|
1341 |
|
|
bw_u1_buf_30x UZfix_ifu_tlu_flush_fd_w ( .a(ifu_tlu_flush_fd_w_q), .z(ifu_tlu_flush_fd_w) );
|
1342 |
|
|
bw_u1_buf_30x UZfix_ifu_tlu_flush_fd2_w ( .a(ifu_tlu_flush_fd2_w_q), .z(ifu_tlu_flush_fd2_w) );
|
1343 |
|
|
bw_u1_buf_30x UZfix_ifu_tlu_flush_fd3_w ( .a(ifu_tlu_flush_fd3_w_q), .z(ifu_tlu_flush_fd3_w) );
|
1344 |
|
|
|
1345 |
|
|
assign ld_vld = ld_inst_vld_unflushed & lsu_inst_vld_w & ~ifu_lsu_flush_w ;
|
1346 |
|
|
wire ld_vld_w_flush ;
|
1347 |
|
|
assign ld_vld_w_flush = ld_vld & ~dctl_flush_pipe_w ;
|
1348 |
|
|
assign lsu_ld_inst_vld_g[0] = ld_vld_w_flush & thread0_g ;
|
1349 |
|
|
assign lsu_ld_inst_vld_g[1] = ld_vld_w_flush & thread1_g ;
|
1350 |
|
|
assign lsu_ld_inst_vld_g[2] = ld_vld_w_flush & thread2_g ;
|
1351 |
|
|
assign lsu_ld_inst_vld_g[3] = ld_vld_w_flush & thread3_g ;
|
1352 |
|
|
|
1353 |
|
|
//=========================================================================================
|
1354 |
|
|
// TLB Control
|
1355 |
|
|
//=========================================================================================
|
1356 |
|
|
|
1357 |
|
|
wire alt_space_e ;
|
1358 |
|
|
dff_s #(1) aspace_e (
|
1359 |
|
|
.din (ifu_lsu_alt_space_d),
|
1360 |
|
|
.q (alt_space_e),
|
1361 |
|
|
.clk (clk),
|
1362 |
|
|
.se (se), .si (), .so ()
|
1363 |
|
|
);
|
1364 |
|
|
|
1365 |
|
|
//Atomics require translation.
|
1366 |
|
|
assign tlb_ldst_cam_vld =
|
1367 |
|
|
memref_e &
|
1368 |
|
|
~dtlb_bypass_e & ~(asi_internal_e & alt_space_e) ;
|
1369 |
|
|
|
1370 |
|
|
// in hyper-lite mode, assumption is that real translation is not supported -
|
1371 |
|
|
// a miss in tlb with real-translation enabled would result in real-address
|
1372 |
|
|
// translation miss. This would be purely accidental on software's part.
|
1373 |
|
|
//wire dtlb_real_byp_e ;
|
1374 |
|
|
//assign dtlb_real_byp_e = hpstate_en_e & ~hpv_priv_e ;
|
1375 |
|
|
// In hyper-lite mode, no concept of real xslation.
|
1376 |
|
|
assign lsu_dtlb_cam_real_e =
|
1377 |
|
|
// lsu-ctl based RA->PA
|
1378 |
|
|
( lsuctl_dtlb_byp_e & ~hpv_priv_e & hpstate_en_e) |
|
1379 |
|
|
// means RA->PA if used by hypervisor.
|
1380 |
|
|
( tlb_byp_asi_e & hpstate_en_e & altspace_ldst_e) ;
|
1381 |
|
|
//( tlb_byp_asi_e & dtlb_real_byp_e & altspace_ldst_e) ;
|
1382 |
|
|
|
1383 |
|
|
assign demap_thread0 = ~tlb_demap_thrid[1] & ~tlb_demap_thrid[0] ;
|
1384 |
|
|
assign demap_thread1 = ~tlb_demap_thrid[1] & tlb_demap_thrid[0] ;
|
1385 |
|
|
assign demap_thread2 = tlb_demap_thrid[1] & ~tlb_demap_thrid[0] ;
|
1386 |
|
|
assign demap_thread3 = tlb_demap_thrid[1] & tlb_demap_thrid[0] ;
|
1387 |
|
|
|
1388 |
|
|
// demap access and regular ldst access to tlb are assumed to
|
1389 |
|
|
// be mutex.
|
1390 |
|
|
assign thread0_ctxt = ( demap_thread0 & tlb_demap_vld) |
|
1391 |
|
|
(~tlb_demap_vld & thread0_e) ;
|
1392 |
|
|
//(thread0_e & memref_e) ;
|
1393 |
|
|
assign thread1_ctxt = ( demap_thread1 & tlb_demap_vld) |
|
1394 |
|
|
(~tlb_demap_vld & thread1_e) ;
|
1395 |
|
|
//(thread1_e & memref_e) ;
|
1396 |
|
|
assign thread2_ctxt = ( demap_thread2 & tlb_demap_vld) |
|
1397 |
|
|
(~tlb_demap_vld & thread2_e) ;
|
1398 |
|
|
//(thread2_e & memref_e) ;
|
1399 |
|
|
assign thread3_ctxt = ( demap_thread3 & tlb_demap_vld) |
|
1400 |
|
|
(~tlb_demap_vld & thread3_e) ;
|
1401 |
|
|
//(thread3_e & memref_e) ;
|
1402 |
|
|
|
1403 |
|
|
assign altspace_ldst_e = memref_e & alt_space_e ;
|
1404 |
|
|
assign non_altspace_ldst_e = memref_e & ~alt_space_e ;
|
1405 |
|
|
|
1406 |
|
|
dff_s #(2) aspace_stgm (
|
1407 |
|
|
.din ({altspace_ldst_e,non_altspace_ldst_e}),
|
1408 |
|
|
.q ({altspace_ldst_m,non_altspace_ldst_m}),
|
1409 |
|
|
.clk (clk),
|
1410 |
|
|
.se (se), .si (), .so ()
|
1411 |
|
|
);
|
1412 |
|
|
|
1413 |
|
|
dff_s #(2) aspace_stgg (
|
1414 |
|
|
.din ({altspace_ldst_m,non_altspace_ldst_m}),
|
1415 |
|
|
.q ({altspace_ldst_g,non_altspace_ldst_g}),
|
1416 |
|
|
.clk (clk),
|
1417 |
|
|
.se (se), .si (), .so ()
|
1418 |
|
|
);
|
1419 |
|
|
|
1420 |
|
|
wire [3:0] tl_zero_d1 ;
|
1421 |
|
|
dff_s #(4) tlz_stgd1 (
|
1422 |
|
|
.din (tlu_lsu_tl_zero[3:0]),
|
1423 |
|
|
.q (tl_zero_d1[3:0]),
|
1424 |
|
|
.clk (clk),
|
1425 |
|
|
.se (se), .si (), .so ()
|
1426 |
|
|
);
|
1427 |
|
|
|
1428 |
|
|
mux4ds #(1) trap_level_zero_mux (
|
1429 |
|
|
.in0 (tl_zero_d1[0]),
|
1430 |
|
|
.in1 (tl_zero_d1[1]),
|
1431 |
|
|
.in2 (tl_zero_d1[2]),
|
1432 |
|
|
.in3 (tl_zero_d1[3]),
|
1433 |
|
|
.sel0 (thread0_e),
|
1434 |
|
|
.sel1 (thread1_e),
|
1435 |
|
|
.sel2 (thread2_e),
|
1436 |
|
|
.sel3 (thread3_e),
|
1437 |
|
|
.dout (thread_tl_zero)
|
1438 |
|
|
);
|
1439 |
|
|
|
1440 |
|
|
wire thread_tl_zero_m ;
|
1441 |
|
|
dff_s #(1) ttlz_stgm (
|
1442 |
|
|
.din (thread_tl_zero),
|
1443 |
|
|
.q (thread_tl_zero_m),
|
1444 |
|
|
.clk (clk),
|
1445 |
|
|
.se (se), .si (), .so ()
|
1446 |
|
|
);
|
1447 |
|
|
|
1448 |
|
|
|
1449 |
|
|
assign lsu_nonalt_nucl_access_m = non_altspace_ldst_m & ~thread_tl_zero_m ;
|
1450 |
|
|
|
1451 |
|
|
// Note : autodemap will need to be or'ed into tlb_demap_vld !!!
|
1452 |
|
|
// use of tlu_lsu_tl_zero needs to be threaded.
|
1453 |
|
|
assign thread_pctxt = ( tlb_demap_pctxt & tlb_demap_vld) | // demap
|
1454 |
|
|
( non_altspace_ldst_e & thread_tl_zero) | // ldst. non-alt- space
|
1455 |
|
|
( altspace_ldst_e & primary_asi_e) | // ldst. alt_space
|
1456 |
|
|
(~(memref_e | tlb_demap_vld)) ; // default for pipe
|
1457 |
|
|
//(~(ld_inst_vld_e | st_inst_vld_e | tlb_demap_vld)) ; // default for pipe
|
1458 |
|
|
assign thread_sctxt = ( tlb_demap_sctxt & tlb_demap_vld) | // demap
|
1459 |
|
|
( altspace_ldst_e & secondary_asi_e) ; // ldst. alt_space
|
1460 |
|
|
assign thread_nctxt = ( tlb_demap_nctxt & tlb_demap_vld) | // demap
|
1461 |
|
|
( non_altspace_ldst_e & ~thread_tl_zero) | // ldst. non-alt- space
|
1462 |
|
|
( altspace_ldst_e & nucleus_asi_e) ; // ldst. alt_space
|
1463 |
|
|
assign thread_actxt = tlb_demap_actxt & tlb_demap_vld ;
|
1464 |
|
|
|
1465 |
|
|
//tmp
|
1466 |
|
|
wire thread_default;
|
1467 |
|
|
assign thread_default = ~(thread_pctxt | thread_sctxt | thread_actxt);
|
1468 |
|
|
|
1469 |
|
|
wire [3:0] pstate_am ;
|
1470 |
|
|
dff_s #(4) psam_stgd1 (
|
1471 |
|
|
.din (tlu_lsu_pstate_am[3:0]),
|
1472 |
|
|
.q (pstate_am[3:0]),
|
1473 |
|
|
.clk (clk),
|
1474 |
|
|
.se (se), .si (), .so ()
|
1475 |
|
|
);
|
1476 |
|
|
|
1477 |
|
|
//assign lsu_dtlb_addr_mask_l_e =
|
1478 |
|
|
// thread0_e ? ~pstate_am[0] :
|
1479 |
|
|
// thread1_e ? ~pstate_am[1] :
|
1480 |
|
|
// thread2_e ? ~pstate_am[2] :
|
1481 |
|
|
// ~pstate_am[3] ;
|
1482 |
|
|
|
1483 |
|
|
mux4ds #(1) pstate_am_mux (
|
1484 |
|
|
.in0 (~pstate_am[0]),
|
1485 |
|
|
.in1 (~pstate_am[1]),
|
1486 |
|
|
.in2 (~pstate_am[2]),
|
1487 |
|
|
.in3 (~pstate_am[3]),
|
1488 |
|
|
.sel0 (thread0_e),
|
1489 |
|
|
.sel1 (thread1_e),
|
1490 |
|
|
.sel2 (thread2_e),
|
1491 |
|
|
.sel3 (thread3_e),
|
1492 |
|
|
.dout (lsu_dtlb_addr_mask_l_e)
|
1493 |
|
|
);
|
1494 |
|
|
|
1495 |
|
|
//=========================================================================================
|
1496 |
|
|
// TLB RD/WR/DMP HANDLING
|
1497 |
|
|
//=========================================================================================
|
1498 |
|
|
|
1499 |
|
|
// To speed up the tlb miss handler, wr_vld will now be generated based on
|
1500 |
|
|
// admp occurence. lsu_dtlb_wr_vld_g is to be ignored. The following paths
|
1501 |
|
|
// can be improved
|
1502 |
|
|
// admp->write initiation (+2)
|
1503 |
|
|
// write->completion initiation (+3)
|
1504 |
|
|
|
1505 |
|
|
wire admp_write ;
|
1506 |
|
|
assign admp_write = lsu_dtlb_dmp_vld_e & tlb_demap_actxt ;
|
1507 |
|
|
wire admp_rst ;
|
1508 |
|
|
assign admp_rst = reset | lsu_dtlb_wr_vld_e ;
|
1509 |
|
|
|
1510 |
|
|
wire local_dtlb_wr_vld_g ;
|
1511 |
|
|
dffre_s #(1) twr_stgd1 (
|
1512 |
|
|
.din (admp_write),
|
1513 |
|
|
.q (local_dtlb_wr_vld_g),
|
1514 |
|
|
.clk (clk),
|
1515 |
|
|
.en (admp_write), .rst (admp_rst),
|
1516 |
|
|
.se (se), .si (), .so ()
|
1517 |
|
|
);
|
1518 |
|
|
|
1519 |
|
|
|
1520 |
|
|
wire dtlb_wr_init_d1,dtlb_wr_init_d2,dtlb_wr_init_d3 ;
|
1521 |
|
|
// Handshake between tlu and lsu needs to be fine-tuned !!!
|
1522 |
|
|
assign lsu_dtlb_wr_vld_e = local_dtlb_wr_vld_g & ~(memref_e | dtlb_wr_init_d1 | dtlb_wr_init_d2) ;
|
1523 |
|
|
//assign lsu_dtlb_wr_vld_e = tlu_dtlb_wr_vld_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
|
1524 |
|
|
assign lsu_dtlb_tag_rd_e = tlu_dtlb_tag_rd_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
|
1525 |
|
|
assign lsu_dtlb_data_rd_e = tlu_dtlb_data_rd_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
|
1526 |
|
|
assign lsu_dtlb_dmp_vld_e = tlu_dtlb_dmp_vld_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
|
1527 |
|
|
|
1528 |
|
|
wire lsu_dtlb_dmp_all_e_tmp;
|
1529 |
|
|
|
1530 |
|
|
assign lsu_dtlb_dmp_all_e_tmp = tlu_dtlb_dmp_all_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
|
1531 |
|
|
bw_u1_buf_5x UZsize_lsu_dtlb_dmp_all_e (.a(lsu_dtlb_dmp_all_e_tmp), .z(lsu_dtlb_dmp_all_e));
|
1532 |
|
|
|
1533 |
|
|
assign lsu_dtlb_rwindex_vld_e = tlu_dtlb_rw_index_vld_g & ~(memref_e | dtlb_wr_init_d1 | dtlb_wr_init_d2) ;
|
1534 |
|
|
//assign lsu_dtlb_rwindex_vld_e = tlu_dtlb_rw_index_vld_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
|
1535 |
|
|
// Can remove reset once invalidate asi in place !!!
|
1536 |
|
|
// assign lsu_dtlb_invalid_all_w2 = reset | tlu_dtlb_invalidate_all_g ;
|
1537 |
|
|
|
1538 |
|
|
assign tlb_demap_vld = lsu_dtlb_dmp_vld_e ;
|
1539 |
|
|
|
1540 |
|
|
// Switchout for threads. Force threads to swo if tlb operation does not occur for over 5 cycles.
|
1541 |
|
|
|
1542 |
|
|
dff_s #(5) tlbop_stgd1 (
|
1543 |
|
|
//.din ({tlu_dtlb_wr_vld_g,tlu_dtlb_tag_rd_g,tlu_dtlb_data_rd_g,tlu_dtlb_dmp_vld_g,
|
1544 |
|
|
.din ({local_dtlb_wr_vld_g,tlu_dtlb_tag_rd_g,tlu_dtlb_data_rd_g,tlu_dtlb_dmp_vld_g,
|
1545 |
|
|
tlu_dtlb_invalidate_all_g}),
|
1546 |
|
|
.q ({dtlb_wr_vld_d1,dtlb_tag_rd_d1,dtlb_data_rd_d1,dtlb_dmp_vld_d1,
|
1547 |
|
|
dtlb_inv_all_d1}),
|
1548 |
|
|
.clk (clk),
|
1549 |
|
|
.se (se), .si (), .so ()
|
1550 |
|
|
);
|
1551 |
|
|
|
1552 |
|
|
// Detect event.
|
1553 |
|
|
//bug6193 / ECO bug6511
|
1554 |
|
|
assign ldst_in_pipe = memref_e ;
|
1555 |
|
|
assign tlbop_init =
|
1556 |
|
|
((~dtlb_wr_vld_d1 & local_dtlb_wr_vld_g) |
|
1557 |
|
|
(~dtlb_tag_rd_d1 & tlu_dtlb_tag_rd_g) |
|
1558 |
|
|
(~dtlb_data_rd_d1 & tlu_dtlb_data_rd_g) |
|
1559 |
|
|
(~dtlb_inv_all_d1 & tlu_dtlb_invalidate_all_g) |
|
1560 |
|
|
(~dtlb_dmp_vld_d1 & tlu_dtlb_dmp_vld_g)) & ldst_in_pipe ;
|
1561 |
|
|
|
1562 |
|
|
dff_s #(1) tlbinit_stgd1 ( .din (tlbop_init), .q (tlbop_init_d1),
|
1563 |
|
|
.clk (clk), .se (se), .si (), .so ());
|
1564 |
|
|
dff_s #(1) tlbinit_stgd2 ( .din (tlbop_init_d1 & ldst_in_pipe), .q (tlbop_init_d2),
|
1565 |
|
|
.clk (clk), .se (se), .si (), .so ());
|
1566 |
|
|
dff_s #(1) tlbinit_stgd3 ( .din (tlbop_init_d2 & ldst_in_pipe), .q (tlbop_init_d3),
|
1567 |
|
|
.clk (clk), .se (se), .si (), .so ());
|
1568 |
|
|
dff_s #(1) tlbinit_stgd4 ( .din (tlbop_init_d3 & ldst_in_pipe), .q (tlbop_init_d4),
|
1569 |
|
|
.clk (clk), .se (se), .si (), .so ());
|
1570 |
|
|
dff_s #(1) tlbinit_stgd5 ( .din (tlbop_init_d4 & ldst_in_pipe), .q (tlbop_init_d5),
|
1571 |
|
|
.clk (clk), .se (se), .si (), .so ());
|
1572 |
|
|
|
1573 |
|
|
|
1574 |
|
|
assign lsu_tlbop_force_swo = tlbop_init_d5 & ldst_in_pipe ;
|
1575 |
|
|
|
1576 |
|
|
//assign dtlb_done = lsu_dtlb_wr_vld_e | lsu_dtlb_tag_rd_e |
|
1577 |
|
|
assign dtlb_done = lsu_dtlb_tag_rd_e | lsu_dtlb_data_rd_e |
|
1578 |
|
|
lsu_dtlb_dmp_vld_e | dtlb_inv_all_e ;
|
1579 |
|
|
|
1580 |
|
|
assign dtlb_inv_all_e = tlu_dtlb_invalidate_all_g & ~(memref_e | dtlb_done_d1 | dtlb_done_d2) ;
|
1581 |
|
|
|
1582 |
|
|
dff_s #(3) dn_stgd1 (
|
1583 |
|
|
.din ({dtlb_done,lsu_dtlb_tag_rd_e,lsu_dtlb_data_rd_e}),
|
1584 |
|
|
.q ({dtlb_done_d1,tag_rd_vld_m,data_rd_vld_m}),
|
1585 |
|
|
.clk (clk),
|
1586 |
|
|
.se (se), .si (), .so ()
|
1587 |
|
|
);
|
1588 |
|
|
|
1589 |
|
|
wire dtlb_inv_all_din ;
|
1590 |
|
|
assign dtlb_inv_all_din = sehold ? dtlb_inv_all_m : dtlb_inv_all_e ;
|
1591 |
|
|
|
1592 |
|
|
dff_s #(1) dinv_stgd1 (
|
1593 |
|
|
.din (dtlb_inv_all_din),
|
1594 |
|
|
.q (dtlb_inv_all_m),
|
1595 |
|
|
.clk (clk),
|
1596 |
|
|
.se (se), .si (), .so ()
|
1597 |
|
|
);
|
1598 |
|
|
|
1599 |
|
|
assign lsu_dtlb_invalid_all_m = dtlb_inv_all_m ;
|
1600 |
|
|
// added by sureshT
|
1601 |
|
|
assign lsu_dtlb_invalid_all_l_m = ~lsu_dtlb_invalid_all_m;
|
1602 |
|
|
|
1603 |
|
|
dff_s #(3) dn_stgd2 (
|
1604 |
|
|
.din ({dtlb_done_d1,tag_rd_vld_m,data_rd_vld_m}),
|
1605 |
|
|
.q ({dtlb_done_d2,tag_rd_vld_g,data_rd_vld_g}),
|
1606 |
|
|
.clk (clk),
|
1607 |
|
|
.se (se), .si (), .so ()
|
1608 |
|
|
);
|
1609 |
|
|
|
1610 |
|
|
assign lsu_tlb_data_rd_vld_g = data_rd_vld_g ;
|
1611 |
|
|
assign lsu_tlb_tag_rd_vld_g = tag_rd_vld_g ;
|
1612 |
|
|
//assign lsu_tlb_st_vld_g = ~lsu_tlb_tag_rd_vld_g & ~lsu_tlb_data_rd_vld_g ;
|
1613 |
|
|
|
1614 |
|
|
// The handshake will have to change !!!
|
1615 |
|
|
assign lsu_tlu_dtlb_done =
|
1616 |
|
|
dtlb_done_d2 | // rest
|
1617 |
|
|
dtlb_wr_init_d3 ; // write
|
1618 |
|
|
|
1619 |
|
|
// Note : if mx_sel bit is high, then it selects va instead of pa.
|
1620 |
|
|
|
1621 |
|
|
|
1622 |
|
|
|
1623 |
|
|
//=========================================================================================
|
1624 |
|
|
// State/ASI Registers.
|
1625 |
|
|
//=========================================================================================
|
1626 |
|
|
|
1627 |
|
|
dff_s #(8) stctl_stg_e (
|
1628 |
|
|
.din ({ifu_tlu_sraddr_d[6:0],ifu_tlu_wsr_inst_d}),
|
1629 |
|
|
.q ({lsu_sraddr_e[6:0], lsu_wsr_inst_e}),
|
1630 |
|
|
.clk (clk),
|
1631 |
|
|
.se (se), .si (), .so ()
|
1632 |
|
|
);
|
1633 |
|
|
|
1634 |
|
|
assign lsu_tlu_wsr_inst_e = lsu_wsr_inst_e;
|
1635 |
|
|
|
1636 |
|
|
wire asi_state_wr_en_e, asi_state_wr_en_m;
|
1637 |
|
|
|
1638 |
|
|
assign asi_state_wr_en_e =
|
1639 |
|
|
~lsu_sraddr_e[6] & // 1=hypervisor
|
1640 |
|
|
~lsu_sraddr_e[5] & // =0 for state reg.
|
1641 |
|
|
~lsu_sraddr_e[4] & ~lsu_sraddr_e[3] &
|
1642 |
|
|
~lsu_sraddr_e[2] & lsu_sraddr_e[1] &
|
1643 |
|
|
lsu_sraddr_e[0] &
|
1644 |
|
|
lsu_wsr_inst_e ; // write
|
1645 |
|
|
|
1646 |
|
|
dff_s #(2) stctl_stg_m (
|
1647 |
|
|
.din ({asi_state_wr_en_e, alt_space_e}),
|
1648 |
|
|
.q ({asi_state_wr_en_m, lsu_alt_space_m}),
|
1649 |
|
|
.clk (clk),
|
1650 |
|
|
.se (se), .si (), .so ()
|
1651 |
|
|
);
|
1652 |
|
|
|
1653 |
|
|
dff_s #(2) stctl_stg_w (
|
1654 |
|
|
.din ({asi_state_wr_en_m, lsu_alt_space_m}),
|
1655 |
|
|
.q ({asi_state_wr_en, lsu_alt_space_g}),
|
1656 |
|
|
.clk (clk),
|
1657 |
|
|
.se (se), .si (), .so ()
|
1658 |
|
|
);
|
1659 |
|
|
|
1660 |
|
|
//assign asi_state_wr_en =
|
1661 |
|
|
// ~lsu_sraddr_w[6] & // 1=hypervisor
|
1662 |
|
|
// ~lsu_sraddr_w[5] & // =0 for state reg.
|
1663 |
|
|
// ~lsu_sraddr_w[4] & ~lsu_sraddr_w[3] &
|
1664 |
|
|
// ~lsu_sraddr_w[2] & lsu_sraddr_w[1] &
|
1665 |
|
|
// lsu_sraddr_w[0] &
|
1666 |
|
|
// lsu_wsr_inst_w ; // write
|
1667 |
|
|
|
1668 |
|
|
|
1669 |
|
|
dff_s #(3) asi_stgw (
|
1670 |
|
|
.din ({tlu_lsu_asi_update_m,tlu_lsu_tid_m[1:0]}),
|
1671 |
|
|
.q ({tlu_lsu_asi_update_g,tlu_lsu_tid_g[1:0]}),
|
1672 |
|
|
.clk (clk),
|
1673 |
|
|
.se (se), .si (), .so ()
|
1674 |
|
|
);
|
1675 |
|
|
|
1676 |
|
|
|
1677 |
|
|
assign tsa_update_asi0 = ~tlu_lsu_tid_g[1] & ~tlu_lsu_tid_g[0] & tlu_lsu_asi_update_g ;
|
1678 |
|
|
assign tsa_update_asi1 = ~tlu_lsu_tid_g[1] & tlu_lsu_tid_g[0] & tlu_lsu_asi_update_g ;
|
1679 |
|
|
assign tsa_update_asi2 = tlu_lsu_tid_g[1] & ~tlu_lsu_tid_g[0] & tlu_lsu_asi_update_g ;
|
1680 |
|
|
assign tsa_update_asi3 = tlu_lsu_tid_g[1] & tlu_lsu_tid_g[0] & tlu_lsu_asi_update_g ;
|
1681 |
|
|
|
1682 |
|
|
assign asi_state_wr_thrd[0] =
|
1683 |
|
|
((asi_state_wr_en & thread0_g) | tsa_update_asi0) & lsu_inst_vld_w & ~dctl_early_flush_w ;
|
1684 |
|
|
//((asi_state_wr_en & thread0_g) | tsa_update_asi0) & lsu_inst_vld_w & ~lsu_flush_pipe_w ;
|
1685 |
|
|
assign asi_state_wr_thrd[1] =
|
1686 |
|
|
((asi_state_wr_en & thread1_g) | tsa_update_asi1) & lsu_inst_vld_w & ~dctl_early_flush_w ;
|
1687 |
|
|
assign asi_state_wr_thrd[2] =
|
1688 |
|
|
((asi_state_wr_en & thread2_g) | tsa_update_asi2) & lsu_inst_vld_w & ~dctl_early_flush_w ;
|
1689 |
|
|
assign asi_state_wr_thrd[3] =
|
1690 |
|
|
((asi_state_wr_en & thread3_g) | tsa_update_asi3) & lsu_inst_vld_w & ~dctl_early_flush_w ;
|
1691 |
|
|
|
1692 |
|
|
// dc diagnstc will swo on write.
|
1693 |
|
|
assign sta_internal_e = asi_internal_e & st_inst_vld_e & alt_space_e ;
|
1694 |
|
|
// dc diagnstc will not swo on read.
|
1695 |
|
|
assign lda_internal_e = asi_internal_e & ~dc_diagnstc_asi_e & ld_inst_vld_e & alt_space_e ;
|
1696 |
|
|
|
1697 |
|
|
assign ldsta_internal_e = sta_internal_e | lda_internal_e ;
|
1698 |
|
|
|
1699 |
|
|
// MMU_ASI
|
1700 |
|
|
// Do no switch out for lds. lds switched out thru ldst_miss.
|
1701 |
|
|
// qualification must be removed.
|
1702 |
|
|
assign lsu_ifu_ldsta_internal_e = asi_internal_e ;
|
1703 |
|
|
//assign lsu_ifu_ldsta_internal_e = asi_internal_e & ~ld_inst_vld_e ;
|
1704 |
|
|
|
1705 |
|
|
|
1706 |
|
|
dff_s #(2) stai_stgm (
|
1707 |
|
|
.din ({sta_internal_e,lda_internal_e}),
|
1708 |
|
|
.q ({sta_internal_m,lda_internal_m}),
|
1709 |
|
|
.clk (clk),
|
1710 |
|
|
.se (se), .si (), .so ()
|
1711 |
|
|
);
|
1712 |
|
|
|
1713 |
|
|
wire stxa_internal_m;
|
1714 |
|
|
assign stxa_internal_m = sta_internal_m & ~(dtagv_diagnstc_asi_m | dc_diagnstc_asi_m);
|
1715 |
|
|
|
1716 |
|
|
dff_s #(2) stai_stgg (
|
1717 |
|
|
.din ({stxa_internal_m, lda_internal_m}),
|
1718 |
|
|
.q ({stxa_internal, ldxa_internal}),
|
1719 |
|
|
.clk (clk),
|
1720 |
|
|
.se (se), .si (), .so ()
|
1721 |
|
|
);
|
1722 |
|
|
|
1723 |
|
|
wire [7:0] ldst_va_g;
|
1724 |
|
|
|
1725 |
|
|
assign ldst_va_g[7:0] = lsu_ldst_va_g[7:0];
|
1726 |
|
|
|
1727 |
|
|
wire [7:0] lsu_asi_state ;
|
1728 |
|
|
dff_s #(8) asistate_stgg (
|
1729 |
|
|
.din (lsu_dctl_asi_state_m[7:0]),
|
1730 |
|
|
.q (lsu_asi_state[7:0]),
|
1731 |
|
|
.clk (clk),
|
1732 |
|
|
.se (se), .si (), .so ()
|
1733 |
|
|
);
|
1734 |
|
|
|
1735 |
|
|
assign pctxt_va_vld = (ldst_va_g[7:0] == 8'h08) ;
|
1736 |
|
|
assign pctxt_state_en = (lsu_asi_state[7:0] == 8'h21) & pctxt_va_vld &
|
1737 |
|
|
lsu_alt_space_g & lsu_inst_vld_w ;
|
1738 |
|
|
|
1739 |
|
|
|
1740 |
|
|
//assign pctxt_state_wr_thrd[0] = pctxt_state_en & st_inst_vld_g & thread0_g ;
|
1741 |
|
|
assign pctxt_state_wr_thrd[0] = pctxt_state_en & asi_st_vld_g & thread0_g ;
|
1742 |
|
|
assign pctxt_state_wr_thrd[1] = pctxt_state_en & asi_st_vld_g & thread1_g ;
|
1743 |
|
|
assign pctxt_state_wr_thrd[2] = pctxt_state_en & asi_st_vld_g & thread2_g ;
|
1744 |
|
|
assign pctxt_state_wr_thrd[3] = pctxt_state_en & asi_st_vld_g & thread3_g ;
|
1745 |
|
|
|
1746 |
|
|
//assign pctxt_state_rd_en[0] = pctxt_state_en & ld_inst_vld_g & thread0_g ;
|
1747 |
|
|
|
1748 |
|
|
//assign pctxt_state_rd_en[0] = pctxt_state_en & asi_ld_vld_g & thread0_g ;
|
1749 |
|
|
//assign pctxt_state_rd_en[1] = pctxt_state_en & asi_ld_vld_g & thread1_g ;
|
1750 |
|
|
//assign pctxt_state_rd_en[2] = pctxt_state_en & asi_ld_vld_g & thread2_g ;
|
1751 |
|
|
//assign pctxt_state_rd_en[3] = pctxt_state_en & asi_ld_vld_g & thread3_g ;
|
1752 |
|
|
|
1753 |
|
|
|
1754 |
|
|
assign sctxt_va_vld = (ldst_va_g[7:0] == 8'h10) ;
|
1755 |
|
|
assign sctxt_state_en = (lsu_asi_state[7:0] == 8'h21) & sctxt_va_vld &
|
1756 |
|
|
lsu_alt_space_g & lsu_inst_vld_w ;
|
1757 |
|
|
|
1758 |
|
|
assign pscxt_ldxa_illgl_va =
|
1759 |
|
|
(lsu_asi_state[7:0] == 8'h21) & ~(pctxt_va_vld | sctxt_va_vld) &
|
1760 |
|
|
lsu_alt_space_g & lsu_inst_vld_w ;
|
1761 |
|
|
|
1762 |
|
|
//assign sctxt_state_wr_thrd[0] = sctxt_state_en & st_inst_vld_g & thread0_g ;
|
1763 |
|
|
assign sctxt_state_wr_thrd[0] = sctxt_state_en & asi_st_vld_g & thread0_g ;
|
1764 |
|
|
assign sctxt_state_wr_thrd[1] = sctxt_state_en & asi_st_vld_g & thread1_g ;
|
1765 |
|
|
assign sctxt_state_wr_thrd[2] = sctxt_state_en & asi_st_vld_g & thread2_g ;
|
1766 |
|
|
assign sctxt_state_wr_thrd[3] = sctxt_state_en & asi_st_vld_g & thread3_g ;
|
1767 |
|
|
|
1768 |
|
|
//assign sctxt_state_rd_en[0] = sctxt_state_en & ld_inst_vld_g & thread0_g ;
|
1769 |
|
|
|
1770 |
|
|
//assign sctxt_state_rd_en[0] = sctxt_state_en & asi_ld_vld_g & thread0_g ;
|
1771 |
|
|
//assign sctxt_state_rd_en[1] = sctxt_state_en & asi_ld_vld_g & thread1_g ;
|
1772 |
|
|
//assign sctxt_state_rd_en[2] = sctxt_state_en & asi_ld_vld_g & thread2_g ;
|
1773 |
|
|
//assign sctxt_state_rd_en[3] = sctxt_state_en & asi_ld_vld_g & thread3_g ;
|
1774 |
|
|
|
1775 |
|
|
|
1776 |
|
|
// LSU CONTROL REGISTER. ASI=0x45,VA=0x00.
|
1777 |
|
|
// b0 - i$ enable.
|
1778 |
|
|
// b1 - d$ enable.
|
1779 |
|
|
// b2 - immu enable.
|
1780 |
|
|
// b3 - dmmu enable.
|
1781 |
|
|
|
1782 |
|
|
assign lsuctl_va_vld = (ldst_va_g[7:0] == 8'h00);
|
1783 |
|
|
assign lsu_ctl_state_en = (lsu_asi_state[7:0] == 8'h45) & lsuctl_va_vld &
|
1784 |
|
|
lsu_alt_space_g & lsu_inst_vld_w ;
|
1785 |
|
|
assign lsuctl_illgl_va = (lsu_asi_state[7:0] == 8'h45) & ~lsuctl_va_vld &
|
1786 |
|
|
lsu_alt_space_g & lsu_inst_vld_w ;
|
1787 |
|
|
|
1788 |
|
|
wire [3:0] lctl_rst ;
|
1789 |
|
|
|
1790 |
|
|
//assign lsu_ctl_state_wr_en[0] = (lsu_ctl_state_en & st_inst_vld_g & thread0_g) | lctl_rst[0] ;
|
1791 |
|
|
assign lsu_ctl_state_wr_en[0] = (lsu_ctl_state_en & asi_st_vld_g & thread0_g) | lctl_rst[0] ;
|
1792 |
|
|
assign lsu_ctl_state_wr_en[1] = (lsu_ctl_state_en & asi_st_vld_g & thread1_g) | lctl_rst[1] ;
|
1793 |
|
|
assign lsu_ctl_state_wr_en[2] = (lsu_ctl_state_en & asi_st_vld_g & thread2_g) | lctl_rst[2];
|
1794 |
|
|
assign lsu_ctl_state_wr_en[3] = (lsu_ctl_state_en & asi_st_vld_g & thread3_g) | lctl_rst[3];
|
1795 |
|
|
|
1796 |
|
|
//assign lsu_ctl_state_rd_en[0] = lsu_ctl_state_en & ld_inst_vld_g & thread0_g ;
|
1797 |
|
|
//assign lsu_ctl_state_rd_en[0] = lsu_ctl_state_en & asi_ld_vld_g & thread0_g ;
|
1798 |
|
|
//assign lsu_ctl_state_rd_en[1] = lsu_ctl_state_en & asi_ld_vld_g & thread1_g ;
|
1799 |
|
|
//assign lsu_ctl_state_rd_en[2] = lsu_ctl_state_en & asi_ld_vld_g & thread2_g ;
|
1800 |
|
|
//assign lsu_ctl_state_rd_en[3] = lsu_ctl_state_en & asi_ld_vld_g & thread3_g ;
|
1801 |
|
|
|
1802 |
|
|
|
1803 |
|
|
|
1804 |
|
|
wire [3:0] redmode_rst ;
|
1805 |
|
|
//dff #(4) rdmode_stgd1 (
|
1806 |
|
|
// .din ({tlu_lsu_redmode_rst[3:0]}),
|
1807 |
|
|
// .q ({redmode_rst[3:0]}),
|
1808 |
|
|
// .clk (clk),
|
1809 |
|
|
// .se (se), .si (), .so ()
|
1810 |
|
|
// );
|
1811 |
|
|
|
1812 |
|
|
assign redmode_rst[3:0] = tlu_lsu_redmode_rst_d1[3:0];
|
1813 |
|
|
|
1814 |
|
|
assign lctl_rst[0] = redmode_rst[0] | reset ;
|
1815 |
|
|
assign lctl_rst[1] = redmode_rst[1] | reset ;
|
1816 |
|
|
assign lctl_rst[2] = redmode_rst[2] | reset ;
|
1817 |
|
|
assign lctl_rst[3] = redmode_rst[3] | reset ;
|
1818 |
|
|
|
1819 |
|
|
assign lsuctl_ctlbits_wr_en[0] = lsu_ctl_state_wr_en[0] | dfture_tap_wr_en[0] | lctl_rst[0];
|
1820 |
|
|
assign lsuctl_ctlbits_wr_en[1] = lsu_ctl_state_wr_en[1] | dfture_tap_wr_en[1] | lctl_rst[1];
|
1821 |
|
|
assign lsuctl_ctlbits_wr_en[2] = lsu_ctl_state_wr_en[2] | dfture_tap_wr_en[2] | lctl_rst[2];
|
1822 |
|
|
assign lsuctl_ctlbits_wr_en[3] = lsu_ctl_state_wr_en[3] | dfture_tap_wr_en[3] | lctl_rst[3];
|
1823 |
|
|
|
1824 |
|
|
assign dfture_tap_wr_mx_sel = | dfture_tap_wr_en[3:0];
|
1825 |
|
|
|
1826 |
|
|
// Could enhance bypass/enable conditions by adding all asi conditions.
|
1827 |
|
|
wire [5:0] lsu_ctl_reg0;
|
1828 |
|
|
wire [5:0] lsu_ctl_reg1;
|
1829 |
|
|
wire [5:0] lsu_ctl_reg2;
|
1830 |
|
|
wire [5:0] lsu_ctl_reg3;
|
1831 |
|
|
|
1832 |
|
|
assign lsu_ctl_reg0[5:0] = lsu_dp_ctl_reg0[5:0];
|
1833 |
|
|
assign lsu_ctl_reg1[5:0] = lsu_dp_ctl_reg1[5:0];
|
1834 |
|
|
assign lsu_ctl_reg2[5:0] = lsu_dp_ctl_reg2[5:0];
|
1835 |
|
|
assign lsu_ctl_reg3[5:0] = lsu_dp_ctl_reg3[5:0];
|
1836 |
|
|
|
1837 |
|
|
wire lsu_dcache_enable;
|
1838 |
|
|
assign lsu_dcache_enable =
|
1839 |
|
|
((lsu_ctl_reg0[1] & thread0_e) | (lsu_ctl_reg1[1] & thread1_e) |
|
1840 |
|
|
(lsu_ctl_reg2[1] & thread2_e) | (lsu_ctl_reg3[1] & thread3_e)) ;
|
1841 |
|
|
|
1842 |
|
|
assign lsuctl_dtlb_byp_e =
|
1843 |
|
|
(~lsu_ctl_reg0[3] & thread0_e) | (~lsu_ctl_reg1[3] & thread1_e) |
|
1844 |
|
|
(~lsu_ctl_reg2[3] & thread2_e) | (~lsu_ctl_reg3[3] & thread3_e) ;
|
1845 |
|
|
assign dtlb_bypass_e =
|
1846 |
|
|
(lsuctl_dtlb_byp_e & ~hpstate_en_e) | // hpv enabled - byp is RA->PA for supv.
|
1847 |
|
|
( tlb_byp_asi_e & ~hpstate_en_e & altspace_ldst_e) | // altspace tlb bypass - non-hpv
|
1848 |
|
|
((hpv_priv_e & hpstate_en_e) & ~(alt_space_e & (as_if_user_asi_e | tlb_byp_asi_e)));
|
1849 |
|
|
// hpv enabled VA->PA
|
1850 |
|
|
|
1851 |
|
|
assign lsu_dtlb_bypass_e = dtlb_bypass_e ;
|
1852 |
|
|
wire dcache_enable_m,dcache_enable_g ;
|
1853 |
|
|
dff_s #(2) dbyp_stgm (
|
1854 |
|
|
.din ({dtlb_bypass_e,lsu_dcache_enable}),
|
1855 |
|
|
.q ({dtlb_bypass_m,dcache_enable_m}),
|
1856 |
|
|
.clk (clk),
|
1857 |
|
|
.se (se), .si (), .so ()
|
1858 |
|
|
);
|
1859 |
|
|
|
1860 |
|
|
dff_s #(2) dbyp_stgg (
|
1861 |
|
|
.din ({dtlb_bypass_m,dcache_enable_m}),
|
1862 |
|
|
.q ({lsu_dtlb_bypass_g,dcache_enable_g}),
|
1863 |
|
|
.clk (clk),
|
1864 |
|
|
.se (se), .si (), .so ()
|
1865 |
|
|
);
|
1866 |
|
|
|
1867 |
|
|
wire lsu_ctl_reg0_bf_b0, lsu_ctl_reg1_bf_b0, lsu_ctl_reg2_bf_b0, lsu_ctl_reg3_bf_b0;
|
1868 |
|
|
wire lsu_ctl_reg0_bf_b2, lsu_ctl_reg1_bf_b2, lsu_ctl_reg2_bf_b2, lsu_ctl_reg3_bf_b2;
|
1869 |
|
|
|
1870 |
|
|
bw_u1_buf_1x UZsize_ctl_reg0_b0 ( .a(lsu_ctl_reg0[0]), .z(lsu_ctl_reg0_bf_b0) );
|
1871 |
|
|
bw_u1_buf_1x UZsize_ctl_reg0_b2 ( .a(lsu_ctl_reg0[2]), .z(lsu_ctl_reg0_bf_b2) );
|
1872 |
|
|
bw_u1_buf_1x UZsize_ctl_reg1_b0 ( .a(lsu_ctl_reg1[0]), .z(lsu_ctl_reg1_bf_b0) );
|
1873 |
|
|
bw_u1_buf_1x UZsize_ctl_reg1_b2 ( .a(lsu_ctl_reg1[2]), .z(lsu_ctl_reg1_bf_b2) );
|
1874 |
|
|
bw_u1_buf_1x UZsize_ctl_reg2_b0 ( .a(lsu_ctl_reg2[0]), .z(lsu_ctl_reg2_bf_b0) );
|
1875 |
|
|
bw_u1_buf_1x UZsize_ctl_reg2_b2 ( .a(lsu_ctl_reg2[2]), .z(lsu_ctl_reg2_bf_b2) );
|
1876 |
|
|
bw_u1_buf_1x UZsize_ctl_reg3_b0 ( .a(lsu_ctl_reg3[0]), .z(lsu_ctl_reg3_bf_b0) );
|
1877 |
|
|
bw_u1_buf_1x UZsize_ctl_reg3_b2 ( .a(lsu_ctl_reg3[2]), .z(lsu_ctl_reg3_bf_b2) );
|
1878 |
|
|
|
1879 |
|
|
assign lsu_ifu_icache_en[3:0] =
|
1880 |
|
|
{lsu_ctl_reg3_bf_b0,lsu_ctl_reg2_bf_b0,lsu_ctl_reg1_bf_b0,lsu_ctl_reg0_bf_b0} & ~tlu_lsu_redmode[3:0] ;
|
1881 |
|
|
assign lsu_ifu_itlb_en[3:0] =
|
1882 |
|
|
{lsu_ctl_reg3_bf_b2,lsu_ctl_reg2_bf_b2,lsu_ctl_reg1_bf_b2,lsu_ctl_reg0_bf_b2} & ~tlu_lsu_redmode[3:0] ;
|
1883 |
|
|
|
1884 |
|
|
//=========================================================================================
|
1885 |
|
|
// DCACHE Access thru IOBrdge
|
1886 |
|
|
//=========================================================================================
|
1887 |
|
|
|
1888 |
|
|
wire iob_fwdpkt_vld ;
|
1889 |
|
|
dff_s iobvld_stg (
|
1890 |
|
|
.din (lsu_iobrdge_fwd_pkt_vld),
|
1891 |
|
|
.q (iob_fwdpkt_vld),
|
1892 |
|
|
.clk (clk),
|
1893 |
|
|
.se (se), .si (), .so ()
|
1894 |
|
|
);
|
1895 |
|
|
|
1896 |
|
|
wire dcache_iob_wr_e, dcache_iob_rd_e ;
|
1897 |
|
|
wire dcache_iob_wr, dcache_iob_rd ;
|
1898 |
|
|
assign dcache_iob_wr =
|
1899 |
|
|
~lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[6] & lsu_iobrdge_fwd_pkt_vld ;
|
1900 |
|
|
assign dcache_iob_rd =
|
1901 |
|
|
lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[6] & lsu_iobrdge_fwd_pkt_vld ;
|
1902 |
|
|
|
1903 |
|
|
dff_s #(2) dcrw_stge (
|
1904 |
|
|
.din ({dcache_iob_wr,dcache_iob_rd}),
|
1905 |
|
|
.q ({dcache_iob_wr_e,dcache_iob_rd_e}),
|
1906 |
|
|
.clk (clk),
|
1907 |
|
|
.se (se), .si (), .so ()
|
1908 |
|
|
);
|
1909 |
|
|
|
1910 |
|
|
assign lsu_dc_iob_access_e = dcache_iob_wr_e | dcache_iob_rd_e ;
|
1911 |
|
|
|
1912 |
|
|
//=========================================================================================
|
1913 |
|
|
// Miscellaneous ASI
|
1914 |
|
|
//=========================================================================================
|
1915 |
|
|
|
1916 |
|
|
// Defeature effects the asi lsu_ctl_reg.
|
1917 |
|
|
// Margin ASI
|
1918 |
|
|
// Diag ASI - No TAP access
|
1919 |
|
|
// BIST ASI
|
1920 |
|
|
|
1921 |
|
|
assign tap_thread[0] = ~lsu_iobrdge_tap_rq_type_b1_b0[1] & ~lsu_iobrdge_tap_rq_type_b1_b0[0] ;
|
1922 |
|
|
assign tap_thread[1] = ~lsu_iobrdge_tap_rq_type_b1_b0[1] & lsu_iobrdge_tap_rq_type_b1_b0[0] ;
|
1923 |
|
|
assign tap_thread[2] = lsu_iobrdge_tap_rq_type_b1_b0[1] & ~lsu_iobrdge_tap_rq_type_b1_b0[0] ;
|
1924 |
|
|
assign tap_thread[3] = lsu_iobrdge_tap_rq_type_b1_b0[1] & lsu_iobrdge_tap_rq_type_b1_b0[0] ;
|
1925 |
|
|
|
1926 |
|
|
wire bist_tap_rd,bist_tap_wr ;
|
1927 |
|
|
assign bist_tap_rd =
|
1928 |
|
|
lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[5] & iob_fwdpkt_vld ;
|
1929 |
|
|
assign bist_tap_wr =
|
1930 |
|
|
~lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[5] & iob_fwdpkt_vld ;
|
1931 |
|
|
|
1932 |
|
|
/*
|
1933 |
|
|
dff_s #(2) bstrw_stge (
|
1934 |
|
|
.din ({bist_tap_rd,bist_tap_wr}),
|
1935 |
|
|
.q ({bist_tap_rd_en,bist_tap_wr_en}),
|
1936 |
|
|
.clk (clk),
|
1937 |
|
|
.se (se), .si (), .so ()
|
1938 |
|
|
);
|
1939 |
|
|
*/
|
1940 |
|
|
dff_s #(1) bstrw_stge (
|
1941 |
|
|
.din ({bist_tap_wr}),
|
1942 |
|
|
.q ({bist_tap_wr_en}),
|
1943 |
|
|
.clk (clk),
|
1944 |
|
|
.se (se), .si (), .so ()
|
1945 |
|
|
);
|
1946 |
|
|
|
1947 |
|
|
wire mrgn_tap_rd,mrgn_tap_wr ;
|
1948 |
|
|
assign mrgn_tap_rd =
|
1949 |
|
|
lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[4] & iob_fwdpkt_vld ;
|
1950 |
|
|
assign mrgn_tap_wr =
|
1951 |
|
|
~lsu_iobrdge_tap_rq_type_b8[8] & lsu_iobrdge_tap_rq_type_b6_b3[4] & iob_fwdpkt_vld ;
|
1952 |
|
|
/*
|
1953 |
|
|
dff_s #(2) mrgnrw_stge (
|
1954 |
|
|
.din ({mrgn_tap_rd,mrgn_tap_wr}),
|
1955 |
|
|
.q ({mrgn_tap_rd_en,mrgn_tap_wr_en}),
|
1956 |
|
|
.clk (clk),
|
1957 |
|
|
.se (se), .si (), .so ()
|
1958 |
|
|
);
|
1959 |
|
|
*/
|
1960 |
|
|
dff_s #(1) mrgnrw_stge (
|
1961 |
|
|
.din ({mrgn_tap_wr}),
|
1962 |
|
|
.q ({mrgn_tap_wr_en}),
|
1963 |
|
|
.clk (clk),
|
1964 |
|
|
.se (se), .si (), .so ()
|
1965 |
|
|
);
|
1966 |
|
|
|
1967 |
|
|
wire dfture_access_vld ;
|
1968 |
|
|
wire [3:0] dfture_tap_rd,dfture_tap_wr ;
|
1969 |
|
|
assign dfture_access_vld = lsu_iobrdge_tap_rq_type_b6_b3[3] & iob_fwdpkt_vld ;
|
1970 |
|
|
|
1971 |
|
|
assign dfture_tap_rd[0] =
|
1972 |
|
|
lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[0] ;
|
1973 |
|
|
assign dfture_tap_rd[1] =
|
1974 |
|
|
lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[1] ;
|
1975 |
|
|
assign dfture_tap_rd[2] =
|
1976 |
|
|
lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[2] ;
|
1977 |
|
|
assign dfture_tap_rd[3] =
|
1978 |
|
|
lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[3] ;
|
1979 |
|
|
|
1980 |
|
|
wire dfture_tap_rd_default;
|
1981 |
|
|
assign dfture_tap_rd_default = ~| dfture_tap_rd[2:0];
|
1982 |
|
|
|
1983 |
|
|
assign dfture_tap_wr[0] =
|
1984 |
|
|
~lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[0] ;
|
1985 |
|
|
assign dfture_tap_wr[1] =
|
1986 |
|
|
~lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[1] ;
|
1987 |
|
|
assign dfture_tap_wr[2] =
|
1988 |
|
|
~lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[2] ;
|
1989 |
|
|
assign dfture_tap_wr[3] =
|
1990 |
|
|
~lsu_iobrdge_tap_rq_type_b8[8] & dfture_access_vld & tap_thread[3] ;
|
1991 |
|
|
|
1992 |
|
|
dff_s #(8) dftrw_stge (
|
1993 |
|
|
.din ({dfture_tap_rd_default, dfture_tap_rd[2:0],dfture_tap_wr[3:0]}),
|
1994 |
|
|
.q ({dfture_tap_rd_d1[3:0], dfture_tap_wr_en[3:0]}),
|
1995 |
|
|
.clk (clk),
|
1996 |
|
|
.se (se), .si (), .so ()
|
1997 |
|
|
);
|
1998 |
|
|
|
1999 |
|
|
|
2000 |
|
|
assign dfture_tap_rd_en [0] = dfture_tap_rd_d1[0] & ~rst_tri_en;
|
2001 |
|
|
assign dfture_tap_rd_en [1] = dfture_tap_rd_d1[1] & ~rst_tri_en;
|
2002 |
|
|
assign dfture_tap_rd_en [2] = dfture_tap_rd_d1[2] & ~rst_tri_en;
|
2003 |
|
|
assign dfture_tap_rd_en [3] = dfture_tap_rd_d1[3] | rst_tri_en;
|
2004 |
|
|
|
2005 |
|
|
|
2006 |
|
|
// BIST_Controller ASI
|
2007 |
|
|
|
2008 |
|
|
wire bistctl_va_vld_m,bistctl_state_en_m;
|
2009 |
|
|
assign bistctl_va_vld_m = (lsu_ldst_va_b7_b0_m[7:0] == 8'h00);
|
2010 |
|
|
assign bistctl_state_en_m = (lsu_dctl_asi_state_m[7:0] == 8'h42) & bistctl_va_vld_m &
|
2011 |
|
|
lsu_alt_space_m ;
|
2012 |
|
|
dff_s #(2) bistdcd_stw (
|
2013 |
|
|
.din ({bistctl_va_vld_m,bistctl_state_en_m}),
|
2014 |
|
|
.q ({bistctl_va_vld,bistctl_state_en}),
|
2015 |
|
|
.clk (clk),
|
2016 |
|
|
.se (se), .si (), .so ()
|
2017 |
|
|
);
|
2018 |
|
|
// asi42 dealt with as a whole.
|
2019 |
|
|
/*assign bistctl_illgl_va = (lsu_asi_state[7:0] == 8'h42) & ~bistctl_va_vld &
|
2020 |
|
|
lsu_alt_space_g ;*/
|
2021 |
|
|
//assign bistctl_rd_en = bistctl_state_en & asi_ld_vld_g ;
|
2022 |
|
|
assign bistctl_wr_en = (bistctl_state_en & asi_st_vld_g) | bist_tap_wr_en ;
|
2023 |
|
|
//assign bistctl_rd_en = bistctl_state_en & ld_inst_vld_g ;
|
2024 |
|
|
//assign bistctl_wr_en = (bistctl_state_en & st_inst_vld_g) | bist_tap_wr_en ;
|
2025 |
|
|
|
2026 |
|
|
//test_stub interface. bist_tap_wr_en should exclude?
|
2027 |
|
|
assign bist_ctl_reg_wr_en = bistctl_wr_en;
|
2028 |
|
|
|
2029 |
|
|
|
2030 |
|
|
// Self-Timed Margin Control ASI
|
2031 |
|
|
|
2032 |
|
|
wire mrgnctl_va_vld_m,mrgnctl_state_en_m;
|
2033 |
|
|
assign mrgnctl_va_vld_m = (lsu_ldst_va_b7_b0_m[7:0] == 8'h00);
|
2034 |
|
|
assign mrgnctl_state_en_m = (lsu_dctl_asi_state_m[7:0] == 8'h44) & mrgnctl_va_vld_m &
|
2035 |
|
|
lsu_alt_space_m ;
|
2036 |
|
|
dff_s #(2) mrgndcd_stw (
|
2037 |
|
|
.din ({mrgnctl_va_vld_m,mrgnctl_state_en_m}),
|
2038 |
|
|
.q ({mrgnctl_va_vld,mrgnctl_state_en}),
|
2039 |
|
|
.clk (clk),
|
2040 |
|
|
.se (se), .si (), .so ()
|
2041 |
|
|
);
|
2042 |
|
|
|
2043 |
|
|
assign mrgnctl_illgl_va = (lsu_asi_state[7:0] == 8'h44) & ~mrgnctl_va_vld &
|
2044 |
|
|
lsu_alt_space_g ;
|
2045 |
|
|
|
2046 |
|
|
assign mrgnctl_wr_en = ((mrgnctl_state_en & asi_st_vld_g) | mrgn_tap_wr_en | ~dctl_rst_l) & ~sehold; //bug 4508
|
2047 |
|
|
|
2048 |
|
|
// LSU Diag Reg ASI
|
2049 |
|
|
// No access from tap.
|
2050 |
|
|
wire ldiagctl_va_vld_m,ldiagctl_state_en_m;
|
2051 |
|
|
assign ldiagctl_va_vld_m = (lsu_ldst_va_b7_b0_m[7:0] == 8'h10);
|
2052 |
|
|
assign ldiagctl_state_en_m = (lsu_dctl_asi_state_m[7:0] == 8'h42) & ldiagctl_va_vld_m &
|
2053 |
|
|
lsu_alt_space_m ;
|
2054 |
|
|
dff_s #(2) ldiagdcd_stw (
|
2055 |
|
|
.din ({ldiagctl_va_vld_m,ldiagctl_state_en_m}),
|
2056 |
|
|
.q ({ldiagctl_va_vld,ldiagctl_state_en}),
|
2057 |
|
|
.clk (clk),
|
2058 |
|
|
.se (se), .si (), .so ()
|
2059 |
|
|
);
|
2060 |
|
|
// asi42 dealt with as a whole.
|
2061 |
|
|
/*assign ldiagctl_illgl_va = (lsu_asi_state[7:0] == 8'h42) & ~ldiagctl_va_vld &
|
2062 |
|
|
lsu_alt_space_g ;*/
|
2063 |
|
|
|
2064 |
|
|
wire asi42_g ;
|
2065 |
|
|
wire ifu_asi42_flush_g ;
|
2066 |
|
|
assign ifu_asi42_flush_g =
|
2067 |
|
|
bistctl_state_en | ldiagctl_state_en | // lsu's asi42 should not set asi queue.
|
2068 |
|
|
(asi42_g & asi42_illgl_va) ; // illgl-va should not set asi queue.
|
2069 |
|
|
|
2070 |
|
|
//assign ldiagctl_rd_en = ldiagctl_state_en & asi_ld_vld_g ;
|
2071 |
|
|
assign ldiagctl_wr_en = (ldiagctl_state_en & asi_st_vld_g) | reset;
|
2072 |
|
|
//assign ldiagctl_rd_en = ldiagctl_state_en & ld_inst_vld_g ;
|
2073 |
|
|
//assign ldiagctl_wr_en = (ldiagctl_state_en & st_inst_vld_g) | reset;
|
2074 |
|
|
|
2075 |
|
|
wire instmsk_va_vld ;
|
2076 |
|
|
assign instmsk_va_vld = (ldst_va_g[7:0] == 8'h08);
|
2077 |
|
|
assign asi42_g = (lsu_asi_state[7:0] == 8'h42) ;
|
2078 |
|
|
assign asi42_illgl_va =
|
2079 |
|
|
asi42_g &
|
2080 |
|
|
~(ldiagctl_va_vld | bistctl_va_vld | instmsk_va_vld) &
|
2081 |
|
|
lsu_alt_space_g ;
|
2082 |
|
|
|
2083 |
|
|
|
2084 |
|
|
|
2085 |
|
|
//=========================================================================================
|
2086 |
|
|
// Partition ID Register
|
2087 |
|
|
//=========================================================================================
|
2088 |
|
|
|
2089 |
|
|
// ASI=58, VA=0x80, Per thread
|
2090 |
|
|
// The pid is to be used by tlb-cam, and writes to tlb. It is kept in the lsu
|
2091 |
|
|
// as it is used by the dtlb, plus changes to mmu_dp are to be kept to a minimum.
|
2092 |
|
|
|
2093 |
|
|
// Trap if supervisor accesses hyperpriv asi - see supv_use_hyp. Could be incorrect.
|
2094 |
|
|
// Correct on merge to mainline.
|
2095 |
|
|
|
2096 |
|
|
// The VA compares can probably be shortened.
|
2097 |
|
|
assign pid_va_vld = (ldst_va_g[7:0] == 8'h80);
|
2098 |
|
|
assign pid_state_en = (lsu_asi_state[7:0] == 8'h58) & pid_va_vld &
|
2099 |
|
|
lsu_alt_space_g & lsu_inst_vld_w ;
|
2100 |
|
|
//assign pid_illgl_va = (lsu_asi_state[7:0] == 8'h58) & ~pid_va_vld &
|
2101 |
|
|
// lsu_alt_space_g & lsu_inst_vld_w ;
|
2102 |
|
|
|
2103 |
|
|
// remove reset ??
|
2104 |
|
|
//assign pid_state_wr_en[0] = (pid_state_en & st_inst_vld_g & thread0_g) | reset ;
|
2105 |
|
|
assign pid_state_wr_en[0] = (pid_state_en & asi_st_vld_g & thread0_g) | reset ;
|
2106 |
|
|
assign pid_state_wr_en[1] = (pid_state_en & asi_st_vld_g & thread1_g) | reset ;
|
2107 |
|
|
assign pid_state_wr_en[2] = (pid_state_en & asi_st_vld_g & thread2_g) | reset ;
|
2108 |
|
|
assign pid_state_wr_en[3] = (pid_state_en & asi_st_vld_g & thread3_g) | reset ;
|
2109 |
|
|
|
2110 |
|
|
//assign pid_state_rd_en[0] = pid_state_en & ld_inst_vld_g & thread0_g ;
|
2111 |
|
|
|
2112 |
|
|
//assign pid_state_rd_en[0] = pid_state_en & asi_ld_vld_g & thread0_g ;
|
2113 |
|
|
//assign pid_state_rd_en[1] = pid_state_en & asi_ld_vld_g & thread1_g ;
|
2114 |
|
|
//assign pid_state_rd_en[2] = pid_state_en & asi_ld_vld_g & thread2_g ;
|
2115 |
|
|
//assign pid_state_rd_en[3] = pid_state_en & asi_ld_vld_g & thread3_g ;
|
2116 |
|
|
|
2117 |
|
|
|
2118 |
|
|
//=========================================================================================
|
2119 |
|
|
// Local LDXA Read
|
2120 |
|
|
//=========================================================================================
|
2121 |
|
|
|
2122 |
|
|
// Timing : rd_en changed to _en with inst_vld
|
2123 |
|
|
|
2124 |
|
|
//wire [3:0] misc_ctl_sel ;
|
2125 |
|
|
wire misc_tap_rd_sel ;
|
2126 |
|
|
/*
|
2127 |
|
|
assign misc_tap_rd_sel = mrgn_tap_rd_en | bist_tap_rd_en | dfture_tap_rd_sel ;
|
2128 |
|
|
assign misc_ctl_sel[0] = bist_tap_rd_en | (~misc_tap_rd_sel & bistctl_state_en & ld_inst_vld_unflushed) ;
|
2129 |
|
|
assign misc_ctl_sel[1] = mrgn_tap_rd_en | (~misc_tap_rd_sel & mrgnctl_state_en & ld_inst_vld_unflushed) ;
|
2130 |
|
|
assign misc_ctl_sel[3] = dfture_tap_rd_sel ;
|
2131 |
|
|
|
2132 |
|
|
//assign misc_ctl_sel[2] = (~misc_tap_rd_sel & ldiagctl_state_en & ld_inst_vld_unflushed) ;
|
2133 |
|
|
assign misc_ctl_sel[2] = ~(misc_ctl_sel[0] | misc_ctl_sel[1] | misc_ctl_sel[3] ); //force default
|
2134 |
|
|
*/
|
2135 |
|
|
|
2136 |
|
|
//****push misc_ctl_sel in previosu cycle*****
|
2137 |
|
|
wire [3:0] misc_ctl_sel_din;
|
2138 |
|
|
|
2139 |
|
|
//0-in bug, priority encode tap requests to prevent illegal type through one-hot mux
|
2140 |
|
|
wire dfture_tap_rd_or ;
|
2141 |
|
|
assign dfture_tap_rd_or = | (dfture_tap_rd [3:0]);
|
2142 |
|
|
assign misc_tap_rd_sel = mrgn_tap_rd | bist_tap_rd | dfture_tap_rd_or ;
|
2143 |
|
|
assign misc_ctl_sel_din[0] = bist_tap_rd |
|
2144 |
|
|
(~misc_tap_rd_sel & bistctl_state_en_m & ld_inst_vld_m) ;
|
2145 |
|
|
assign misc_ctl_sel_din[1] = (~bist_tap_rd & mrgn_tap_rd) |
|
2146 |
|
|
(~misc_tap_rd_sel & mrgnctl_state_en_m & ld_inst_vld_m) ;
|
2147 |
|
|
assign misc_ctl_sel_din[3] = ~bist_tap_rd & ~mrgn_tap_rd & dfture_tap_rd_or;
|
2148 |
|
|
assign misc_ctl_sel_din[2] = ~(misc_ctl_sel_din[0] | misc_ctl_sel_din[1] | misc_ctl_sel_din[3] ) ;
|
2149 |
|
|
|
2150 |
|
|
|
2151 |
|
|
|
2152 |
|
|
// ASI accesses should be mutex except for non-access cases.
|
2153 |
|
|
assign lsu_asi_sel_fmx1[0] = pctxt_state_en & ld_inst_vld_unflushed;
|
2154 |
|
|
assign lsu_asi_sel_fmx1[1] = sctxt_state_en & ld_inst_vld_unflushed & ~lsu_asi_sel_fmx1[0];
|
2155 |
|
|
assign lsu_asi_sel_fmx1[2] = ~(|lsu_asi_sel_fmx1[1:0]); //force default
|
2156 |
|
|
|
2157 |
|
|
assign lsu_asi_sel_fmx2[0] = |lsu_asi_sel_fmx1[1:0] | (pid_state_en & ld_inst_vld_unflushed) ;
|
2158 |
|
|
assign lsu_asi_sel_fmx2[1] = lsu_ctl_state_en & ld_inst_vld_unflushed & ~(lsu_asi_sel_fmx2[0]);
|
2159 |
|
|
assign lsu_asi_sel_fmx2[2] = ~(|lsu_asi_sel_fmx2[1:0]) ; //force default
|
2160 |
|
|
|
2161 |
|
|
wire va_wtchpt_en;
|
2162 |
|
|
|
2163 |
|
|
wire lsu_asi_rd_sel ;
|
2164 |
|
|
//assign lsu_asi_rd_sel = ((|lsu_asi_sel_fmx1[1:0]) |
|
2165 |
|
|
// ((pid_state_en | va_wtchpt_en) & ld_inst_vld_unflushed) |
|
2166 |
|
|
// (|lsu_asi_sel_fmx2[1:0]) |
|
2167 |
|
|
// misc_asi_rd_en) &
|
2168 |
|
|
// lsu_inst_vld_w ;
|
2169 |
|
|
|
2170 |
|
|
assign lsu_asi_rd_sel = ((|lsu_asi_sel_fmx1[1:0]) |
|
2171 |
|
|
(pid_state_en & ld_inst_vld_unflushed) | //remove va_wtchpt_en
|
2172 |
|
|
(|lsu_asi_sel_fmx2[1:0]) |
|
2173 |
|
|
misc_asi_rd_en) &
|
2174 |
|
|
lsu_inst_vld_w ;
|
2175 |
|
|
|
2176 |
|
|
|
2177 |
|
|
assign lsu_asi_rd_en = (lsu_asi_rd_sel | lsu_va_wtchpt_sel_g) & ~dctl_early_flush_w ; //add va_wtchpt
|
2178 |
|
|
|
2179 |
|
|
//assign lsu_asi_rd_en = lsu_asi_rd_sel & ~lsu_flush_pipe_w ;
|
2180 |
|
|
|
2181 |
|
|
assign misc_asi_rd_en = (bistctl_state_en | mrgnctl_state_en | ldiagctl_state_en) & ld_inst_vld_unflushed ;
|
2182 |
|
|
|
2183 |
|
|
assign lsu_local_ldxa_sel_g = lsu_asi_rd_sel & ~rst_tri_en ; // w/o flush
|
2184 |
|
|
assign lsu_local_ldxa_tlbrd_sel_g = (lsu_tlb_tag_rd_vld_g | lsu_tlb_data_rd_vld_g) & ~rst_tri_en;
|
2185 |
|
|
assign lsu_va_wtchpt_sel_g = (va_wtchpt_en & ld_inst_vld_unflushed) & ~rst_tri_en;
|
2186 |
|
|
|
2187 |
|
|
assign lsu_local_diagnstc_tagrd_sel_g = (~(lsu_local_ldxa_sel_g | lsu_local_ldxa_tlbrd_sel_g |
|
2188 |
|
|
lsu_va_wtchpt_sel_g)) | rst_tri_en; //add va_wtchpt
|
2189 |
|
|
|
2190 |
|
|
// or diagnostic read w/ asi read enable
|
2191 |
|
|
assign lsu_diagnstc_asi_rd_en = lsu_asi_rd_en | dtagv_diagnstc_rd_g ; //Bug 3959
|
2192 |
|
|
//assign lsu_diagnstc_asi_rd_en = lsu_asi_rd_en | dtagv_diagnstc_rd_g | lsu_local_ldxa_tlbrd_sel_g;
|
2193 |
|
|
|
2194 |
|
|
|
2195 |
|
|
dff_s #(1) lldxa_stw2 (
|
2196 |
|
|
.din (lsu_diagnstc_asi_rd_en),
|
2197 |
|
|
.q (lsu_asi_rd_en_w2),
|
2198 |
|
|
.clk (clk),
|
2199 |
|
|
.se (se), .si (), .so ()
|
2200 |
|
|
);
|
2201 |
|
|
|
2202 |
|
|
wire ldxa_tlbrd0_w2,ldxa_tlbrd1_w2,ldxa_tlbrd2_w2,ldxa_tlbrd3_w2;
|
2203 |
|
|
wire ldxa_tlbrd0_w3,ldxa_tlbrd1_w3,ldxa_tlbrd2_w3,ldxa_tlbrd3_w3;
|
2204 |
|
|
|
2205 |
|
|
// stg mismatched intentionally. stxa_tid decode can be used by ldxa.
|
2206 |
|
|
assign ldxa_tlbrd3_w2 = tlu_stxa_thread3_w2 & lsu_local_ldxa_tlbrd_sel_g ;
|
2207 |
|
|
assign ldxa_tlbrd2_w2 = tlu_stxa_thread2_w2 & lsu_local_ldxa_tlbrd_sel_g ;
|
2208 |
|
|
assign ldxa_tlbrd1_w2 = tlu_stxa_thread1_w2 & lsu_local_ldxa_tlbrd_sel_g ;
|
2209 |
|
|
assign ldxa_tlbrd0_w2 = tlu_stxa_thread0_w2 & lsu_local_ldxa_tlbrd_sel_g ;
|
2210 |
|
|
|
2211 |
|
|
// Bug 3959
|
2212 |
|
|
dff_s #(4) tlbrd_stw3 (
|
2213 |
|
|
.din ({ldxa_tlbrd3_w2,ldxa_tlbrd2_w2,
|
2214 |
|
|
ldxa_tlbrd1_w2,ldxa_tlbrd0_w2}),
|
2215 |
|
|
.q ({ldxa_tlbrd3_w3,ldxa_tlbrd2_w3,
|
2216 |
|
|
ldxa_tlbrd1_w3,ldxa_tlbrd0_w3}),
|
2217 |
|
|
.clk (clk),
|
2218 |
|
|
.se (se), .si (), .so ()
|
2219 |
|
|
);
|
2220 |
|
|
|
2221 |
|
|
// pid and va-wtchpt va removed.
|
2222 |
|
|
assign lsu_asi_illgl_va =
|
2223 |
|
|
lsuctl_illgl_va | pscxt_ldxa_illgl_va | mrgnctl_illgl_va | asi42_illgl_va ;
|
2224 |
|
|
assign lsu_asi_illgl_va_cmplt[0] = lsu_asi_illgl_va & ld_inst_vld_g & thread0_g ;
|
2225 |
|
|
assign lsu_asi_illgl_va_cmplt[1] = lsu_asi_illgl_va & ld_inst_vld_g & thread1_g ;
|
2226 |
|
|
assign lsu_asi_illgl_va_cmplt[2] = lsu_asi_illgl_va & ld_inst_vld_g & thread2_g ;
|
2227 |
|
|
assign lsu_asi_illgl_va_cmplt[3] = lsu_asi_illgl_va & ld_inst_vld_g & thread3_g ;
|
2228 |
|
|
|
2229 |
|
|
dff_s #(4) lsuillgl_stgw2(
|
2230 |
|
|
.din (lsu_asi_illgl_va_cmplt[3:0]),
|
2231 |
|
|
.q (lsu_asi_illgl_va_cmplt_w2[3:0]),
|
2232 |
|
|
.clk (clk),
|
2233 |
|
|
.se (se), .si (), .so ()
|
2234 |
|
|
);
|
2235 |
|
|
|
2236 |
|
|
//=========================================================================================
|
2237 |
|
|
// ASI_DCACHE_TAG way decode
|
2238 |
|
|
//=========================================================================================
|
2239 |
|
|
|
2240 |
|
|
// Bug 4569.
|
2241 |
|
|
// add sehold. adding in dctldp flop will cause critical path.
|
2242 |
|
|
|
2243 |
|
|
wire [3:0] dtag_rsel_dcd,dtag_rsel_hold ;
|
2244 |
|
|
assign dtag_rsel_dcd[3:0] = {(lsu_ldst_va_b12_b11_m[12:11] == 2'b11),
|
2245 |
|
|
(lsu_ldst_va_b12_b11_m[12:11] == 2'b10),
|
2246 |
|
|
(lsu_ldst_va_b12_b11_m[12:11] == 2'b01),
|
2247 |
|
|
(lsu_ldst_va_b12_b11_m[12:11] == 2'b00)};
|
2248 |
|
|
//bug5994
|
2249 |
|
|
dffe_s #(4) dtag_hold (
|
2250 |
|
|
.din (dtag_rsel_dcd[3:0]),
|
2251 |
|
|
.q (dtag_rsel_hold[3:0]),
|
2252 |
|
|
.en (sehold),
|
2253 |
|
|
.clk (clk),
|
2254 |
|
|
.se (se), .si (), .so ()
|
2255 |
|
|
);
|
2256 |
|
|
|
2257 |
|
|
assign lsu_dtag_rsel_m[3:0] = sehold ? dtag_rsel_hold[3:0] : dtag_rsel_dcd[3:0] ;
|
2258 |
|
|
|
2259 |
|
|
|
2260 |
|
|
//=========================================================================================
|
2261 |
|
|
// Watchpoint Control
|
2262 |
|
|
//=========================================================================================
|
2263 |
|
|
wire va_vld;
|
2264 |
|
|
|
2265 |
|
|
assign va_vld = (ldst_va_g[7:0] == 8'h38);
|
2266 |
|
|
|
2267 |
|
|
assign va_wtchpt_en = (lsu_asi_state[7:0] == 8'h58) & va_vld &
|
2268 |
|
|
lsu_alt_space_g & lsu_inst_vld_w ;
|
2269 |
|
|
|
2270 |
|
|
// Illegal va checking for asi 58 done in MMU.
|
2271 |
|
|
|
2272 |
|
|
// one VA watchptr supported per thread
|
2273 |
|
|
|
2274 |
|
|
// Need to read register !!!
|
2275 |
|
|
// Switchout thread on read.
|
2276 |
|
|
// qualify with inst_vld_w.
|
2277 |
|
|
//assign va_wtchpt_rd_en = va_wtchpt_en & ld_inst_vld_g ;
|
2278 |
|
|
|
2279 |
|
|
wire va_wtchpt0_wr_en, va_wtchpt1_wr_en, va_wtchpt2_wr_en, va_wtchpt3_wr_en;
|
2280 |
|
|
|
2281 |
|
|
//assign va_wtchpt0_wr_en = va_wtchpt_en & st_inst_vld_g & thread0_g;
|
2282 |
|
|
assign va_wtchpt0_wr_en = va_wtchpt_en & asi_st_vld_g & thread0_g;
|
2283 |
|
|
assign va_wtchpt1_wr_en = va_wtchpt_en & asi_st_vld_g & thread1_g;
|
2284 |
|
|
assign va_wtchpt2_wr_en = va_wtchpt_en & asi_st_vld_g & thread2_g;
|
2285 |
|
|
assign va_wtchpt3_wr_en = va_wtchpt_en & asi_st_vld_g & thread3_g;
|
2286 |
|
|
assign lsu_va_wtchpt0_wr_en_l = ~va_wtchpt0_wr_en ;
|
2287 |
|
|
assign lsu_va_wtchpt1_wr_en_l = ~va_wtchpt1_wr_en ;
|
2288 |
|
|
assign lsu_va_wtchpt2_wr_en_l = ~va_wtchpt2_wr_en ;
|
2289 |
|
|
assign lsu_va_wtchpt3_wr_en_l = ~va_wtchpt3_wr_en ;
|
2290 |
|
|
|
2291 |
|
|
assign vw_wtchpt_cmp_en_m = // VA Write Watchpoint Enable
|
2292 |
|
|
(thread0_m & lsu_ctl_reg0[4]) |
|
2293 |
|
|
(thread1_m & lsu_ctl_reg1[4]) |
|
2294 |
|
|
(thread2_m & lsu_ctl_reg2[4]) |
|
2295 |
|
|
(thread3_m & lsu_ctl_reg3[4]) ;
|
2296 |
|
|
|
2297 |
|
|
assign vr_wtchpt_cmp_en_m = // VA Read Watchpoint Enable
|
2298 |
|
|
(thread0_m & lsu_ctl_reg0[5]) |
|
2299 |
|
|
(thread1_m & lsu_ctl_reg1[5]) |
|
2300 |
|
|
(thread2_m & lsu_ctl_reg2[5]) |
|
2301 |
|
|
(thread3_m & lsu_ctl_reg3[5]) ;
|
2302 |
|
|
|
2303 |
|
|
assign va_wtchpt_cmp_en_m =
|
2304 |
|
|
(vw_wtchpt_cmp_en_m & st_inst_vld_m) |
|
2305 |
|
|
(vr_wtchpt_cmp_en_m & ld_inst_vld_m) ;
|
2306 |
|
|
|
2307 |
|
|
//=========================================================================================
|
2308 |
|
|
// Hit/Miss/Fill Control
|
2309 |
|
|
//=========================================================================================
|
2310 |
|
|
dff_s #(10) stg_m (
|
2311 |
|
|
.din ({ld_inst_vld_e, st_inst_vld_e,ldst_sz_e[1:0],
|
2312 |
|
|
ifu_lsu_rd_e[4:0],ifu_lsu_ldst_fp_e}),
|
2313 |
|
|
.q ({ld_inst_vld_m, st_inst_vld_m,ldst_sz_m[1:0],
|
2314 |
|
|
ld_rd_m[4:0],fp_ldst_m}),
|
2315 |
|
|
.clk (clk),
|
2316 |
|
|
.se (se), .si (), .so ()
|
2317 |
|
|
);
|
2318 |
|
|
|
2319 |
|
|
wire dcache_arry_data_sel_e;
|
2320 |
|
|
|
2321 |
|
|
assign dcache_arry_data_sel_e = lsu_bist_rvld_e | ld_inst_vld_e | dcache_iob_rd_e ;
|
2322 |
|
|
dff_s #(1) dcache_arry_data_sel_stgm (
|
2323 |
|
|
.din (dcache_arry_data_sel_e),
|
2324 |
|
|
.q (dcache_arry_data_sel_m),
|
2325 |
|
|
.clk (clk),
|
2326 |
|
|
.se (se), .si (), .so ()
|
2327 |
|
|
);
|
2328 |
|
|
|
2329 |
|
|
|
2330 |
|
|
dff_s #(10) stg_g (
|
2331 |
|
|
.din ({ld_inst_vld_m, st_inst_vld_m,ldst_sz_m[1:0],
|
2332 |
|
|
ld_rd_m[4:0],fp_ldst_m}),
|
2333 |
|
|
.q ({ld_inst_vld_unflushed, st_inst_vld_unflushed,ldst_sz_g[1:0],
|
2334 |
|
|
ld_rd_g[4:0],fp_ldst_g}),
|
2335 |
|
|
.clk (clk),
|
2336 |
|
|
.se (se), .si (), .so ()
|
2337 |
|
|
);
|
2338 |
|
|
|
2339 |
|
|
|
2340 |
|
|
//assign asi_ld_vld_g = ld_inst_vld_unflushed & lsu_inst_vld_w & ~dctl_early_flush_w ;
|
2341 |
|
|
assign asi_st_vld_g = st_inst_vld_unflushed & lsu_inst_vld_w & ~dctl_early_flush_w ;
|
2342 |
|
|
assign ld_inst_vld_g = ld_inst_vld_unflushed & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
|
2343 |
|
|
assign st_inst_vld_g = st_inst_vld_unflushed & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
|
2344 |
|
|
|
2345 |
|
|
assign lsu_way_hit[0] = cache_way_hit_buf1[0] & dcache_enable_g ;
|
2346 |
|
|
assign lsu_way_hit[1] = cache_way_hit_buf1[1] & dcache_enable_g ;
|
2347 |
|
|
assign lsu_way_hit[2] = cache_way_hit_buf1[2] & dcache_enable_g ;
|
2348 |
|
|
assign lsu_way_hit[3] = cache_way_hit_buf1[3] & dcache_enable_g ;
|
2349 |
|
|
|
2350 |
|
|
//assign st_set_index_g[5:0] = ldst_va_g[9:4] ;
|
2351 |
|
|
//assign st_set_way_g[3:1] = lsu_way_hit[3:1] ;
|
2352 |
|
|
|
2353 |
|
|
// This should contain ld miss, MMU miss, exception.
|
2354 |
|
|
// should tlb_cam_miss be factored in or can miss/hit be solely
|
2355 |
|
|
// based on way_hit.
|
2356 |
|
|
|
2357 |
|
|
wire tlb_cam_hit_mod ;
|
2358 |
|
|
dff_s stgcmiss_g (
|
2359 |
|
|
.din (tlb_cam_hit),
|
2360 |
|
|
.q (tlb_cam_hit_mod),
|
2361 |
|
|
.clk (clk),
|
2362 |
|
|
.se (se), .si (), .so ()
|
2363 |
|
|
);
|
2364 |
|
|
|
2365 |
|
|
// NOTE !! qualification with tte_data_parity_error removed for timing.
|
2366 |
|
|
assign tlb_cam_hit_g = tlb_cam_hit_mod ;
|
2367 |
|
|
//assign tlb_cam_hit_g = tlb_cam_hit_mod & ~tte_data_parity_error ;
|
2368 |
|
|
|
2369 |
|
|
/*assign ld_stb_hit_g =
|
2370 |
|
|
ld_stb0_full_raw_g | ld_stb1_full_raw_g |
|
2371 |
|
|
ld_stb2_full_raw_g | ld_stb3_full_raw_g |
|
2372 |
|
|
ld_stb0_partial_raw_g | ld_stb1_partial_raw_g |
|
2373 |
|
|
ld_stb2_partial_raw_g | ld_stb3_partial_raw_g ; */
|
2374 |
|
|
|
2375 |
|
|
wire nceen_pipe_m, nceen_pipe_g ;
|
2376 |
|
|
|
2377 |
|
|
wire [3:0] lsu_nceen_d1;
|
2378 |
|
|
|
2379 |
|
|
dff_s #(4) nceen_stg (
|
2380 |
|
|
.din (ifu_lsu_nceen[3:0]),
|
2381 |
|
|
.q (lsu_nceen_d1[3:0]),
|
2382 |
|
|
.clk (clk),
|
2383 |
|
|
.se (se), .si (), .so ()
|
2384 |
|
|
);
|
2385 |
|
|
|
2386 |
|
|
|
2387 |
|
|
assign nceen_pipe_m =
|
2388 |
|
|
(thread0_m & lsu_nceen_d1[0]) | (thread1_m & lsu_nceen_d1[1]) |
|
2389 |
|
|
(thread2_m & lsu_nceen_d1[2]) | (thread3_m & lsu_nceen_d1[3]) ;
|
2390 |
|
|
|
2391 |
|
|
dff_s #(1) stgg_een (
|
2392 |
|
|
.din (nceen_pipe_m),
|
2393 |
|
|
.q (nceen_pipe_g),
|
2394 |
|
|
.clk (clk),
|
2395 |
|
|
.se (se), .si (), .so ()
|
2396 |
|
|
);
|
2397 |
|
|
|
2398 |
|
|
//wire tte_data_perror_corr_en ;
|
2399 |
|
|
wire tte_data_perror_unc_en ;
|
2400 |
|
|
// separate ld from st for error reporting.
|
2401 |
|
|
assign tte_data_perror_unc_en = ld_inst_vld_unflushed & tte_data_perror_unc & nceen_pipe_g ;
|
2402 |
|
|
//assign tte_data_perror_unc_en = tte_data_perror_unc & nceen_pipe_g ;
|
2403 |
|
|
//assign tte_data_perror_corr_en = tte_data_perror_corr ;
|
2404 |
|
|
//assign tte_data_perror_corr_en = tte_data_perror_corr & ceen_pipe_g ;
|
2405 |
|
|
|
2406 |
|
|
wire dtlb_perror_en_w,dtlb_perror_en_w2,dtlb_perror_en_w3 ;
|
2407 |
|
|
assign dtlb_perror_en_w = tte_data_perror_unc_en ;
|
2408 |
|
|
//assign dtlb_perror_en_w = tte_data_perror_unc_en | tte_data_perror_corr_en ;
|
2409 |
|
|
|
2410 |
|
|
dff_s #(1) stgw2_perr (
|
2411 |
|
|
.din (dtlb_perror_en_w),
|
2412 |
|
|
.q (dtlb_perror_en_w2),
|
2413 |
|
|
.clk (clk),
|
2414 |
|
|
.se (se), .si (), .so ()
|
2415 |
|
|
);
|
2416 |
|
|
|
2417 |
|
|
dff_s #(1) stgw3_perr (
|
2418 |
|
|
.din (dtlb_perror_en_w2),
|
2419 |
|
|
.q (dtlb_perror_en_w3),
|
2420 |
|
|
.clk (clk),
|
2421 |
|
|
.se (se), .si (), .so ()
|
2422 |
|
|
);
|
2423 |
|
|
|
2424 |
|
|
// For now, "or" ld_inst_vld_g and ldst_dbl. Ultimately, it ldst_dbl
|
2425 |
|
|
// needs to cause ld_inst_vld_g to be asserted.
|
2426 |
|
|
// st and ld ldst_dbl terms are redundant.
|
2427 |
|
|
// Diagnostic Dcache access will force a hit in cache. Whatever is read
|
2428 |
|
|
// out will be written back to irf regardless of whether hit or not. The
|
2429 |
|
|
// expectation is that cache has been set up to hit.
|
2430 |
|
|
// lsu_dcache_enable is redundant as factored in lsu_way_hit !!!
|
2431 |
|
|
// squash both ld_miss and ld_hit in cause of dtlb unc data error.
|
2432 |
|
|
wire ldd_force_l2access_g;
|
2433 |
|
|
|
2434 |
|
|
wire int_ldd_g, fp_ldd_g;
|
2435 |
|
|
assign fp_ldd_g = fp_ldst_g & ~(blk_asi_g & lsu_alt_space_g);
|
2436 |
|
|
|
2437 |
|
|
//sas code need int_ldd_g
|
2438 |
|
|
assign int_ldd_g = ldst_dbl_g & ~fp_ldd_g;
|
2439 |
|
|
assign ldd_force_l2access_g = int_ldd_g;
|
2440 |
|
|
|
2441 |
|
|
assign lsu_ld_miss_wb =
|
2442 |
|
|
(~(|lsu_way_hit[3:0]) | ~dcache_enable_g | ~(tlb_cam_hit_g | lsu_dtlb_bypass_g) |
|
2443 |
|
|
ldxa_internal | ldd_force_l2access_g | atomic_g | endian_mispred_g | // remove stb_cam_hit
|
2444 |
|
|
dcache_rd_parity_error | dtag_perror_g) &
|
2445 |
|
|
~((dc_diagnstc_asi_g & lsu_alt_space_g)) &
|
2446 |
|
|
//~(tte_data_perror_unc_en | tte_data_perror_corr_en | (dc_diagnstc_asi_g & lsu_alt_space_g)) &
|
2447 |
|
|
(ld_vld & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g))) |
|
2448 |
|
|
//(ld_inst_vld_g & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g))) |
|
2449 |
|
|
//(ldst_dbl_g & st_inst_vld_g) // signal ld-miss for stdbl.
|
2450 |
|
|
ncache_asild_rq_g ; // asi ld requires bypass
|
2451 |
|
|
|
2452 |
|
|
assign lsu_ld_hit_wb =
|
2453 |
|
|
((|lsu_way_hit[3:0]) & dcache_enable_g & (tlb_cam_hit_g | lsu_dtlb_bypass_g) & //bug3702
|
2454 |
|
|
~ldxa_internal & ~dcache_rd_parity_error & ~dtag_perror_g & ~endian_mispred_g &
|
2455 |
|
|
~ldd_force_l2access_g & ~atomic_g & ~ncache_asild_rq_g) & // remove stb_cam_hit
|
2456 |
|
|
~((dc_diagnstc_asi_g & lsu_alt_space_g)) &
|
2457 |
|
|
//~(tte_data_perror_unc_en | tte_data_perror_corr_en | (dc_diagnstc_asi_g & lsu_alt_space_g)) &
|
2458 |
|
|
ld_vld & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g)) ;
|
2459 |
|
|
//ld_inst_vld_g & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g)) ;
|
2460 |
|
|
// force hit for diagnostic write.
|
2461 |
|
|
|
2462 |
|
|
// correctible dtlb data parity error on cam will cause dmmu miss.
|
2463 |
|
|
// prefetch will rely on the ld_inst_vld/st_inst_vld not being asserted
|
2464 |
|
|
// to prevent mmu_miss from being signalled if prefetch does not translate.
|
2465 |
|
|
// Timing Change : Remove data perror from dmmu_miss ; to be treated as disrupting trap.
|
2466 |
|
|
//SC assign dmmu_miss_g =
|
2467 |
|
|
//SC ~tlb_cam_hit_mod & ~lsu_dtlb_bypass_g &
|
2468 |
|
|
//SC //~(tlb_cam_hit_mod & ~tte_data_perror_corr) & ~lsu_dtlb_bypass_g &
|
2469 |
|
|
//SC ((ld_inst_vld_unflushed & lsu_inst_vld_w) |
|
2470 |
|
|
//SC (st_inst_vld_unflushed & lsu_inst_vld_w)) &
|
2471 |
|
|
//SC ~(ldxa_internal | stxa_internal | early_trap_vld_g) ;
|
2472 |
|
|
|
2473 |
|
|
//SC wire dmmu_miss_only_g ;
|
2474 |
|
|
|
2475 |
|
|
//SC assign dmmu_miss_only_g =
|
2476 |
|
|
//SC ~tlb_cam_hit_mod & ~lsu_dtlb_bypass_g &
|
2477 |
|
|
//SC //~(tlb_cam_hit_mod & ~tte_data_perror_corr) & ~lsu_dtlb_bypass_g &
|
2478 |
|
|
//SC ((ld_inst_vld_unflushed & lsu_inst_vld_w) |
|
2479 |
|
|
//SC (st_inst_vld_unflushed & lsu_inst_vld_w)) &
|
2480 |
|
|
//SC ~(ldxa_internal | stxa_internal);
|
2481 |
|
|
|
2482 |
|
|
// Atomic Handling :
|
2483 |
|
|
// Bypass to irf will occur. However, the loads will not write to cache/tag etc.
|
2484 |
|
|
|
2485 |
|
|
// Exceptions, tlb miss will have to be included.
|
2486 |
|
|
// diagnostic dcache/dtagv will read respective arrays in pipeline. (changed!)
|
2487 |
|
|
// They will not switch out thread with this assumption.
|
2488 |
|
|
|
2489 |
|
|
//dc_diagnstc will not switch out, dtagv will switch out
|
2490 |
|
|
|
2491 |
|
|
//wire dc_diagnstc_rd_g;
|
2492 |
|
|
//assign dc_diagnstc_rd_g = dc_diagnstc_asi_g & ld_inst_vld_g & lsu_alt_space_g ;
|
2493 |
|
|
|
2494 |
|
|
//wire dc0_diagnstc_rd_g,dc1_diagnstc_rd_g,dc2_diagnstc_rd_g,dc3_diagnstc_rd_g ;
|
2495 |
|
|
//wire dc0_diagnstc_rd_w2,dc1_diagnstc_rd_w2,dc2_diagnstc_rd_w2,dc3_diagnstc_rd_w2 ;
|
2496 |
|
|
//assign dc0_diagnstc_rd_g = dc_diagnstc_rd_g & thread0_g ;
|
2497 |
|
|
//assign dc1_diagnstc_rd_g = dc_diagnstc_rd_g & thread1_g ;
|
2498 |
|
|
//assign dc2_diagnstc_rd_g = dc_diagnstc_rd_g & thread2_g ;
|
2499 |
|
|
//assign dc3_diagnstc_rd_g = dc_diagnstc_rd_g & thread3_g ;
|
2500 |
|
|
|
2501 |
|
|
//dff #(4) stgw2_dcdiag (
|
2502 |
|
|
// .din ({dc3_diagnstc_rd_g,dc2_diagnstc_rd_g,dc1_diagnstc_rd_g,dc0_diagnstc_rd_g}),
|
2503 |
|
|
// .q ({dc3_diagnstc_rd_w2,dc2_diagnstc_rd_w2,dc1_diagnstc_rd_w2,dc0_diagnstc_rd_w2}),
|
2504 |
|
|
// .clk (clk),
|
2505 |
|
|
// .se (se), .si (), .so ()
|
2506 |
|
|
// );
|
2507 |
|
|
|
2508 |
|
|
assign dtagv_diagnstc_rd_g = dtagv_diagnstc_asi_g & ld_inst_vld_g & lsu_alt_space_g ;
|
2509 |
|
|
|
2510 |
|
|
// Prefetch will swo thread if it does not miss in tlb.
|
2511 |
|
|
dff_s stgm_prf (
|
2512 |
|
|
.din (ifu_lsu_pref_inst_e),
|
2513 |
|
|
.q (pref_inst_m),
|
2514 |
|
|
.clk (clk),
|
2515 |
|
|
.se (se), .si (), .so ()
|
2516 |
|
|
);
|
2517 |
|
|
|
2518 |
|
|
dff_s stgg_prf (
|
2519 |
|
|
.din (pref_inst_m),
|
2520 |
|
|
.q (pref_inst_g),
|
2521 |
|
|
.clk (clk),
|
2522 |
|
|
.se (se), .si (), .so ()
|
2523 |
|
|
);
|
2524 |
|
|
|
2525 |
|
|
|
2526 |
|
|
|
2527 |
|
|
//assign lsu_ifu_data_error_w = 1'b0 ;
|
2528 |
|
|
|
2529 |
|
|
// is this redundant ? isn't lsu_ncache_ld_e sufficient ?
|
2530 |
|
|
assign atomic_ld_squash_e =
|
2531 |
|
|
~lmq_ld_rq_type_e[2] & lmq_ld_rq_type_e[1] & lmq_ld_rq_type_e[0] ;
|
2532 |
|
|
|
2533 |
|
|
// bypass will occur with hit in d$ or data return from L2.
|
2534 |
|
|
// Fill for dcache diagnostic rd will happen regardless. dfill vld qualified with
|
2535 |
|
|
// flush_pipe and inst_vld !!!
|
2536 |
|
|
|
2537 |
|
|
//timing fix. move logic to previous cycle M.
|
2538 |
|
|
//assign lsu_exu_dfill_vld_w2 =
|
2539 |
|
|
// (l2fill_vld_g & ~(unc_err_trap_g | l2fill_fpld_g)) | // fill
|
2540 |
|
|
// (~fp_ldst_g & ld_inst_vld_unflushed & lsu_inst_vld_w) | // in pipe
|
2541 |
|
|
// intld_byp_data_vld ; // bypass
|
2542 |
|
|
|
2543 |
|
|
wire lsu_exu_dfill_vld_m;
|
2544 |
|
|
wire intld_byp_data_vld_e,intld_byp_data_vld_m ;
|
2545 |
|
|
wire intld_byp_data_vld ;
|
2546 |
|
|
wire ldxa_swo_annul ;
|
2547 |
|
|
|
2548 |
|
|
assign lsu_exu_dfill_vld_m =
|
2549 |
|
|
(l2fill_vld_m & ~(unc_err_trap_m | l2fill_fpld_m)) | // fill
|
2550 |
|
|
(~fp_ldst_m & ld_inst_vld_m &
|
2551 |
|
|
~(ldxa_swo_annul & lsu_alt_space_m) & flush_w_inst_vld_m) | // in pipe
|
2552 |
|
|
intld_byp_data_vld_m ; // bypass
|
2553 |
|
|
|
2554 |
|
|
dff_s #(1) dfill_vld_stgg (
|
2555 |
|
|
.din (lsu_exu_dfill_vld_m),
|
2556 |
|
|
.q (lsu_exu_dfill_vld_w2),
|
2557 |
|
|
.clk (clk),
|
2558 |
|
|
.se (se), .si (), .so ()
|
2559 |
|
|
);
|
2560 |
|
|
|
2561 |
|
|
//------
|
2562 |
|
|
// Bld errors : Bug 4315
|
2563 |
|
|
// Errors need to be accummulated across helpers. Once unc error detected
|
2564 |
|
|
// in any helper, then all further writes to frf are squashed.
|
2565 |
|
|
// daccess_error trap taken at very end if *any* helper had an unc error.
|
2566 |
|
|
|
2567 |
|
|
wire bld_cnt_max_m,bld_cnt_max_g ;
|
2568 |
|
|
assign bld_cnt_max_m = lsu_bld_cnt_m[2] & lsu_bld_cnt_m[1] & lsu_bld_cnt_m[0] ;
|
2569 |
|
|
|
2570 |
|
|
wire [1:0] cpx_ld_err_m ;
|
2571 |
|
|
dff_s #(3) lderr_stgm (
|
2572 |
|
|
.din ({lsu_cpx_pkt_ld_err[1:0],bld_cnt_max_m}),
|
2573 |
|
|
.q ({cpx_ld_err_m[1:0],bld_cnt_max_g}),
|
2574 |
|
|
.clk (clk),
|
2575 |
|
|
.se (se), .si (), .so ()
|
2576 |
|
|
);
|
2577 |
|
|
|
2578 |
|
|
wire [1:0] bld_err ;
|
2579 |
|
|
wire [1:0] bld_err_din ;
|
2580 |
|
|
wire bld_rst ;
|
2581 |
|
|
// Accummulate errors.
|
2582 |
|
|
assign bld_err_din[1:0] = cpx_ld_err_m[1:0] | bld_err[1:0] ;
|
2583 |
|
|
assign bld_rst = reset | lsu_bld_reset ;
|
2584 |
|
|
|
2585 |
|
|
dffre_s #(2) blderr_ff (
|
2586 |
|
|
.din (bld_err_din[1:0]),
|
2587 |
|
|
.q (bld_err[1:0]),
|
2588 |
|
|
.clk (clk),
|
2589 |
|
|
.en (lsu_bld_helper_cmplt_m), .rst (bld_rst),
|
2590 |
|
|
.se (se), .si (), .so ()
|
2591 |
|
|
);
|
2592 |
|
|
|
2593 |
|
|
wire bld_helper_cmplt_g ;
|
2594 |
|
|
dff_s bldh_stgg (
|
2595 |
|
|
.din (lsu_bld_helper_cmplt_m),
|
2596 |
|
|
.q (bld_helper_cmplt_g),
|
2597 |
|
|
.clk (clk),
|
2598 |
|
|
.se (se), .si (), .so ()
|
2599 |
|
|
);
|
2600 |
|
|
|
2601 |
|
|
wire bld_unc_err_pend_g, bld_unc_err_pend_w2 ;
|
2602 |
|
|
assign bld_unc_err_pend_g = bld_err[1] & bld_helper_cmplt_g ;
|
2603 |
|
|
wire bld_corr_err_pend_g, bld_corr_err_pend_w2 ;
|
2604 |
|
|
// pended unc error gets priority.
|
2605 |
|
|
assign bld_corr_err_pend_g = bld_err[0] & ~bld_err[1] & bld_helper_cmplt_g ;
|
2606 |
|
|
|
2607 |
|
|
wire bld_squash_err_g,bld_squash_err_w2 ;
|
2608 |
|
|
// bld cnt should be vld till g
|
2609 |
|
|
assign bld_squash_err_g = bld_helper_cmplt_g & ~bld_cnt_max_g ;
|
2610 |
|
|
|
2611 |
|
|
dff_s #(3) bldsq_stgw2 (
|
2612 |
|
|
.din ({bld_squash_err_g,bld_unc_err_pend_g,bld_corr_err_pend_g}),
|
2613 |
|
|
.q ({bld_squash_err_w2,bld_unc_err_pend_w2,bld_corr_err_pend_w2}),
|
2614 |
|
|
.clk (clk),
|
2615 |
|
|
.se (se), .si (), .so ()
|
2616 |
|
|
);
|
2617 |
|
|
|
2618 |
|
|
//------
|
2619 |
|
|
|
2620 |
|
|
wire stb_cam_hit_w2 ;
|
2621 |
|
|
wire fld_vld_sync_no_camhit,fld_vld_sync_no_camhit_w2 ;
|
2622 |
|
|
wire fld_vld_async,fld_vld_async_w2 ;
|
2623 |
|
|
dff_s #(3) stbchit_stg (
|
2624 |
|
|
.din ({stb_cam_hit,fld_vld_sync_no_camhit,fld_vld_async}),
|
2625 |
|
|
.q ({stb_cam_hit_w2,fld_vld_sync_no_camhit_w2,fld_vld_async_w2}),
|
2626 |
|
|
.clk (clk),
|
2627 |
|
|
.se (se), .si (), .so ()
|
2628 |
|
|
);
|
2629 |
|
|
|
2630 |
|
|
assign fld_vld_sync_no_camhit =
|
2631 |
|
|
(lsu_ld_hit_wb & ~tte_data_perror_unc_en & fp_ldst_g &
|
2632 |
|
|
~dctl_flush_pipe_w) ; // l1hit
|
2633 |
|
|
|
2634 |
|
|
assign fld_vld_async =
|
2635 |
|
|
(l2fill_vld_g & l2fill_fpld_g & ~(unc_err_trap_g | bld_unc_err_pend_g)) |
|
2636 |
|
|
// fill from l2, // bug 3705, 4315(err_trap)
|
2637 |
|
|
fpld_byp_data_vld ; // bypass data
|
2638 |
|
|
|
2639 |
|
|
assign lsu_ffu_ld_vld =
|
2640 |
|
|
(fld_vld_sync_no_camhit_w2 & ~stb_cam_hit_w2) |
|
2641 |
|
|
fld_vld_async_w2 ;
|
2642 |
|
|
|
2643 |
|
|
|
2644 |
|
|
/*dff #(1) fldvld_stgw2 (
|
2645 |
|
|
.din (ffu_ld_vld),
|
2646 |
|
|
.q (lsu_ffu_ld_vld),
|
2647 |
|
|
.clk (clk),
|
2648 |
|
|
.se (1'b0), .si (), .so ()
|
2649 |
|
|
); */
|
2650 |
|
|
|
2651 |
|
|
dff_s #(2) dtid_stgm (
|
2652 |
|
|
.din (lsu_dfill_tid_e[1:0]),
|
2653 |
|
|
.q (dfq_tid_m[1:0]),
|
2654 |
|
|
.clk (clk),
|
2655 |
|
|
.se (se), .si (), .so ()
|
2656 |
|
|
);
|
2657 |
|
|
|
2658 |
|
|
dff_s #(2) dtid_stgg (
|
2659 |
|
|
.din (dfq_tid_m[1:0]),
|
2660 |
|
|
.q (dfq_tid_g[1:0]),
|
2661 |
|
|
.clk (clk),
|
2662 |
|
|
.se (se), .si (), .so ()
|
2663 |
|
|
);
|
2664 |
|
|
|
2665 |
|
|
// Timing Change - shifting dfill-data sel gen. to m-stage
|
2666 |
|
|
//assign ldbyp_tid[0] = ld_thrd_byp_sel_g[1] | ld_thrd_byp_sel_g[3] ;
|
2667 |
|
|
//assign ldbyp_tid[1] = ld_thrd_byp_sel_g[2] | ld_thrd_byp_sel_g[3] ;
|
2668 |
|
|
wire [3:0] ld_thrd_byp_sel_m ;
|
2669 |
|
|
assign ldbyp_tid_m[0] = ld_thrd_byp_sel_m[1] | ld_thrd_byp_sel_m[3] ;
|
2670 |
|
|
assign ldbyp_tid_m[1] = ld_thrd_byp_sel_m[2] | ld_thrd_byp_sel_m[3] ;
|
2671 |
|
|
|
2672 |
|
|
|
2673 |
|
|
/*assign lsu_exu_thr_g[1:0] = ld_inst_vld_unflushed ? thrid_g[1:0] :
|
2674 |
|
|
l2fill_vld_g ? dfq_tid_g[1:0] : ldbyp_tid[1:0] ; */
|
2675 |
|
|
assign lsu_exu_thr_m[1:0] = ld_inst_vld_m ? thrid_m[1:0] :
|
2676 |
|
|
l2fill_vld_m ? dfq_tid_m[1:0] : ldbyp_tid_m[1:0] ;
|
2677 |
|
|
|
2678 |
|
|
// What is the policy for load-double/atomics to update cache ?
|
2679 |
|
|
// cas will not update cache. similary neither will ldstub nor cas.
|
2680 |
|
|
// BIST will effect dcache only, not tags and vld bits.
|
2681 |
|
|
// Removed dcache_enable from dc_diagnstc_wr_en !!!
|
2682 |
|
|
wire l2fill_vld_e ;
|
2683 |
|
|
wire dcache_alt_src_wr_e ;
|
2684 |
|
|
assign l2fill_vld_e = lsu_l2fill_vld & ~lsu_cpx_pkt_prefetch2 ;
|
2685 |
|
|
assign lsu_dcache_wr_vld_e =
|
2686 |
|
|
(l2fill_vld_e & ~ignore_fill & ~atomic_ld_squash_e & ~ld_sec_active & ~lsu_ncache_ld_e) |
|
2687 |
|
|
lsu_st_wr_dcache | // st writes from stb
|
2688 |
|
|
dcache_alt_src_wr_e ;
|
2689 |
|
|
|
2690 |
|
|
assign dcache_alt_src_wr_e =
|
2691 |
|
|
(lsu_diagnstc_wr_src_sel_e & dc_diagnstc_wr_en)
|
2692 |
|
|
| lsu_bist_wvld_e // bist engine writes to cache
|
2693 |
|
|
| dcache_iob_wr_e ; // iobridge request write to dcache
|
2694 |
|
|
|
2695 |
|
|
//d$ valid bit
|
2696 |
|
|
wire dv_diagnstic_wr;
|
2697 |
|
|
assign dv_diagnstic_wr = (lsu_diagnstc_wr_src_sel_e & dtagv_diagnstc_wr_en & lsu_diagnstc_wr_data_b0) ;
|
2698 |
|
|
|
2699 |
|
|
wire dva_din_e;
|
2700 |
|
|
wire ld_fill_e;
|
2701 |
|
|
|
2702 |
|
|
assign ld_fill_e= (l2fill_vld_e & ~atomic_ld_squash_e & ~ld_sec_active & ~lsu_ncache_ld_e) ; //ld-fill
|
2703 |
|
|
//######################################
|
2704 |
|
|
//snp => dva_din = 0
|
2705 |
|
|
//ld fill => dva_din = 1
|
2706 |
|
|
//diag wrt => dva_din = wrt_value
|
2707 |
|
|
//######################################
|
2708 |
|
|
assign dva_din_e = ld_fill_e | //ld-fill
|
2709 |
|
|
dv_diagnstic_wr; // diagnostic write valid bit
|
2710 |
|
|
|
2711 |
|
|
|
2712 |
|
|
// iob rd dominates
|
2713 |
|
|
wire lsu_dc_alt_rd_vld_e;
|
2714 |
|
|
|
2715 |
|
|
assign lsu_dc_alt_rd_vld_e = dcache_iob_rd_e | lsu_bist_rvld_e ;
|
2716 |
|
|
|
2717 |
|
|
//?? default when no ld in pipe
|
2718 |
|
|
assign dcache_alt_mx_sel_e =
|
2719 |
|
|
//lsu_dcache_wr_vld_e | : Timing
|
2720 |
|
|
dcache_alt_src_wr_e | // rm st updates/fill - ~ld_inst_vld_e.
|
2721 |
|
|
lsu_dcache_wr_vld_e |
|
2722 |
|
|
lsu_dc_alt_rd_vld_e | ~ld_inst_vld_e;
|
2723 |
|
|
|
2724 |
|
|
assign dcache_alt_mx_sel_e_bf = dcache_alt_mx_sel_e;
|
2725 |
|
|
|
2726 |
|
|
wire dcache_rvld_e_tmp, dcache_rvld_e_minbf;
|
2727 |
|
|
assign dcache_rvld_e_tmp = ld_inst_vld_e | lsu_dc_alt_rd_vld_e ;
|
2728 |
|
|
bw_u1_minbuf_5x UZfix_dcache_rvld_e_minbf (.a(dcache_rvld_e_tmp), .z(dcache_rvld_e_minbf));
|
2729 |
|
|
assign dcache_rvld_e = dcache_rvld_e_minbf;
|
2730 |
|
|
|
2731 |
|
|
wire lsu_dtag_wr_vld_e_tmp;
|
2732 |
|
|
|
2733 |
|
|
assign lsu_dtag_wr_vld_e_tmp =
|
2734 |
|
|
ld_fill_e & ~ignore_fill | //ld fill //bug3601, 3676
|
2735 |
|
|
(lsu_diagnstc_wr_src_sel_e & dtagv_diagnstc_wr_en) ; // dtag/vld diagnostic wr
|
2736 |
|
|
|
2737 |
|
|
bw_u1_buf_30x UZsize_lsu_dtag_wrreq_x ( .a(lsu_dtag_wr_vld_e_tmp), .z(lsu_dtag_wrreq_x_e) );
|
2738 |
|
|
bw_u1_buf_30x UZsize_lsu_dtag_index_sel_x ( .a(lsu_dtag_wr_vld_e_tmp), .z(lsu_dtag_index_sel_x_e) );
|
2739 |
|
|
|
2740 |
|
|
assign lsu_dtagv_wr_vld_e =
|
2741 |
|
|
lsu_dtag_wr_vld_e_tmp | // fill
|
2742 |
|
|
dva_svld_e | // snp
|
2743 |
|
|
lsu_bist_wvld_e ; // bist clears dva by default
|
2744 |
|
|
|
2745 |
|
|
// mem cell change for dva
|
2746 |
|
|
wire [15:0] dva_fill_bit_wr_en_e;
|
2747 |
|
|
|
2748 |
|
|
assign dva_fill_bit_wr_en_e[15] = dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[3];
|
2749 |
|
|
assign dva_fill_bit_wr_en_e[14] = dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[2];
|
2750 |
|
|
assign dva_fill_bit_wr_en_e[13] = dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[1];
|
2751 |
|
|
assign dva_fill_bit_wr_en_e[12] = dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[0];
|
2752 |
|
|
|
2753 |
|
|
assign dva_fill_bit_wr_en_e[11] = dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[3];
|
2754 |
|
|
assign dva_fill_bit_wr_en_e[10] = dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[2];
|
2755 |
|
|
assign dva_fill_bit_wr_en_e[09] = dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[1];
|
2756 |
|
|
assign dva_fill_bit_wr_en_e[08] = dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[0];
|
2757 |
|
|
|
2758 |
|
|
assign dva_fill_bit_wr_en_e[07] = ~dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[3];
|
2759 |
|
|
assign dva_fill_bit_wr_en_e[06] = ~dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[2];
|
2760 |
|
|
assign dva_fill_bit_wr_en_e[05] = ~dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[1];
|
2761 |
|
|
assign dva_fill_bit_wr_en_e[04] = ~dcache_fill_addr_e[5] & dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[0];
|
2762 |
|
|
|
2763 |
|
|
assign dva_fill_bit_wr_en_e[03] = ~dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[3];
|
2764 |
|
|
assign dva_fill_bit_wr_en_e[02] = ~dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[2];
|
2765 |
|
|
assign dva_fill_bit_wr_en_e[01] = ~dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[1];
|
2766 |
|
|
assign dva_fill_bit_wr_en_e[00] = ~dcache_fill_addr_e[5] & ~dcache_fill_addr_e[4] & lsu_dcache_fill_way_e[0];
|
2767 |
|
|
|
2768 |
|
|
wire [15:0] dva_bit_wr_en_e;
|
2769 |
|
|
assign dva_bit_wr_en_e[15:0] = dva_svld_e ? dva_snp_bit_wr_en_e[15:0] : dva_fill_bit_wr_en_e;
|
2770 |
|
|
|
2771 |
|
|
wire [4:0] dva_snp_addr_e_bf;
|
2772 |
|
|
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b4 (.a(dva_snp_addr_e[4]), .z(dva_snp_addr_e_bf[4]));
|
2773 |
|
|
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b3 (.a(dva_snp_addr_e[3]), .z(dva_snp_addr_e_bf[3]));
|
2774 |
|
|
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b2 (.a(dva_snp_addr_e[2]), .z(dva_snp_addr_e_bf[2]));
|
2775 |
|
|
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b1 (.a(dva_snp_addr_e[1]), .z(dva_snp_addr_e_bf[1]));
|
2776 |
|
|
bw_u1_buf_5x UZsize_dva_snp_addr_e_bf_b0 (.a(dva_snp_addr_e[0]), .z(dva_snp_addr_e_bf[0]));
|
2777 |
|
|
|
2778 |
|
|
assign dva_wr_adr_e[10:6] = dva_svld_e ? dva_snp_addr_e_bf[4:0] : dcache_fill_addr_e[10:6];
|
2779 |
|
|
|
2780 |
|
|
// should ldxa_data_vld be included ?
|
2781 |
|
|
|
2782 |
|
|
assign dfill_thread0 = ~lsu_dfill_tid_e[1] & ~lsu_dfill_tid_e[0] ;
|
2783 |
|
|
assign dfill_thread1 = ~lsu_dfill_tid_e[1] & lsu_dfill_tid_e[0] ;
|
2784 |
|
|
assign dfill_thread2 = lsu_dfill_tid_e[1] & ~lsu_dfill_tid_e[0] ;
|
2785 |
|
|
assign dfill_thread3 = lsu_dfill_tid_e[1] & lsu_dfill_tid_e[0] ;
|
2786 |
|
|
|
2787 |
|
|
assign l2fill_fpld_e = lsu_l2fill_fpld_e ;
|
2788 |
|
|
|
2789 |
|
|
//=========================================================================================
|
2790 |
|
|
// LD/ST COMPLETE SIGNAL
|
2791 |
|
|
//=========================================================================================
|
2792 |
|
|
|
2793 |
|
|
// Prefetch
|
2794 |
|
|
|
2795 |
|
|
wire pref_tlbmiss_g ;
|
2796 |
|
|
assign pref_tlbmiss_g =
|
2797 |
|
|
pref_inst_g &
|
2798 |
|
|
(~tlb_cam_hit_g | (tlb_cam_hit_g & tlb_pgnum[39])) // nop on tlbmiss or io access
|
2799 |
|
|
& lsu_inst_vld_w & ~dctl_flush_pipe_w ; // Bug 4318 bug6406/eco6619
|
2800 |
|
|
|
2801 |
|
|
//assign pref_tlbmiss_g = pref_inst_g & lsu_inst_vld_w & ~tlb_cam_hit_g ;
|
2802 |
|
|
wire [3:0] pref_tlbmiss_cmplt,pref_tlbmiss_cmplt_d1,pref_tlbmiss_cmplt_d2 ;
|
2803 |
|
|
assign pref_tlbmiss_cmplt[0] = pref_tlbmiss_g & thread0_g ;
|
2804 |
|
|
assign pref_tlbmiss_cmplt[1] = pref_tlbmiss_g & thread1_g ;
|
2805 |
|
|
assign pref_tlbmiss_cmplt[2] = pref_tlbmiss_g & thread2_g ;
|
2806 |
|
|
assign pref_tlbmiss_cmplt[3] = pref_tlbmiss_g & thread3_g ;
|
2807 |
|
|
|
2808 |
|
|
dff_s #(4) pfcmpl_stgd1 (
|
2809 |
|
|
.din (pref_tlbmiss_cmplt[3:0]),
|
2810 |
|
|
.q (pref_tlbmiss_cmplt_d1[3:0]),
|
2811 |
|
|
.clk (clk),
|
2812 |
|
|
.se (se), .si (), .so ()
|
2813 |
|
|
);
|
2814 |
|
|
|
2815 |
|
|
dff_s #(4) pfcmpl_stgd2 (
|
2816 |
|
|
.din (pref_tlbmiss_cmplt_d1[3:0]),
|
2817 |
|
|
.q (pref_tlbmiss_cmplt_d2[3:0]),
|
2818 |
|
|
.clk (clk),
|
2819 |
|
|
.se (se), .si (), .so ()
|
2820 |
|
|
);
|
2821 |
|
|
|
2822 |
|
|
// *** add diagnstc rd and prefetch(tlb-miss) signals. ***
|
2823 |
|
|
// *** add ifu asi ack.
|
2824 |
|
|
|
2825 |
|
|
// This equation is critical and needs to be optimized.
|
2826 |
|
|
wire [3:0] lsu_pcx_pref_issue;
|
2827 |
|
|
wire diag_wr_cmplt0,diag_wr_cmplt1,diag_wr_cmplt2,diag_wr_cmplt3;
|
2828 |
|
|
wire ldst_cmplt_late_0, ldst_cmplt_late_1 ;
|
2829 |
|
|
wire ldst_cmplt_late_2, ldst_cmplt_late_3 ;
|
2830 |
|
|
wire ldst_cmplt_late_0_d1, ldst_cmplt_late_1_d1 ;
|
2831 |
|
|
wire ldst_cmplt_late_2_d1, ldst_cmplt_late_3_d1 ;
|
2832 |
|
|
|
2833 |
|
|
assign ignore_fill = lmq_ldd_vld & ~ldd_in_dfq_out;
|
2834 |
|
|
|
2835 |
|
|
assign lsu_ifu_ldst_cmplt[0] =
|
2836 |
|
|
// * can be early or
|
2837 |
|
|
((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
|
2838 |
|
|
// * late signal and critical.
|
2839 |
|
|
// Can this be snapped earlier ?
|
2840 |
|
|
//(((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill)) //Bug 3624
|
2841 |
|
|
(((l2fill_vld_e & ~ignore_fill)) // 1st fill for ldd.
|
2842 |
|
|
& ~l2fill_fpld_e & ~lsu_cpx_pkt_atm_st_cmplt &
|
2843 |
|
|
~(lsu_cpx_pkt_ld_err[1] & lsu_nceen_d1[0]) & dfill_thread0) |
|
2844 |
|
|
intld_byp_cmplt[0] |
|
2845 |
|
|
// * early-or signals
|
2846 |
|
|
ldst_cmplt_late_0_d1 ;
|
2847 |
|
|
|
2848 |
|
|
wire atm_st_cmplt0 ;
|
2849 |
|
|
assign atm_st_cmplt0 = lsu_atm_st_cmplt_e & dfill_thread0 ;
|
2850 |
|
|
assign ldst_cmplt_late_0 =
|
2851 |
|
|
(atm_st_cmplt0 & ~pend_atm_ld_ue[0]) | // Bug 3624,4048
|
2852 |
|
|
bsync0_reset |
|
2853 |
|
|
lsu_intrpt_cmplt[0] |
|
2854 |
|
|
diag_wr_cmplt0 |
|
2855 |
|
|
// dc0_diagnstc_rd_w2 |
|
2856 |
|
|
ldxa_illgl_va_cmplt_d1[0] |
|
2857 |
|
|
pref_tlbmiss_cmplt_d2[0] |
|
2858 |
|
|
lsu_pcx_pref_issue[0];
|
2859 |
|
|
|
2860 |
|
|
|
2861 |
|
|
assign lsu_ifu_ldst_cmplt[1] =
|
2862 |
|
|
((stxa_internal_d2 & thread1_w3) | stxa_stall_wr_cmplt1_d1) |
|
2863 |
|
|
(((l2fill_vld_e & ~ignore_fill)) // // 1st fill for ldd
|
2864 |
|
|
& ~l2fill_fpld_e & ~lsu_cpx_pkt_atm_st_cmplt &
|
2865 |
|
|
~(lsu_cpx_pkt_ld_err[1] & lsu_nceen_d1[1]) & dfill_thread1) |
|
2866 |
|
|
intld_byp_cmplt[1] |
|
2867 |
|
|
ldst_cmplt_late_1_d1 ;
|
2868 |
|
|
|
2869 |
|
|
wire atm_st_cmplt1 ;
|
2870 |
|
|
assign atm_st_cmplt1 = lsu_atm_st_cmplt_e & dfill_thread1 ;
|
2871 |
|
|
assign ldst_cmplt_late_1 =
|
2872 |
|
|
(atm_st_cmplt1 & ~pend_atm_ld_ue[1]) | // Bug 3624,4048
|
2873 |
|
|
bsync1_reset |
|
2874 |
|
|
lsu_intrpt_cmplt[1] |
|
2875 |
|
|
diag_wr_cmplt1 |
|
2876 |
|
|
// dc1_diagnstc_rd_w2 |
|
2877 |
|
|
ldxa_illgl_va_cmplt_d1[1] |
|
2878 |
|
|
pref_tlbmiss_cmplt_d2[1] |
|
2879 |
|
|
lsu_pcx_pref_issue[1];
|
2880 |
|
|
|
2881 |
|
|
assign lsu_ifu_ldst_cmplt[2] =
|
2882 |
|
|
((stxa_internal_d2 & thread2_w3) | stxa_stall_wr_cmplt2_d1) |
|
2883 |
|
|
(((l2fill_vld_e & ~ignore_fill)) // 1st fill for ldd.
|
2884 |
|
|
& ~l2fill_fpld_e & ~lsu_cpx_pkt_atm_st_cmplt &
|
2885 |
|
|
~(lsu_cpx_pkt_ld_err[1] & lsu_nceen_d1[2]) & dfill_thread2) |
|
2886 |
|
|
intld_byp_cmplt[2] |
|
2887 |
|
|
ldst_cmplt_late_2_d1 ;
|
2888 |
|
|
|
2889 |
|
|
wire atm_st_cmplt2 ;
|
2890 |
|
|
assign atm_st_cmplt2 = lsu_atm_st_cmplt_e & dfill_thread2 ;
|
2891 |
|
|
assign ldst_cmplt_late_2 =
|
2892 |
|
|
(atm_st_cmplt2 & ~pend_atm_ld_ue[2]) | // Bug 3624,4048
|
2893 |
|
|
bsync2_reset |
|
2894 |
|
|
lsu_intrpt_cmplt[2] |
|
2895 |
|
|
diag_wr_cmplt2 |
|
2896 |
|
|
// dc2_diagnstc_rd_w2 |
|
2897 |
|
|
ldxa_illgl_va_cmplt_d1[2] |
|
2898 |
|
|
pref_tlbmiss_cmplt_d2[2] |
|
2899 |
|
|
lsu_pcx_pref_issue[2];
|
2900 |
|
|
|
2901 |
|
|
assign lsu_ifu_ldst_cmplt[3] =
|
2902 |
|
|
((stxa_internal_d2 & thread3_w3) | stxa_stall_wr_cmplt3_d1) |
|
2903 |
|
|
//(((l2fill_vld_e & atomic_st_cmplt) |
|
2904 |
|
|
(((l2fill_vld_e & ~ignore_fill)) // 1st fill for ldd.
|
2905 |
|
|
& ~l2fill_fpld_e & ~lsu_cpx_pkt_atm_st_cmplt &
|
2906 |
|
|
~(lsu_cpx_pkt_ld_err[1] & lsu_nceen_d1[3]) & dfill_thread3) |
|
2907 |
|
|
intld_byp_cmplt[3] |
|
2908 |
|
|
ldst_cmplt_late_3_d1 ;
|
2909 |
|
|
|
2910 |
|
|
wire atm_st_cmplt3 ;
|
2911 |
|
|
assign atm_st_cmplt3 = lsu_atm_st_cmplt_e & dfill_thread3 ;
|
2912 |
|
|
assign ldst_cmplt_late_3 =
|
2913 |
|
|
(atm_st_cmplt3 & ~pend_atm_ld_ue[3]) | // Bug 3624,4048
|
2914 |
|
|
bsync3_reset |
|
2915 |
|
|
lsu_intrpt_cmplt[3] |
|
2916 |
|
|
diag_wr_cmplt3 |
|
2917 |
|
|
// dc3_diagnstc_rd_w2 |
|
2918 |
|
|
ldxa_illgl_va_cmplt_d1[3] |
|
2919 |
|
|
pref_tlbmiss_cmplt_d2[3] |
|
2920 |
|
|
lsu_pcx_pref_issue[3];
|
2921 |
|
|
|
2922 |
|
|
dff_s #(4) ldstcmplt_d1 (
|
2923 |
|
|
.din ({ldst_cmplt_late_3,ldst_cmplt_late_2,ldst_cmplt_late_1,ldst_cmplt_late_0}),
|
2924 |
|
|
.q ({ldst_cmplt_late_3_d1,ldst_cmplt_late_2_d1,
|
2925 |
|
|
ldst_cmplt_late_1_d1,ldst_cmplt_late_0_d1}),
|
2926 |
|
|
.clk (clk),
|
2927 |
|
|
.se (se), .si (), .so ()
|
2928 |
|
|
);
|
2929 |
|
|
|
2930 |
|
|
//=========================================================================================
|
2931 |
|
|
// LD/ST MISS SIGNAL - IFU
|
2932 |
|
|
//=========================================================================================
|
2933 |
|
|
|
2934 |
|
|
// Switchout of internal asi ld
|
2935 |
|
|
// Do not switchout for tag-target,
|
2936 |
|
|
assign ldxa_swo_annul =
|
2937 |
|
|
(lsu_dctl_asi_state_m[7:4] == 4'h3) | // ldxa to 0x3X does not swo
|
2938 |
|
|
(((lsu_dctl_asi_state_m[7:0] == 8'h58) & // tag-target,tag-access,sfsr,sfar
|
2939 |
|
|
~((lsu_ldst_va_b7_b0_m[7:0] == 8'h38) | (lsu_ldst_va_b7_b0_m[7:0] == 8'h80))) | // wtcpt/pid
|
2940 |
|
|
(lsu_dctl_asi_state_m[7:0] == 8'h50)) |
|
2941 |
|
|
mmu_rd_only_asi_m ;
|
2942 |
|
|
|
2943 |
|
|
wire ldxa_internal_swo_m,ldxa_internal_swo_g ;
|
2944 |
|
|
assign ldxa_internal_swo_m = lda_internal_m & ~ldxa_swo_annul ;
|
2945 |
|
|
|
2946 |
|
|
// This represents *all* ld asi.
|
2947 |
|
|
wire asi_internal_ld_m,asi_internal_ld_g ;
|
2948 |
|
|
assign asi_internal_ld_m =
|
2949 |
|
|
asi_internal_m & ld_inst_vld_m & lsu_alt_space_m ;
|
2950 |
|
|
|
2951 |
|
|
dff_s #(2) ldaswo_stgg (
|
2952 |
|
|
.din ({ldxa_internal_swo_m,asi_internal_ld_m}),
|
2953 |
|
|
.q ({ldxa_internal_swo_g,asi_internal_ld_g}),
|
2954 |
|
|
.clk (clk),
|
2955 |
|
|
.se (se), .si (), .so ()
|
2956 |
|
|
);
|
2957 |
|
|
|
2958 |
|
|
wire common_ldst_miss_w ;
|
2959 |
|
|
assign common_ldst_miss_w =
|
2960 |
|
|
(~(cache_hit & (tlb_cam_hit_g | lsu_dtlb_bypass_g)) | // include miss in tlb;bypass
|
2961 |
|
|
~dcache_enable_g | //
|
2962 |
|
|
//endian_mispred_g | // endian mispredict
|
2963 |
|
|
ldd_force_l2access_g | // ifu to incorporate directly
|
2964 |
|
|
ncache_asild_rq_g ) & // bypass asi
|
2965 |
|
|
~asi_internal_ld_g ;
|
2966 |
|
|
|
2967 |
|
|
assign lsu_ifu_ldst_miss_w =
|
2968 |
|
|
(common_ldst_miss_w | // common between ifu and exu.
|
2969 |
|
|
// MMU_ASI : ifu must switch out early only for stores.
|
2970 |
|
|
ldxa_internal_swo_g)
|
2971 |
|
|
// ldxa_internal | // ifu incorporates directly
|
2972 |
|
|
// atomic_g | // ifu incorporates directly
|
2973 |
|
|
// ld_stb_hit_g | // late
|
2974 |
|
|
// stb_cam_hit) // ** rm once ifu uses late signal. **
|
2975 |
|
|
// dcache_rd_parity_error | // late
|
2976 |
|
|
// dtag_perror_g) & | // late
|
2977 |
|
|
& (lsu_inst_vld_w & ld_inst_vld_unflushed) ; // flush uptil m accounted for.
|
2978 |
|
|
// & ld_inst_vld_g ; // assume flush=1 clears ldst_miss=1
|
2979 |
|
|
// ~tte_data_perror_unc & // in flush
|
2980 |
|
|
// (ld_inst_vld_g & (~lsu_alt_space_g | (lsu_alt_space_g & recognized_asi_g))) |
|
2981 |
|
|
// ncache_asild_rq_g ; // asi ld requires bypass
|
2982 |
|
|
|
2983 |
|
|
|
2984 |
|
|
//timing fix
|
2985 |
|
|
wire lsu_ifu_dc_parity_error_w;
|
2986 |
|
|
assign lsu_ifu_dc_parity_error_w =
|
2987 |
|
|
(
|
2988 |
|
|
lsu_dcache_data_perror_g | // bug 4267
|
2989 |
|
|
lsu_dcache_tag_perror_g |
|
2990 |
|
|
endian_mispred_g | // endian mispredict ; mv'ed from ldst_miss
|
2991 |
|
|
tte_data_perror_unc_en) ;
|
2992 |
|
|
|
2993 |
|
|
/*
|
2994 |
|
|
wire lsu_ld_inst_vld_flush_w, lsu_ld_inst_vld_flush_w2;
|
2995 |
|
|
assign lsu_ld_inst_vld_flush_w = lsu_inst_vld_w & ld_inst_vld_unflushed & ~dctl_flush_pipe_w ;
|
2996 |
|
|
|
2997 |
|
|
|
2998 |
|
|
dff_s #(1) lsu_ld_inst_vld_flush_stgw2 (
|
2999 |
|
|
.din (lsu_ld_inst_vld_flush_w),
|
3000 |
|
|
.q (lsu_ld_inst_vld_flush_w2),
|
3001 |
|
|
.clk (clk),
|
3002 |
|
|
.se (se), .si (), .so ()
|
3003 |
|
|
);
|
3004 |
|
|
*/
|
3005 |
|
|
|
3006 |
|
|
wire lsu_ifu_dc_parity_error_w2_q;
|
3007 |
|
|
|
3008 |
|
|
dff_s #(1) lsu_ifu_dc_parity_error_stgw2 (
|
3009 |
|
|
.din (lsu_ifu_dc_parity_error_w),
|
3010 |
|
|
.q (lsu_ifu_dc_parity_error_w2_q),
|
3011 |
|
|
.clk (clk),
|
3012 |
|
|
.se (se), .si (), .so ()
|
3013 |
|
|
);
|
3014 |
|
|
|
3015 |
|
|
assign lsu_ifu_dc_parity_error_w2 = (lsu_ifu_dc_parity_error_w2_q | stb_cam_hit_w2) & ld_inst_vld_w2;
|
3016 |
|
|
|
3017 |
|
|
//=========================================================================================
|
3018 |
|
|
// LD/ST MISS SIGNAL - EXU
|
3019 |
|
|
//=========================================================================================
|
3020 |
|
|
|
3021 |
|
|
// for a diagnstc access to the cache, the if it misses in the cache, then
|
3022 |
|
|
// ldst_miss is asserted, preventing a write into the cache, but code is
|
3023 |
|
|
// allowed to continue executing.
|
3024 |
|
|
wire exu_ldst_miss_g_no_stb_cam_hit ;
|
3025 |
|
|
assign exu_ldst_miss_g_no_stb_cam_hit =
|
3026 |
|
|
(common_ldst_miss_w |
|
3027 |
|
|
ldxa_internal_swo_g |
|
3028 |
|
|
endian_mispred_g |
|
3029 |
|
|
atomic_g |
|
3030 |
|
|
lsu_dcache_data_perror_g |
|
3031 |
|
|
lsu_dcache_tag_perror_g |
|
3032 |
|
|
tte_data_perror_unc_en |
|
3033 |
|
|
pref_inst_g) & ld_inst_vld_unflushed & lsu_inst_vld_w ; // flush qual done in exu
|
3034 |
|
|
|
3035 |
|
|
|
3036 |
|
|
wire ld_inst_vld_no_flush_w, ld_inst_vld_no_flush_w2;
|
3037 |
|
|
assign ld_inst_vld_no_flush_w = ld_inst_vld_unflushed & lsu_inst_vld_w;
|
3038 |
|
|
|
3039 |
|
|
dff_s #(1) ld_inst_vld_no_flush_stgw2 (
|
3040 |
|
|
.din (ld_inst_vld_no_flush_w),
|
3041 |
|
|
.q (ld_inst_vld_no_flush_w2),
|
3042 |
|
|
.clk (clk),
|
3043 |
|
|
.se (se), .si (), .so ()
|
3044 |
|
|
);
|
3045 |
|
|
|
3046 |
|
|
wire lsu_exu_ldst_miss_w2_tmp;
|
3047 |
|
|
|
3048 |
|
|
dff_s #(1) exuldstmiss_stgw2 (
|
3049 |
|
|
.din (exu_ldst_miss_g_no_stb_cam_hit),
|
3050 |
|
|
.q (lsu_exu_ldst_miss_w2_tmp),
|
3051 |
|
|
.clk (clk),
|
3052 |
|
|
.se (se), .si (), .so ()
|
3053 |
|
|
);
|
3054 |
|
|
|
3055 |
|
|
assign lsu_exu_ldst_miss_w2 = (lsu_exu_ldst_miss_w2_tmp | stb_cam_hit_w2) & ld_inst_vld_no_flush_w2;
|
3056 |
|
|
|
3057 |
|
|
|
3058 |
|
|
wire lsu_ldst_miss_w2;
|
3059 |
|
|
assign lsu_ldst_miss_w2 = lsu_exu_ldst_miss_w2 ;
|
3060 |
|
|
|
3061 |
|
|
//=========================================================================================
|
3062 |
|
|
// RMO Store control data
|
3063 |
|
|
//=========================================================================================
|
3064 |
|
|
|
3065 |
|
|
assign lsu_st_rmo_m = (st_inst_vld_m & (binit_quad_asi_m | blk_asi_m) & lsu_alt_space_m) | blkst_m ;
|
3066 |
|
|
assign lsu_bst_in_pipe_m = (st_inst_vld_m & blk_asi_m & lsu_alt_space_m) ;
|
3067 |
|
|
|
3068 |
|
|
//=========================================================================================
|
3069 |
|
|
// ASI BUS
|
3070 |
|
|
//=========================================================================================
|
3071 |
|
|
|
3072 |
|
|
// *** This logic is now used by all long-latency asi operations on chip. ***
|
3073 |
|
|
|
3074 |
|
|
// Start with SDATA Reg for Streaming
|
3075 |
|
|
wire strm_asi, strm_asi_m ;
|
3076 |
|
|
assign strm_asi_m = (lsu_dctl_asi_state_m[7:0]==8'h40) ;
|
3077 |
|
|
|
3078 |
|
|
dff_s strm_stgg (
|
3079 |
|
|
.din (strm_asi_m),
|
3080 |
|
|
.q (strm_asi),
|
3081 |
|
|
.clk (clk),
|
3082 |
|
|
.se (se), .si (), .so ()
|
3083 |
|
|
);
|
3084 |
|
|
|
3085 |
|
|
assign stxa_stall_asi_g =
|
3086 |
|
|
strm_asi & ((ldst_va_g[7:0] == 8'h80)) ; // ma ctl
|
3087 |
|
|
/*strm_asi & ( (ldst_va_g[7:0] == 8'h18) | // streaming stxa to sdata
|
3088 |
|
|
(ldst_va_g[7:0] == 8'h00) | // stream ctl
|
3089 |
|
|
(ldst_va_g[7:0] == 8'h08) ) ; // ma ctl */
|
3090 |
|
|
|
3091 |
|
|
wire dtlb_wr_cmplt0, dtlb_wr_cmplt1;
|
3092 |
|
|
wire dtlb_wr_cmplt2, dtlb_wr_cmplt3;
|
3093 |
|
|
assign dtlb_wr_cmplt0 = demap_thread0 & lsu_dtlb_wr_vld_e ;
|
3094 |
|
|
assign dtlb_wr_cmplt1 = demap_thread1 & lsu_dtlb_wr_vld_e ;
|
3095 |
|
|
assign dtlb_wr_cmplt2 = demap_thread2 & lsu_dtlb_wr_vld_e ;
|
3096 |
|
|
assign dtlb_wr_cmplt3 = demap_thread3 & lsu_dtlb_wr_vld_e ;
|
3097 |
|
|
|
3098 |
|
|
dff_s dtlbw_stgd1 (
|
3099 |
|
|
.din (lsu_dtlb_wr_vld_e),
|
3100 |
|
|
.q (dtlb_wr_init_d1),
|
3101 |
|
|
.clk (clk),
|
3102 |
|
|
.se (se), .si (), .so ()
|
3103 |
|
|
);
|
3104 |
|
|
|
3105 |
|
|
dff_s dtlbw_stgd2 (
|
3106 |
|
|
.din (dtlb_wr_init_d1),
|
3107 |
|
|
.q (dtlb_wr_init_d2),
|
3108 |
|
|
.clk (clk),
|
3109 |
|
|
.se (se), .si (), .so ()
|
3110 |
|
|
);
|
3111 |
|
|
|
3112 |
|
|
dff_s dtlbw_stgd3 (
|
3113 |
|
|
.din (dtlb_wr_init_d2),
|
3114 |
|
|
.q (dtlb_wr_init_d3),
|
3115 |
|
|
.clk (clk),
|
3116 |
|
|
.se (se), .si (), .so ()
|
3117 |
|
|
);
|
3118 |
|
|
|
3119 |
|
|
wire dtlb_wr_init_d4 ;
|
3120 |
|
|
dff_s dtlbw_stgd4 (
|
3121 |
|
|
.din (dtlb_wr_init_d3),
|
3122 |
|
|
.q (dtlb_wr_init_d4),
|
3123 |
|
|
.clk (clk),
|
3124 |
|
|
.se (se), .si (), .so ()
|
3125 |
|
|
);
|
3126 |
|
|
|
3127 |
|
|
|
3128 |
|
|
|
3129 |
|
|
wire tlb_access_sel_thrd3_d1,tlb_access_sel_thrd2_d1;
|
3130 |
|
|
wire tlb_access_sel_thrd1_d1,tlb_access_sel_thrd0_d1 ;
|
3131 |
|
|
wire ifu_asi_store_cmplt_en, ifu_asi_store_cmplt_en_d1 ;
|
3132 |
|
|
assign stxa_stall_wr_cmplt0 = (spu_lsu_stxa_ack & spu_stxa_thread0) |
|
3133 |
|
|
(tlu_stxa_thread0_w2 & tlu_lsu_stxa_ack & ~dtlb_wr_init_d4) |
|
3134 |
|
|
(ifu_asi_store_cmplt_en_d1 & tlb_access_sel_thrd0_d1) |
|
3135 |
|
|
dtlb_wr_cmplt0 ;
|
3136 |
|
|
assign stxa_stall_wr_cmplt1 = (spu_lsu_stxa_ack & spu_stxa_thread1) |
|
3137 |
|
|
(tlu_stxa_thread1_w2 & tlu_lsu_stxa_ack & ~dtlb_wr_init_d4) |
|
3138 |
|
|
(ifu_asi_store_cmplt_en_d1 & tlb_access_sel_thrd1_d1) |
|
3139 |
|
|
dtlb_wr_cmplt1 ;
|
3140 |
|
|
assign stxa_stall_wr_cmplt2 = (spu_lsu_stxa_ack & spu_stxa_thread2) |
|
3141 |
|
|
(tlu_stxa_thread2_w2 & tlu_lsu_stxa_ack & ~dtlb_wr_init_d4) |
|
3142 |
|
|
(ifu_asi_store_cmplt_en_d1 & tlb_access_sel_thrd2_d1) |
|
3143 |
|
|
dtlb_wr_cmplt2 ;
|
3144 |
|
|
assign stxa_stall_wr_cmplt3 = (spu_lsu_stxa_ack & spu_stxa_thread3) |
|
3145 |
|
|
(tlu_stxa_thread3_w2 & tlu_lsu_stxa_ack & ~dtlb_wr_init_d4) |
|
3146 |
|
|
(ifu_asi_store_cmplt_en_d1 & tlb_access_sel_thrd3_d1) |
|
3147 |
|
|
dtlb_wr_cmplt3 ;
|
3148 |
|
|
|
3149 |
|
|
dff_s #(4) stxastall_stgd1 (
|
3150 |
|
|
.din ({stxa_stall_wr_cmplt3,stxa_stall_wr_cmplt2,
|
3151 |
|
|
stxa_stall_wr_cmplt1,stxa_stall_wr_cmplt0}),
|
3152 |
|
|
.q ({stxa_stall_wr_cmplt3_d1,stxa_stall_wr_cmplt2_d1,
|
3153 |
|
|
stxa_stall_wr_cmplt1_d1,stxa_stall_wr_cmplt0_d1}),
|
3154 |
|
|
.clk (clk),
|
3155 |
|
|
.se (se), .si (), .so ()
|
3156 |
|
|
);
|
3157 |
|
|
|
3158 |
|
|
|
3159 |
|
|
// enable speculates on inst not being flushed
|
3160 |
|
|
// Only dside diagnostic writes will be logged for long-latency action. dside diagnostic
|
3161 |
|
|
// reads are aligned to pipe.
|
3162 |
|
|
wire wr_dc_diag_asi_e, wr_dtagv_diag_asi_e ;
|
3163 |
|
|
|
3164 |
|
|
assign wr_dc_diag_asi_e = dc_diagnstc_asi_e & st_inst_vld_e ;
|
3165 |
|
|
assign wr_dtagv_diag_asi_e = dtagv_diagnstc_asi_e & st_inst_vld_e ;
|
3166 |
|
|
|
3167 |
|
|
assign tlb_access_en0_e =
|
3168 |
|
|
(tlb_lng_ltncy_asi_e | wr_dc_diag_asi_e | wr_dtagv_diag_asi_e | ifu_nontlb_asi_e)
|
3169 |
|
|
& thread0_e & alt_space_e ;
|
3170 |
|
|
assign tlb_access_en1_e =
|
3171 |
|
|
(tlb_lng_ltncy_asi_e | wr_dc_diag_asi_e | wr_dtagv_diag_asi_e | ifu_nontlb_asi_e)
|
3172 |
|
|
& thread1_e & alt_space_e ;
|
3173 |
|
|
assign tlb_access_en2_e =
|
3174 |
|
|
(tlb_lng_ltncy_asi_e | wr_dc_diag_asi_e | wr_dtagv_diag_asi_e | ifu_nontlb_asi_e)
|
3175 |
|
|
& thread2_e & alt_space_e ;
|
3176 |
|
|
assign tlb_access_en3_e =
|
3177 |
|
|
(tlb_lng_ltncy_asi_e | wr_dc_diag_asi_e | wr_dtagv_diag_asi_e | ifu_nontlb_asi_e)
|
3178 |
|
|
& thread3_e & alt_space_e ;
|
3179 |
|
|
|
3180 |
|
|
dff_s #(4) tlbac_stgm (
|
3181 |
|
|
.din ({tlb_access_en0_e,tlb_access_en1_e,tlb_access_en2_e,tlb_access_en3_e}),
|
3182 |
|
|
.q ({tlb_access_en0_tmp,tlb_access_en1_tmp,tlb_access_en2_tmp,tlb_access_en3_tmp}),
|
3183 |
|
|
.clk (clk),
|
3184 |
|
|
.se (se), .si (), .so ()
|
3185 |
|
|
);
|
3186 |
|
|
|
3187 |
|
|
wire ldst_vld_m = ld_inst_vld_m | st_inst_vld_m ;
|
3188 |
|
|
assign tlb_access_en0_m = tlb_access_en0_tmp & ldst_vld_m ;
|
3189 |
|
|
assign tlb_access_en1_m = tlb_access_en1_tmp & ldst_vld_m ;
|
3190 |
|
|
assign tlb_access_en2_m = tlb_access_en2_tmp & ldst_vld_m ;
|
3191 |
|
|
assign tlb_access_en3_m = tlb_access_en3_tmp & ldst_vld_m ;
|
3192 |
|
|
|
3193 |
|
|
dff_s #(4) tlbac_stgw (
|
3194 |
|
|
.din ({tlb_access_en0_m,tlb_access_en1_m,tlb_access_en2_m,tlb_access_en3_m}),
|
3195 |
|
|
.q ({tlb_access_en0_unflushed,tlb_access_en1_unflushed,tlb_access_en2_unflushed,tlb_access_en3_unflushed}),
|
3196 |
|
|
.clk (clk),
|
3197 |
|
|
.se (se), .si (), .so ()
|
3198 |
|
|
);
|
3199 |
|
|
|
3200 |
|
|
// Flush ld/st with as=42 belonging to lsu. bistctl and ldiag
|
3201 |
|
|
|
3202 |
|
|
assign tlb_access_en0_g = tlb_access_en0_unflushed & lsu_inst_vld_w & ~(dctl_early_flush_w | ifu_asi42_flush_g) ;
|
3203 |
|
|
//assign tlb_access_en0_g = tlb_access_en0_unflushed & lsu_inst_vld_w & ~(dctl_flush_pipe_w | ifu_asi42_flush_g) ;
|
3204 |
|
|
assign tlb_access_en1_g = tlb_access_en1_unflushed & lsu_inst_vld_w & ~(dctl_early_flush_w | ifu_asi42_flush_g) ;
|
3205 |
|
|
assign tlb_access_en2_g = tlb_access_en2_unflushed & lsu_inst_vld_w & ~(dctl_early_flush_w | ifu_asi42_flush_g) ;
|
3206 |
|
|
assign tlb_access_en3_g = tlb_access_en3_unflushed & lsu_inst_vld_w & ~(dctl_early_flush_w | ifu_asi42_flush_g) ;
|
3207 |
|
|
|
3208 |
|
|
assign diag_wr_cmplt0 = lsu_diagnstc_wr_src_sel_e & tlb_access_sel_thrd0_d1 ;
|
3209 |
|
|
assign diag_wr_cmplt1 = lsu_diagnstc_wr_src_sel_e & tlb_access_sel_thrd1_d1 ;
|
3210 |
|
|
assign diag_wr_cmplt2 = lsu_diagnstc_wr_src_sel_e & tlb_access_sel_thrd2_d1 ;
|
3211 |
|
|
assign diag_wr_cmplt3 = lsu_diagnstc_wr_src_sel_e & tlb_access_sel_thrd3_d1 ;
|
3212 |
|
|
|
3213 |
|
|
wire ifu_tlb_rd_cmplt0,ifu_tlb_rd_cmplt1,ifu_tlb_rd_cmplt2,ifu_tlb_rd_cmplt3 ;
|
3214 |
|
|
wire st_sqsh_m, ifu_asi_ack_d1 ;
|
3215 |
|
|
assign ifu_tlb_rd_cmplt0 = (ifu_ldxa_thread0_w2 & ifu_lsu_ldxa_data_vld_w2 & ~ifu_nontlb0_asi) ;
|
3216 |
|
|
assign ifu_tlb_rd_cmplt1 = (ifu_ldxa_thread1_w2 & ifu_lsu_ldxa_data_vld_w2 & ~ifu_nontlb1_asi) ;
|
3217 |
|
|
assign ifu_tlb_rd_cmplt2 = (ifu_ldxa_thread2_w2 & ifu_lsu_ldxa_data_vld_w2 & ~ifu_nontlb2_asi) ;
|
3218 |
|
|
assign ifu_tlb_rd_cmplt3 = (ifu_ldxa_thread3_w2 & ifu_lsu_ldxa_data_vld_w2 & ~ifu_nontlb3_asi) ;
|
3219 |
|
|
|
3220 |
|
|
// stxa ack will share tid with ldxa
|
3221 |
|
|
// This should be qualified with inst_vld_w also !!!
|
3222 |
|
|
// ldxa_data_vld needs to be removed once full interface in !!!
|
3223 |
|
|
assign tlb_access_rst0 = reset |
|
3224 |
|
|
(tlu_ldxa_thread0_w2 & tlu_lsu_ldxa_async_data_vld) |
|
3225 |
|
|
(tlu_stxa_thread0_w2 & tlu_lsu_stxa_ack) |
|
3226 |
|
|
(ifu_tlb_rd_cmplt0) |
|
3227 |
|
|
(ifu_stxa_thread0_w2 & ifu_lsu_asi_ack) |
|
3228 |
|
|
diag_wr_cmplt0 ;
|
3229 |
|
|
assign tlb_access_rst1 = reset |
|
3230 |
|
|
(tlu_ldxa_thread1_w2 & tlu_lsu_ldxa_async_data_vld) |
|
3231 |
|
|
(tlu_stxa_thread1_w2 & tlu_lsu_stxa_ack) |
|
3232 |
|
|
(ifu_tlb_rd_cmplt1) |
|
3233 |
|
|
(ifu_stxa_thread1_w2 & ifu_lsu_asi_ack) |
|
3234 |
|
|
diag_wr_cmplt1 ;
|
3235 |
|
|
assign tlb_access_rst2 = reset |
|
3236 |
|
|
(tlu_ldxa_thread2_w2 & tlu_lsu_ldxa_async_data_vld) |
|
3237 |
|
|
(tlu_stxa_thread2_w2 & tlu_lsu_stxa_ack) |
|
3238 |
|
|
(ifu_tlb_rd_cmplt2) |
|
3239 |
|
|
(ifu_stxa_thread2_w2 & ifu_lsu_asi_ack) |
|
3240 |
|
|
diag_wr_cmplt2 ;
|
3241 |
|
|
assign tlb_access_rst3 = reset |
|
3242 |
|
|
(tlu_ldxa_thread3_w2 & tlu_lsu_ldxa_async_data_vld) |
|
3243 |
|
|
(tlu_stxa_thread3_w2 & tlu_lsu_stxa_ack) |
|
3244 |
|
|
(ifu_tlb_rd_cmplt3) |
|
3245 |
|
|
(ifu_stxa_thread3_w2 & ifu_lsu_asi_ack) |
|
3246 |
|
|
diag_wr_cmplt3 ;
|
3247 |
|
|
|
3248 |
|
|
|
3249 |
|
|
// tlb_ld_inst* and tlb_st_inst* are generically used to indicate a read or write.
|
3250 |
|
|
// Thread 0
|
3251 |
|
|
|
3252 |
|
|
dffre_s #(2) asiv_thrd0 (
|
3253 |
|
|
.din ({ld_inst_vld_g,st_inst_vld_g}),
|
3254 |
|
|
.q ({tlb_ld_inst0,tlb_st_inst0}),
|
3255 |
|
|
.rst (tlb_access_rst0), .en (tlb_access_en0_g),
|
3256 |
|
|
.clk (clk),
|
3257 |
|
|
.se (se), .si (), .so ()
|
3258 |
|
|
);
|
3259 |
|
|
|
3260 |
|
|
dffe_s #(3) asiv_thrd0_sec (
|
3261 |
|
|
.din ({dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,ifu_nontlb_asi_g}),
|
3262 |
|
|
.q ({dc0_diagnstc_asi,dtagv0_diagnstc_asi,ifu_nontlb0_asi}),
|
3263 |
|
|
.en (tlb_access_en0_g),
|
3264 |
|
|
.clk (clk),
|
3265 |
|
|
.se (se), .si (), .so ()
|
3266 |
|
|
);
|
3267 |
|
|
|
3268 |
|
|
assign nontlb_asi0 = dc0_diagnstc_asi | dtagv0_diagnstc_asi | ifu_nontlb0_asi ;
|
3269 |
|
|
|
3270 |
|
|
// Thread 1
|
3271 |
|
|
|
3272 |
|
|
dffre_s #(2) asiv_thrd1 (
|
3273 |
|
|
.din ({ld_inst_vld_g,st_inst_vld_g}),
|
3274 |
|
|
.q ({tlb_ld_inst1,tlb_st_inst1}),
|
3275 |
|
|
.rst (tlb_access_rst1), .en (tlb_access_en1_g),
|
3276 |
|
|
.clk (clk),
|
3277 |
|
|
.se (se), .si (), .so ()
|
3278 |
|
|
);
|
3279 |
|
|
|
3280 |
|
|
dffe_s #(3) asiv_thrd1_sec (
|
3281 |
|
|
.din ({dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,ifu_nontlb_asi_g}),
|
3282 |
|
|
.q ({dc1_diagnstc_asi,dtagv1_diagnstc_asi,ifu_nontlb1_asi}),
|
3283 |
|
|
.en (tlb_access_en1_g),
|
3284 |
|
|
.clk (clk),
|
3285 |
|
|
.se (se), .si (), .so ()
|
3286 |
|
|
);
|
3287 |
|
|
|
3288 |
|
|
assign nontlb_asi1 = dc1_diagnstc_asi | dtagv1_diagnstc_asi | ifu_nontlb1_asi ;
|
3289 |
|
|
|
3290 |
|
|
// Thread 2
|
3291 |
|
|
|
3292 |
|
|
dffre_s #(2) asiv_thrd2 (
|
3293 |
|
|
.din ({ld_inst_vld_g,st_inst_vld_g}),
|
3294 |
|
|
.q ({tlb_ld_inst2,tlb_st_inst2}),
|
3295 |
|
|
.rst (tlb_access_rst2), .en (tlb_access_en2_g),
|
3296 |
|
|
.clk (clk),
|
3297 |
|
|
.se (se), .si (), .so ()
|
3298 |
|
|
);
|
3299 |
|
|
|
3300 |
|
|
dffe_s #(3) asiv_thrd2_sec (
|
3301 |
|
|
.din ({dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,ifu_nontlb_asi_g}),
|
3302 |
|
|
.q ({dc2_diagnstc_asi,dtagv2_diagnstc_asi,ifu_nontlb2_asi}),
|
3303 |
|
|
.en (tlb_access_en2_g),
|
3304 |
|
|
.clk (clk),
|
3305 |
|
|
.se (se), .si (), .so ()
|
3306 |
|
|
);
|
3307 |
|
|
|
3308 |
|
|
assign nontlb_asi2 = dc2_diagnstc_asi | dtagv2_diagnstc_asi | ifu_nontlb2_asi ;
|
3309 |
|
|
|
3310 |
|
|
// Thread 3
|
3311 |
|
|
|
3312 |
|
|
dffre_s #(2) asiv_thrd3 (
|
3313 |
|
|
.din ({ld_inst_vld_g,st_inst_vld_g}),
|
3314 |
|
|
.q ({tlb_ld_inst3,tlb_st_inst3}),
|
3315 |
|
|
.rst (tlb_access_rst3), .en (tlb_access_en3_g),
|
3316 |
|
|
.clk (clk),
|
3317 |
|
|
.se (se), .si (), .so ()
|
3318 |
|
|
);
|
3319 |
|
|
|
3320 |
|
|
dffe_s #(3) asiv_thrd3_sec (
|
3321 |
|
|
.din ({dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,ifu_nontlb_asi_g}),
|
3322 |
|
|
.q ({dc3_diagnstc_asi,dtagv3_diagnstc_asi,ifu_nontlb3_asi}),
|
3323 |
|
|
.en (tlb_access_en3_g),
|
3324 |
|
|
.clk (clk),
|
3325 |
|
|
.se (se), .si (), .so ()
|
3326 |
|
|
);
|
3327 |
|
|
|
3328 |
|
|
assign nontlb_asi3 = dc3_diagnstc_asi | dtagv3_diagnstc_asi | ifu_nontlb3_asi ;
|
3329 |
|
|
|
3330 |
|
|
//---
|
3331 |
|
|
// Prioritization of threaded events from asi queue.
|
3332 |
|
|
// - It is not expected that a significant bias will exist in selecting
|
3333 |
|
|
// 1 of 4 possible events from the asi queue because of the low frequency
|
3334 |
|
|
// of such events. However, to bulletproof we will prioritize the events
|
3335 |
|
|
// in a fifo manner.
|
3336 |
|
|
//---
|
3337 |
|
|
|
3338 |
|
|
// Control :
|
3339 |
|
|
|
3340 |
|
|
wire [3:0] fifo_top ;
|
3341 |
|
|
wire asi_fifo0_vld,asi_fifo1_vld,asi_fifo2_vld,asi_fifo3_vld;
|
3342 |
|
|
|
3343 |
|
|
assign fifo_top[0] = ~asi_fifo0_vld ;
|
3344 |
|
|
assign fifo_top[1] = ~asi_fifo1_vld & asi_fifo0_vld ;
|
3345 |
|
|
assign fifo_top[2] = ~asi_fifo2_vld & asi_fifo1_vld & asi_fifo0_vld ;
|
3346 |
|
|
assign fifo_top[3] = ~asi_fifo3_vld & asi_fifo2_vld & asi_fifo1_vld & asi_fifo0_vld ;
|
3347 |
|
|
|
3348 |
|
|
// Check for timing on flush.
|
3349 |
|
|
// Do not confuse thread# with fifo entry#.
|
3350 |
|
|
wire fifo_wr, fifo_shift ;
|
3351 |
|
|
assign fifo_wr =
|
3352 |
|
|
tlb_access_en0_g | tlb_access_en1_g | tlb_access_en2_g | tlb_access_en3_g ;
|
3353 |
|
|
assign fifo_shift =
|
3354 |
|
|
tlb_access_rst0 | tlb_access_rst1 | tlb_access_rst2 | tlb_access_rst3 ;
|
3355 |
|
|
|
3356 |
|
|
wire [3:0] fifo_top_wr ;
|
3357 |
|
|
assign fifo_top_wr[0] = fifo_top[0] & fifo_wr ;
|
3358 |
|
|
assign fifo_top_wr[1] = fifo_top[1] & fifo_wr ;
|
3359 |
|
|
assign fifo_top_wr[2] = fifo_top[2] & fifo_wr ;
|
3360 |
|
|
assign fifo_top_wr[3] = fifo_top[3] & fifo_wr ;
|
3361 |
|
|
|
3362 |
|
|
// Matrix for Data Selection.
|
3363 |
|
|
// shift | wr | din for entry
|
3364 |
|
|
// 0 0 na
|
3365 |
|
|
// 0 1 thrid_g
|
3366 |
|
|
// 1 0 q
|
3367 |
|
|
// 1 1 q if top is not 1 above
|
3368 |
|
|
// 1 1 thrid_g if top is 1 above
|
3369 |
|
|
|
3370 |
|
|
// shift writeable entry into correct position, if exists.
|
3371 |
|
|
wire asi_fifo0_sel,asi_fifo1_sel,asi_fifo2_sel ;
|
3372 |
|
|
assign asi_fifo0_sel = fifo_shift ? fifo_top_wr[1] : fifo_top_wr[0] ;
|
3373 |
|
|
assign asi_fifo1_sel = fifo_shift ? fifo_top_wr[2] : fifo_top_wr[1] ;
|
3374 |
|
|
assign asi_fifo2_sel = fifo_shift ? fifo_top_wr[3] : fifo_top_wr[2] ;
|
3375 |
|
|
|
3376 |
|
|
wire [1:0] asi_fifo3_din,asi_fifo2_din,asi_fifo1_din,asi_fifo0_din ;
|
3377 |
|
|
wire [1:0] asi_fifo3_q,asi_fifo2_q,asi_fifo1_q,asi_fifo0_q ;
|
3378 |
|
|
assign asi_fifo0_din[1:0] = asi_fifo0_sel ? thrid_g[1:0] : asi_fifo1_q[1:0] ;
|
3379 |
|
|
assign asi_fifo1_din[1:0] = asi_fifo1_sel ? thrid_g[1:0] : asi_fifo2_q[1:0] ;
|
3380 |
|
|
assign asi_fifo2_din[1:0] = asi_fifo2_sel ? thrid_g[1:0] : asi_fifo3_q[1:0] ;
|
3381 |
|
|
assign asi_fifo3_din[1:0] = thrid_g[1:0] ; // can never shift into.
|
3382 |
|
|
|
3383 |
|
|
// Matrix for Enable
|
3384 |
|
|
// shift | wr | Entry Written ?
|
3385 |
|
|
// 0 0 0
|
3386 |
|
|
// 0 1 if top
|
3387 |
|
|
// 1 0 if entry+1 is vld
|
3388 |
|
|
// 1 1 if entry itself is vld => as is.
|
3389 |
|
|
|
3390 |
|
|
wire wr_not_sh,sh_not_wr,wr_and_sh ;
|
3391 |
|
|
assign wr_not_sh = fifo_wr & ~fifo_shift ; // write not shift
|
3392 |
|
|
assign sh_not_wr = ~fifo_wr & fifo_shift ; // shift not write
|
3393 |
|
|
assign wr_and_sh = fifo_wr & fifo_shift ; // shift and write
|
3394 |
|
|
|
3395 |
|
|
wire asi_fifo0_vin,asi_fifo1_vin,asi_fifo2_vin,asi_fifo3_vin ;
|
3396 |
|
|
assign asi_fifo0_vin =
|
3397 |
|
|
(wr_not_sh & fifo_top[0]) |
|
3398 |
|
|
(sh_not_wr & asi_fifo1_vld) |
|
3399 |
|
|
(wr_and_sh & asi_fifo0_vld) ;
|
3400 |
|
|
assign asi_fifo1_vin =
|
3401 |
|
|
(wr_not_sh & fifo_top[1]) |
|
3402 |
|
|
(sh_not_wr & asi_fifo2_vld) |
|
3403 |
|
|
(wr_and_sh & asi_fifo1_vld) ;
|
3404 |
|
|
assign asi_fifo2_vin =
|
3405 |
|
|
(wr_not_sh & fifo_top[2]) |
|
3406 |
|
|
(sh_not_wr & asi_fifo3_vld) |
|
3407 |
|
|
(wr_and_sh & asi_fifo2_vld) ;
|
3408 |
|
|
assign asi_fifo3_vin =
|
3409 |
|
|
(wr_not_sh & fifo_top[3]) |
|
3410 |
|
|
(wr_and_sh & asi_fifo3_vld) ;
|
3411 |
|
|
|
3412 |
|
|
wire asi_fifo0_en,asi_fifo1_en,asi_fifo2_en,asi_fifo3_en ;
|
3413 |
|
|
assign asi_fifo0_en = (fifo_wr & fifo_top[0]) | fifo_shift ;
|
3414 |
|
|
assign asi_fifo1_en = (fifo_wr & fifo_top[1]) | fifo_shift ;
|
3415 |
|
|
assign asi_fifo2_en = (fifo_wr & fifo_top[2]) | fifo_shift ;
|
3416 |
|
|
assign asi_fifo3_en = (fifo_wr & fifo_top[3]) | fifo_shift ;
|
3417 |
|
|
|
3418 |
|
|
wire asi_fifo3_rst,asi_fifo2_rst,asi_fifo1_rst,asi_fifo0_rst ;
|
3419 |
|
|
assign asi_fifo0_rst = reset ;
|
3420 |
|
|
assign asi_fifo1_rst = reset ;
|
3421 |
|
|
assign asi_fifo2_rst = reset ;
|
3422 |
|
|
assign asi_fifo3_rst = reset ;
|
3423 |
|
|
|
3424 |
|
|
// Datapath :
|
3425 |
|
|
// fifo entry 0 is earliest. fifo entry 3 is latest.
|
3426 |
|
|
dffe_s #(2) asiq_fifo_0 (
|
3427 |
|
|
.din (asi_fifo0_din[1:0]),
|
3428 |
|
|
.q (asi_fifo0_q[1:0]),
|
3429 |
|
|
.en (asi_fifo0_en),
|
3430 |
|
|
.clk (clk),
|
3431 |
|
|
.se (se), .si (), .so ()
|
3432 |
|
|
);
|
3433 |
|
|
|
3434 |
|
|
dffre_s asiqv_fifo_0 (
|
3435 |
|
|
.din (asi_fifo0_vin),
|
3436 |
|
|
.q (asi_fifo0_vld),
|
3437 |
|
|
.en (asi_fifo0_en), .rst (asi_fifo0_rst),
|
3438 |
|
|
.clk (clk),
|
3439 |
|
|
.se (se), .si (), .so ()
|
3440 |
|
|
);
|
3441 |
|
|
|
3442 |
|
|
wire asi_sel_thrd3,asi_sel_thrd2,asi_sel_thrd1,asi_sel_thrd0;
|
3443 |
|
|
assign asi_sel_thrd0 = ~asi_fifo0_q[1] & ~asi_fifo0_q[0] & (tlb_ld_inst0 | tlb_st_inst0) ;
|
3444 |
|
|
assign asi_sel_thrd1 = ~asi_fifo0_q[1] & asi_fifo0_q[0] & (tlb_ld_inst1 | tlb_st_inst1) ;
|
3445 |
|
|
assign asi_sel_thrd2 = asi_fifo0_q[1] & ~asi_fifo0_q[0] & (tlb_ld_inst2 | tlb_st_inst2) ;
|
3446 |
|
|
assign asi_sel_thrd3 = asi_fifo0_q[1] & asi_fifo0_q[0] & (tlb_ld_inst3 | tlb_st_inst3) ;
|
3447 |
|
|
|
3448 |
|
|
dffe_s #(2) asiq_fifo_1 (
|
3449 |
|
|
.din (asi_fifo1_din[1:0]),
|
3450 |
|
|
.q (asi_fifo1_q[1:0]),
|
3451 |
|
|
.en (asi_fifo1_en),
|
3452 |
|
|
.clk (clk),
|
3453 |
|
|
.se (se), .si (), .so ()
|
3454 |
|
|
);
|
3455 |
|
|
|
3456 |
|
|
dffre_s asiqv_fifo_1 (
|
3457 |
|
|
.din (asi_fifo1_vin),
|
3458 |
|
|
.q (asi_fifo1_vld),
|
3459 |
|
|
.en (asi_fifo1_en), .rst (asi_fifo1_rst),
|
3460 |
|
|
.clk (clk),
|
3461 |
|
|
.se (se), .si (), .so ()
|
3462 |
|
|
);
|
3463 |
|
|
|
3464 |
|
|
dffe_s #(2) asiq_fifo_2 (
|
3465 |
|
|
.din (asi_fifo2_din[1:0]),
|
3466 |
|
|
.q (asi_fifo2_q[1:0]),
|
3467 |
|
|
.en (asi_fifo2_en),
|
3468 |
|
|
.clk (clk),
|
3469 |
|
|
.se (se), .si (), .so ()
|
3470 |
|
|
);
|
3471 |
|
|
|
3472 |
|
|
dffre_s asiqv_fifo_2 (
|
3473 |
|
|
.din (asi_fifo2_vin),
|
3474 |
|
|
.q (asi_fifo2_vld),
|
3475 |
|
|
.en (asi_fifo2_en), .rst (asi_fifo2_rst),
|
3476 |
|
|
.clk (clk),
|
3477 |
|
|
.se (se), .si (), .so ()
|
3478 |
|
|
);
|
3479 |
|
|
|
3480 |
|
|
dffe_s #(2) asiq_fifo_3 (
|
3481 |
|
|
.din (asi_fifo3_din[1:0]),
|
3482 |
|
|
.q (asi_fifo3_q[1:0]),
|
3483 |
|
|
.en (asi_fifo3_en),
|
3484 |
|
|
.clk (clk),
|
3485 |
|
|
.se (se), .si (), .so ()
|
3486 |
|
|
);
|
3487 |
|
|
|
3488 |
|
|
dffre_s asiqv_fifo_3 (
|
3489 |
|
|
.din (asi_fifo3_vin),
|
3490 |
|
|
.q (asi_fifo3_vld),
|
3491 |
|
|
.en (asi_fifo3_en), .rst (asi_fifo3_rst),
|
3492 |
|
|
.clk (clk),
|
3493 |
|
|
.se (se), .si (), .so ()
|
3494 |
|
|
);
|
3495 |
|
|
|
3496 |
|
|
//---
|
3497 |
|
|
|
3498 |
|
|
assign tlb_access_initiated =
|
3499 |
|
|
((tlb_access_sel_thrd0 & ~tlb_access_rst0) |
|
3500 |
|
|
(tlb_access_sel_thrd1 & ~tlb_access_rst1) |
|
3501 |
|
|
(tlb_access_sel_thrd2 & ~tlb_access_rst2) |
|
3502 |
|
|
(tlb_access_sel_thrd3 & ~tlb_access_rst3)) & ~tlb_access_pending ;
|
3503 |
|
|
|
3504 |
|
|
|
3505 |
|
|
wire tlb_blocking_rst ;
|
3506 |
|
|
assign tlb_blocking_rst = reset |
|
3507 |
|
|
tlu_lsu_stxa_ack | tlu_lsu_ldxa_async_data_vld |
|
3508 |
|
|
ifu_tlb_rd_cmplt0 | ifu_tlb_rd_cmplt1 |
|
3509 |
|
|
ifu_tlb_rd_cmplt2 | ifu_tlb_rd_cmplt3 |
|
3510 |
|
|
ifu_lsu_asi_ack |
|
3511 |
|
|
lsu_diagnstc_wr_src_sel_e;
|
3512 |
|
|
|
3513 |
|
|
|
3514 |
|
|
// MMU/IFU/DIAG Action is pending
|
3515 |
|
|
dffre_s #(1) tlbpnd (
|
3516 |
|
|
.din (tlb_access_initiated),
|
3517 |
|
|
.q (tlb_access_pending),
|
3518 |
|
|
.rst (tlb_blocking_rst), .en (tlb_access_initiated),
|
3519 |
|
|
.clk (clk),
|
3520 |
|
|
.se (se), .si (), .so ()
|
3521 |
|
|
);
|
3522 |
|
|
|
3523 |
|
|
/*wire asi_pend0,asi_pend1,asi_pend2,asi_pend3 ;
|
3524 |
|
|
dffre_s #(4) asithrdpnd (
|
3525 |
|
|
.din ({tlb_access_sel_thrd3,tlb_access_sel_thrd2,
|
3526 |
|
|
tlb_access_sel_thrd1,tlb_access_sel_thrd0}),
|
3527 |
|
|
.q ({asi_pend3,asi_pend2,asi_pend1,asi_pend0}),
|
3528 |
|
|
.rst (tlb_blocking_rst), .en (tlb_access_initiated),
|
3529 |
|
|
.clk (clk),
|
3530 |
|
|
.se (se), .si (), .so ()
|
3531 |
|
|
);
|
3532 |
|
|
|
3533 |
|
|
wire asi_pend_non_thrd0 ;
|
3534 |
|
|
assign asi_pend_non_thrd0 = asi_pend1 | asi_pend2 | asi_pend3 ;
|
3535 |
|
|
wire asi_pend_non_thrd1 ;
|
3536 |
|
|
assign asi_pend_non_thrd1 = asi_pend0 | asi_pend2 | asi_pend3 ;
|
3537 |
|
|
wire asi_pend_non_thrd2 ;
|
3538 |
|
|
assign asi_pend_non_thrd2 = asi_pend0 | asi_pend1 | asi_pend3 ;
|
3539 |
|
|
wire asi_pend_non_thrd3 ;
|
3540 |
|
|
assign asi_pend_non_thrd3 = asi_pend0 | asi_pend1 | asi_pend2 ; */
|
3541 |
|
|
|
3542 |
|
|
// Would like to remove st_inst_vld_m. This is however required to
|
3543 |
|
|
// source rs3 data to tlu/mmu. Send rs3_data directly !!!
|
3544 |
|
|
|
3545 |
|
|
wire diag_wr_src, diag_wr_src_d1, diag_wr_src_d2 ;
|
3546 |
|
|
|
3547 |
|
|
assign tlb_access_blocked =
|
3548 |
|
|
(tlb_access_pending & ~ifu_asi_vld_d1 & ~diag_wr_src_d1) |
|
3549 |
|
|
(st_sqsh_m & ~(ifu_asi_vld_d1 & ~ifu_asi_ack_d1) & ~diag_wr_src_d1) ; // Bug 4875
|
3550 |
|
|
//(st_inst_vld_m & ~lsu_ifu_asi_vld_d1 & ~diag_wr_src_d1) ;
|
3551 |
|
|
|
3552 |
|
|
// fixed priority. tlb accesses are issued speculatively in the m-stage and are
|
3553 |
|
|
// Change priority to round-robin !!!
|
3554 |
|
|
// flushed in the g-stage in the tlu if necessary.
|
3555 |
|
|
// diagnstc writes will block for cache/tag access.
|
3556 |
|
|
// This means that access can be blocked if a st is
|
3557 |
|
|
// in the m-stage or a memref in the d stage. (!!!)
|
3558 |
|
|
// In this case, it is better to stage a different
|
3559 |
|
|
// bus for rs3 data.
|
3560 |
|
|
|
3561 |
|
|
// Note : Selection Process.
|
3562 |
|
|
// 1. Priority Encoded selection if no access pending.
|
3563 |
|
|
// This may have to be changed to prevent bias towards a
|
3564 |
|
|
// single thread.
|
3565 |
|
|
// 2. Once thread is selected :
|
3566 |
|
|
// a. generate single pulse - mmu. tlb_access_blocked
|
3567 |
|
|
// used for this purpose.
|
3568 |
|
|
// b. generate window - ifu/diag. To prevent spurious change
|
3569 |
|
|
// in selects, asi_pend_non_thrdx and tlb_access_pending
|
3570 |
|
|
// qual. is required.
|
3571 |
|
|
|
3572 |
|
|
|
3573 |
|
|
assign tlb_access_sel_thrd0 = ~rst_tri_en &
|
3574 |
|
|
asi_sel_thrd0 & ~tlb_access_blocked ;
|
3575 |
|
|
assign tlb_access_sel_thrd1 = ~rst_tri_en &
|
3576 |
|
|
asi_sel_thrd1 & ~tlb_access_blocked ;
|
3577 |
|
|
assign tlb_access_sel_thrd2 = ~rst_tri_en &
|
3578 |
|
|
asi_sel_thrd2 & ~tlb_access_blocked ;
|
3579 |
|
|
assign tlb_access_sel_thrd3 = ~rst_tri_en &
|
3580 |
|
|
asi_sel_thrd3 & ~tlb_access_blocked ;
|
3581 |
|
|
|
3582 |
|
|
//assign tlb_access_sel_thrd0 = ~rst_tri_en & (
|
3583 |
|
|
// (tlb_ld_inst0 | tlb_st_inst0) & ~tlb_access_blocked &
|
3584 |
|
|
// ~asi_pend_non_thrd0 );
|
3585 |
|
|
//assign tlb_access_sel_thrd1 = ~rst_tri_en & (
|
3586 |
|
|
// (tlb_ld_inst1 | tlb_st_inst1) &
|
3587 |
|
|
// ~(((tlb_ld_inst0 | tlb_st_inst0) & ~tlb_access_pending) | tlb_access_blocked) &
|
3588 |
|
|
// ~asi_pend_non_thrd1 );
|
3589 |
|
|
//assign tlb_access_sel_thrd2 = ~rst_tri_en & (
|
3590 |
|
|
// (tlb_ld_inst2 | tlb_st_inst2) &
|
3591 |
|
|
// ~(((tlb_ld_inst0 | tlb_st_inst0 | tlb_ld_inst1 | tlb_st_inst1) & ~tlb_access_pending)
|
3592 |
|
|
// | tlb_access_blocked) &
|
3593 |
|
|
// ~asi_pend_non_thrd2 );
|
3594 |
|
|
//assign tlb_access_sel_thrd3 = ~rst_tri_en & (
|
3595 |
|
|
// (tlb_ld_inst3 | tlb_st_inst3) &
|
3596 |
|
|
// ~(((tlb_ld_inst0 | tlb_st_inst0 | tlb_ld_inst1 | tlb_st_inst1 |
|
3597 |
|
|
// tlb_ld_inst2 | tlb_st_inst2) & ~tlb_access_pending) | tlb_access_blocked) &
|
3598 |
|
|
// ~asi_pend_non_thrd3 );
|
3599 |
|
|
|
3600 |
|
|
dff_s #(4) selt_stgd1 (
|
3601 |
|
|
.din ({tlb_access_sel_thrd3,tlb_access_sel_thrd2,
|
3602 |
|
|
tlb_access_sel_thrd1,tlb_access_sel_thrd0}),
|
3603 |
|
|
.q ({tlb_access_sel_thrd3_d1,tlb_access_sel_thrd2_d1,
|
3604 |
|
|
tlb_access_sel_thrd1_d1,tlb_access_sel_thrd0_d1}),
|
3605 |
|
|
.clk (clk),
|
3606 |
|
|
.se (se), .si (), .so ()
|
3607 |
|
|
);
|
3608 |
|
|
|
3609 |
|
|
wire tlb_access_sel_default;
|
3610 |
|
|
assign tlb_access_sel_default = rst_tri_en | (
|
3611 |
|
|
~(tlb_access_sel_thrd2 | tlb_access_sel_thrd1 | tlb_access_sel_thrd0));
|
3612 |
|
|
|
3613 |
|
|
dff_s #(4) lsu_diagnstc_data_sel_ff (
|
3614 |
|
|
.din ({tlb_access_sel_default,tlb_access_sel_thrd2,
|
3615 |
|
|
tlb_access_sel_thrd1,tlb_access_sel_thrd0}),
|
3616 |
|
|
.q ({lsu_diagnstc_data_sel[3:0]}),
|
3617 |
|
|
.clk (clk),
|
3618 |
|
|
.se (se), .si (), .so ()
|
3619 |
|
|
);
|
3620 |
|
|
|
3621 |
|
|
dff_s #(4) lsu_diagnstc_va_sel_ff (
|
3622 |
|
|
.din ({tlb_access_sel_default,tlb_access_sel_thrd2,
|
3623 |
|
|
tlb_access_sel_thrd1,tlb_access_sel_thrd0}),
|
3624 |
|
|
.q ({lsu_diagnstc_va_sel[3:0]}),
|
3625 |
|
|
.clk (clk),
|
3626 |
|
|
.se (se), .si (), .so ()
|
3627 |
|
|
);
|
3628 |
|
|
|
3629 |
|
|
|
3630 |
|
|
// Begin - Bug 3487
|
3631 |
|
|
assign st_sqsh_m =
|
3632 |
|
|
(st_inst_vld_m & asi_internal_m & lsu_alt_space_m) ; // Squash as bus required for stxa.
|
3633 |
|
|
assign tlb_st_data_sel_m[0] = (tlb_access_sel_thrd0 & ~st_sqsh_m) | (st_sqsh_m & thread0_m) ;
|
3634 |
|
|
assign tlb_st_data_sel_m[1] = (tlb_access_sel_thrd1 & ~st_sqsh_m) | (st_sqsh_m & thread1_m) ;
|
3635 |
|
|
assign tlb_st_data_sel_m[2] = (tlb_access_sel_thrd2 & ~st_sqsh_m) | (st_sqsh_m & thread2_m) ;
|
3636 |
|
|
assign tlb_st_data_sel_m[3] = ~|tlb_st_data_sel_m[2:0];
|
3637 |
|
|
|
3638 |
|
|
assign lsu_ifu_asi_data_en_l = ~(ifu_asi_vld & tlb_access_initiated) ;
|
3639 |
|
|
|
3640 |
|
|
// End - Bug 3487
|
3641 |
|
|
|
3642 |
|
|
/*assign tlb_st_data_sel_m[0] = tlb_access_sel_thrd0 | ((st_inst_vld_m & thread0_m) & tlb_access_blocked) ;
|
3643 |
|
|
assign tlb_st_data_sel_m[1] = tlb_access_sel_thrd1 | ((st_inst_vld_m & thread1_m) & tlb_access_blocked) ;
|
3644 |
|
|
assign tlb_st_data_sel_m[2] = tlb_access_sel_thrd2 | ((st_inst_vld_m & thread2_m) & tlb_access_blocked) ;
|
3645 |
|
|
assign tlb_st_data_sel_m[3] = ~|tlb_st_data_sel_m[2:0];*/
|
3646 |
|
|
|
3647 |
|
|
//assign lsu_tlb_st_sel_m[3:0] = tlb_st_data_sel_m[3:0] ;
|
3648 |
|
|
assign lsu_tlb_st_sel_m[0] = tlb_st_data_sel_m[0] & ~rst_tri_en;
|
3649 |
|
|
assign lsu_tlb_st_sel_m[1] = tlb_st_data_sel_m[1] & ~rst_tri_en;
|
3650 |
|
|
assign lsu_tlb_st_sel_m[2] = tlb_st_data_sel_m[2] & ~rst_tri_en;
|
3651 |
|
|
assign lsu_tlb_st_sel_m[3] = tlb_st_data_sel_m[3] | rst_tri_en;
|
3652 |
|
|
|
3653 |
|
|
assign lsu_tlu_tlb_ld_inst_m =
|
3654 |
|
|
(tlb_access_sel_thrd0 & tlb_ld_inst0 & ~nontlb_asi0) |
|
3655 |
|
|
(tlb_access_sel_thrd1 & tlb_ld_inst1 & ~nontlb_asi1) |
|
3656 |
|
|
(tlb_access_sel_thrd2 & tlb_ld_inst2 & ~nontlb_asi2) |
|
3657 |
|
|
(tlb_access_sel_thrd3 & tlb_ld_inst3 & ~nontlb_asi3) ;
|
3658 |
|
|
|
3659 |
|
|
// diagnstic write for dside will not go thru tlu.
|
3660 |
|
|
assign lsu_tlu_tlb_st_inst_m =
|
3661 |
|
|
(tlb_access_sel_thrd0 & tlb_st_inst0 & ~nontlb_asi0) |
|
3662 |
|
|
(tlb_access_sel_thrd1 & tlb_st_inst1 & ~nontlb_asi1) |
|
3663 |
|
|
(tlb_access_sel_thrd2 & tlb_st_inst2 & ~nontlb_asi2) |
|
3664 |
|
|
(tlb_access_sel_thrd3 & tlb_st_inst3 & ~nontlb_asi3) ;
|
3665 |
|
|
|
3666 |
|
|
assign lsu_tlu_tlb_access_tid_m[0] = tlb_access_sel_thrd1 | tlb_access_sel_thrd3 ;
|
3667 |
|
|
assign lsu_tlu_tlb_access_tid_m[1] = tlb_access_sel_thrd2 | tlb_access_sel_thrd3 ;
|
3668 |
|
|
|
3669 |
|
|
// Diagnostic write to dcache
|
3670 |
|
|
assign dc0_diagnstc_wr_en = (tlb_access_sel_thrd0 & tlb_st_inst0 & dc0_diagnstc_asi) ;
|
3671 |
|
|
assign dc1_diagnstc_wr_en = (tlb_access_sel_thrd1 & tlb_st_inst1 & dc1_diagnstc_asi) ;
|
3672 |
|
|
assign dc2_diagnstc_wr_en = (tlb_access_sel_thrd2 & tlb_st_inst2 & dc2_diagnstc_asi) ;
|
3673 |
|
|
assign dc3_diagnstc_wr_en = (tlb_access_sel_thrd3 & tlb_st_inst3 & dc3_diagnstc_asi) ;
|
3674 |
|
|
assign dc_diagnstc_wr_en =
|
3675 |
|
|
dc0_diagnstc_wr_en | dc1_diagnstc_wr_en | dc2_diagnstc_wr_en | dc3_diagnstc_wr_en ;
|
3676 |
|
|
|
3677 |
|
|
// Diagnostic write to dtag/vld
|
3678 |
|
|
assign dtagv0_diagnstc_wr_en = (tlb_access_sel_thrd0 & tlb_st_inst0 & dtagv0_diagnstc_asi) ;
|
3679 |
|
|
assign dtagv1_diagnstc_wr_en = (tlb_access_sel_thrd1 & tlb_st_inst1 & dtagv1_diagnstc_asi) ;
|
3680 |
|
|
assign dtagv2_diagnstc_wr_en = (tlb_access_sel_thrd2 & tlb_st_inst2 & dtagv2_diagnstc_asi) ;
|
3681 |
|
|
assign dtagv3_diagnstc_wr_en = (tlb_access_sel_thrd3 & tlb_st_inst3 & dtagv3_diagnstc_asi) ;
|
3682 |
|
|
assign dtagv_diagnstc_wr_en =
|
3683 |
|
|
dtagv0_diagnstc_wr_en | dtagv1_diagnstc_wr_en | dtagv2_diagnstc_wr_en | dtagv3_diagnstc_wr_en ;
|
3684 |
|
|
|
3685 |
|
|
// If a diagnostic access is selected in a cycle, then the earliest the
|
3686 |
|
|
// e-stage can occur for the write is 2-cycles later.
|
3687 |
|
|
|
3688 |
|
|
assign diag_wr_src = dtagv_diagnstc_wr_en | dc_diagnstc_wr_en ;
|
3689 |
|
|
|
3690 |
|
|
wire diag_wr_src_with_rst;
|
3691 |
|
|
assign diag_wr_src_with_rst = diag_wr_src & ~lsu_diagnstc_wr_src_sel_e;
|
3692 |
|
|
|
3693 |
|
|
dff_s #(1) diagwr_d1 (
|
3694 |
|
|
.din (diag_wr_src_with_rst),
|
3695 |
|
|
.q (diag_wr_src_d1),
|
3696 |
|
|
.clk (clk),
|
3697 |
|
|
.se (se), .si (), .so ()
|
3698 |
|
|
);
|
3699 |
|
|
|
3700 |
|
|
wire diag_wr_src_d1_with_rst;
|
3701 |
|
|
assign diag_wr_src_d1_with_rst = diag_wr_src_d1 & ~lsu_diagnstc_wr_src_sel_e;
|
3702 |
|
|
|
3703 |
|
|
dff_s #(1) diagwr_d2 (
|
3704 |
|
|
.din (diag_wr_src_d1_with_rst),
|
3705 |
|
|
.q (diag_wr_src_d2),
|
3706 |
|
|
.clk (clk),
|
3707 |
|
|
.se (se), .si (), .so ()
|
3708 |
|
|
);
|
3709 |
|
|
|
3710 |
|
|
// If there is no memory reference, then the diag access is free to go.
|
3711 |
|
|
// tlb_access_blocked must be set appr.
|
3712 |
|
|
wire diag_wr_src_sel_d1, diag_wr_src_sel_din;
|
3713 |
|
|
|
3714 |
|
|
//bug4057: kill diagnostic write if dfq has valid requests to l1d$
|
3715 |
|
|
//assign diag_wr_src_sel_din = diag_wr_src_d2 & ~memref_e;
|
3716 |
|
|
assign diag_wr_src_sel_din = diag_wr_src_d2 & ~(memref_e | lsu_dfq_vld);
|
3717 |
|
|
|
3718 |
|
|
assign lsu_diagnstc_wr_src_sel_e = ~diag_wr_src_sel_d1 & diag_wr_src_sel_din ;
|
3719 |
|
|
|
3720 |
|
|
dff_s #(1) diagwrsel_d1 (
|
3721 |
|
|
.din (diag_wr_src_sel_din),
|
3722 |
|
|
.q (diag_wr_src_sel_d1),
|
3723 |
|
|
.clk (clk),
|
3724 |
|
|
.se (se), .si (), .so ()
|
3725 |
|
|
);
|
3726 |
|
|
|
3727 |
|
|
// Decode for diagnostic cache/dtag/vld write
|
3728 |
|
|
//wire [13:11] lngltncy_ldst_va;
|
3729 |
|
|
|
3730 |
|
|
//assign lngltncy_ldst_va[13:11]= lsu_lngltncy_ldst_va[13:11];
|
3731 |
|
|
|
3732 |
|
|
//assign lsu_diagnstc_wr_way_e[0] = ~lngltncy_ldst_va[12] & ~lngltncy_ldst_va[11] ;
|
3733 |
|
|
//assign lsu_diagnstc_wr_way_e[1] = ~lngltncy_ldst_va[12] & lngltncy_ldst_va[11] ;
|
3734 |
|
|
//assign lsu_diagnstc_wr_way_e[2] = lngltncy_ldst_va[12] & ~lngltncy_ldst_va[11] ;
|
3735 |
|
|
//assign lsu_diagnstc_wr_way_e[3] = lngltncy_ldst_va[12] & lngltncy_ldst_va[11] ;
|
3736 |
|
|
|
3737 |
|
|
assign lsu_diagnstc_dtagv_prty_invrt_e =
|
3738 |
|
|
lsu_diag_va_prty_invrt & dtagv_diagnstc_wr_en & lsu_diagnstc_wr_src_sel_e ;
|
3739 |
|
|
|
3740 |
|
|
// ASI Interface to IFU
|
3741 |
|
|
|
3742 |
|
|
assign lsu_ifu_asi_load =
|
3743 |
|
|
(tlb_access_sel_thrd0 & tlb_ld_inst0 & ifu_nontlb0_asi) |
|
3744 |
|
|
(tlb_access_sel_thrd1 & tlb_ld_inst1 & ifu_nontlb1_asi) |
|
3745 |
|
|
(tlb_access_sel_thrd2 & tlb_ld_inst2 & ifu_nontlb2_asi) |
|
3746 |
|
|
(tlb_access_sel_thrd3 & tlb_ld_inst3 & ifu_nontlb3_asi) ;
|
3747 |
|
|
|
3748 |
|
|
assign ifu_asi_store =
|
3749 |
|
|
(tlb_access_sel_thrd0 & tlb_st_inst0 & ifu_nontlb0_asi) |
|
3750 |
|
|
(tlb_access_sel_thrd1 & tlb_st_inst1 & ifu_nontlb1_asi) |
|
3751 |
|
|
(tlb_access_sel_thrd2 & tlb_st_inst2 & ifu_nontlb2_asi) |
|
3752 |
|
|
(tlb_access_sel_thrd3 & tlb_st_inst3 & ifu_nontlb3_asi) ;
|
3753 |
|
|
|
3754 |
|
|
assign ifu_asi_vld = lsu_ifu_asi_load | ifu_asi_store ;
|
3755 |
|
|
|
3756 |
|
|
dff_s #(2) iasiv_d1 (
|
3757 |
|
|
.din ({ifu_asi_vld,ifu_lsu_asi_ack}),
|
3758 |
|
|
.q ({ifu_asi_vld_d1,ifu_asi_ack_d1}),
|
3759 |
|
|
.clk (clk),
|
3760 |
|
|
.se (se), .si (), .so ()
|
3761 |
|
|
);
|
3762 |
|
|
|
3763 |
|
|
// Bug 3932 - delay asi_vld for ifu.
|
3764 |
|
|
assign lsu_ifu_asi_vld = ifu_asi_vld_d1 & ~ifu_asi_ack_d1 ;
|
3765 |
|
|
|
3766 |
|
|
assign ifu_asi_store_cmplt_en = ifu_asi_store & ifu_lsu_asi_ack ;
|
3767 |
|
|
dff_s #(1) iasist_d1 (
|
3768 |
|
|
.din (ifu_asi_store_cmplt_en),
|
3769 |
|
|
.q (ifu_asi_store_cmplt_en_d1),
|
3770 |
|
|
.clk (clk),
|
3771 |
|
|
.se (se), .si (), .so ()
|
3772 |
|
|
);
|
3773 |
|
|
|
3774 |
|
|
assign lsu_ifu_asi_thrid[1:0] = lsu_tlu_tlb_access_tid_m[1:0] ;
|
3775 |
|
|
|
3776 |
|
|
|
3777 |
|
|
//=========================================================================================
|
3778 |
|
|
// MEMBAR/FLUSH HANDLING
|
3779 |
|
|
//=========================================================================================
|
3780 |
|
|
|
3781 |
|
|
// Check for skids in this area - verification.
|
3782 |
|
|
|
3783 |
|
|
wire [3:0] no_spc_rmo_st ;
|
3784 |
|
|
|
3785 |
|
|
// Can membar/flush cause switch out from front end ??? Need to remove from
|
3786 |
|
|
// ldst_miss if case.
|
3787 |
|
|
// membar/flush will both swo thread and assert flush.
|
3788 |
|
|
// membar will signal completion once stb for thread empty
|
3789 |
|
|
// flush will signal completion once flush pkt is visible at head of cfq and
|
3790 |
|
|
// i-side invalidates are complete
|
3791 |
|
|
// ** flush bit needs to be added to dfq **
|
3792 |
|
|
|
3793 |
|
|
dff_s #(2) bsync_stgm (
|
3794 |
|
|
.din ({ifu_tlu_mb_inst_e,ifu_tlu_flsh_inst_e}),
|
3795 |
|
|
.q ({mbar_inst_m,flsh_inst_m}),
|
3796 |
|
|
.clk (clk),
|
3797 |
|
|
.se (se), .si (), .so ()
|
3798 |
|
|
);
|
3799 |
|
|
|
3800 |
|
|
assign lsu_flsh_inst_m = flsh_inst_m ;
|
3801 |
|
|
|
3802 |
|
|
wire mbar_inst_unflushed,flsh_inst_unflushed ;
|
3803 |
|
|
|
3804 |
|
|
dff_s #(2) bsync_stgg (
|
3805 |
|
|
.din ({mbar_inst_m,flsh_inst_m}),
|
3806 |
|
|
.q ({mbar_inst_unflushed,flsh_inst_unflushed}),
|
3807 |
|
|
.clk (clk),
|
3808 |
|
|
.se (se), .si (), .so ()
|
3809 |
|
|
);
|
3810 |
|
|
|
3811 |
|
|
wire [3:0] flsh_cmplt_d1 ;
|
3812 |
|
|
/*dff #(4) flshcmplt (
|
3813 |
|
|
.din (lsu_dfq_flsh_cmplt[3:0]),
|
3814 |
|
|
.q (flsh_cmplt_d1[3:0]),
|
3815 |
|
|
.clk (clk),
|
3816 |
|
|
.se (se), .si (), .so ()
|
3817 |
|
|
);*/
|
3818 |
|
|
|
3819 |
|
|
// now flopped in dctl
|
3820 |
|
|
assign flsh_cmplt_d1[3:0] = lsu_dfq_flsh_cmplt[3:0] ;
|
3821 |
|
|
|
3822 |
|
|
assign mbar_inst_g = mbar_inst_unflushed & lsu_inst_vld_w ;
|
3823 |
|
|
assign flsh_inst_g = flsh_inst_unflushed & lsu_inst_vld_w ;
|
3824 |
|
|
|
3825 |
|
|
// THREAD0 MEMBAR/FLUSH
|
3826 |
|
|
|
3827 |
|
|
// barrier sync
|
3828 |
|
|
assign bsync0_reset =
|
3829 |
|
|
reset | (mbar_vld0 & lsu_stb_empty[0] & no_spc_rmo_st[0])
|
3830 |
|
|
| (flsh_vld0 & flsh_cmplt_d1[0]) ;
|
3831 |
|
|
|
3832 |
|
|
assign bsync0_en = (flush_inst0_g | mbar_inst0_g) & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
|
3833 |
|
|
|
3834 |
|
|
assign flush_inst0_g = flsh_inst_g & thread0_g ;
|
3835 |
|
|
assign mbar_inst0_g = mbar_inst_g & thread0_g ;
|
3836 |
|
|
|
3837 |
|
|
// bsyncs are set in g-stage to allow earlier stores in pipe to drain to
|
3838 |
|
|
// thread's stb
|
3839 |
|
|
dffre_s #(2) bsync_vld0 (
|
3840 |
|
|
.din ({mbar_inst0_g,flush_inst0_g}),
|
3841 |
|
|
.q ({mbar_vld0,flsh_vld0}),
|
3842 |
|
|
.rst (bsync0_reset), .en (bsync0_en),
|
3843 |
|
|
.clk (clk),
|
3844 |
|
|
.se (se), .si (), .so ()
|
3845 |
|
|
);
|
3846 |
|
|
|
3847 |
|
|
// THREAD1 MEMBAR/FLUSH
|
3848 |
|
|
|
3849 |
|
|
// barrier sync
|
3850 |
|
|
assign bsync1_reset =
|
3851 |
|
|
reset | (mbar_vld1 & lsu_stb_empty[1] & no_spc_rmo_st[1])
|
3852 |
|
|
| (flsh_vld1 & flsh_cmplt_d1[1]) ;
|
3853 |
|
|
|
3854 |
|
|
assign bsync1_en = (flush_inst1_g | mbar_inst1_g) & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
|
3855 |
|
|
|
3856 |
|
|
assign flush_inst1_g = flsh_inst_g & thread1_g ;
|
3857 |
|
|
assign mbar_inst1_g = mbar_inst_g & thread1_g ;
|
3858 |
|
|
|
3859 |
|
|
// bsyncs are set in g-stage to allow earlier stores in pipe to drain to
|
3860 |
|
|
// thread's stb
|
3861 |
|
|
dffre_s #(2) bsync_vld1 (
|
3862 |
|
|
.din ({mbar_inst1_g,flush_inst1_g}),
|
3863 |
|
|
.q ({mbar_vld1,flsh_vld1}),
|
3864 |
|
|
.rst (bsync1_reset), .en (bsync1_en),
|
3865 |
|
|
.clk (clk),
|
3866 |
|
|
.se (se), .si (), .so ()
|
3867 |
|
|
);
|
3868 |
|
|
|
3869 |
|
|
// THREAD2 MEMBAR/FLUSH
|
3870 |
|
|
|
3871 |
|
|
// barrier sync
|
3872 |
|
|
assign bsync2_reset =
|
3873 |
|
|
reset | (mbar_vld2 & lsu_stb_empty[2] & no_spc_rmo_st[2])
|
3874 |
|
|
| (flsh_vld2 & flsh_cmplt_d1[2]) ;
|
3875 |
|
|
|
3876 |
|
|
assign bsync2_en = (flush_inst2_g | mbar_inst2_g) & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
|
3877 |
|
|
|
3878 |
|
|
assign flush_inst2_g = flsh_inst_g & thread2_g ;
|
3879 |
|
|
assign mbar_inst2_g = mbar_inst_g & thread2_g ;
|
3880 |
|
|
|
3881 |
|
|
// bsyncs are set in g-stage to allow earlier stores in pipe to drain to
|
3882 |
|
|
// thread's stb
|
3883 |
|
|
dffre_s #(2) bsync_vld2 (
|
3884 |
|
|
.din ({mbar_inst2_g,flush_inst2_g}),
|
3885 |
|
|
.q ({mbar_vld2,flsh_vld2}),
|
3886 |
|
|
.rst (bsync2_reset), .en (bsync2_en),
|
3887 |
|
|
.clk (clk),
|
3888 |
|
|
.se (se), .si (), .so ()
|
3889 |
|
|
);
|
3890 |
|
|
|
3891 |
|
|
// THREAD3 MEMBAR/FLUSH
|
3892 |
|
|
|
3893 |
|
|
// barrier sync
|
3894 |
|
|
assign bsync3_reset =
|
3895 |
|
|
reset | (mbar_vld3 & lsu_stb_empty[3] & no_spc_rmo_st[3])
|
3896 |
|
|
| (flsh_vld3 & flsh_cmplt_d1[3]) ;
|
3897 |
|
|
|
3898 |
|
|
assign bsync3_en = (flush_inst3_g | mbar_inst3_g) & lsu_inst_vld_w & ~dctl_flush_pipe_w ;
|
3899 |
|
|
|
3900 |
|
|
assign flush_inst3_g = flsh_inst_g & thread3_g ;
|
3901 |
|
|
assign mbar_inst3_g = mbar_inst_g & thread3_g ;
|
3902 |
|
|
|
3903 |
|
|
// bsyncs are set in g-stage to allow earlier stores in pipe to drain to
|
3904 |
|
|
// thread's stb
|
3905 |
|
|
dffre_s #(2) bsync_vld3 (
|
3906 |
|
|
.din ({mbar_inst3_g,flush_inst3_g}),
|
3907 |
|
|
.q ({mbar_vld3,flsh_vld3}),
|
3908 |
|
|
.rst (bsync3_reset), .en (bsync3_en),
|
3909 |
|
|
.clk (clk),
|
3910 |
|
|
.se (se), .si (), .so ()
|
3911 |
|
|
);
|
3912 |
|
|
|
3913 |
|
|
//=========================================================================================
|
3914 |
|
|
// RMO Store Ack Count
|
3915 |
|
|
//=========================================================================================
|
3916 |
|
|
|
3917 |
|
|
// Each thread maintains an 8b outstanding rmo ack count. To avoid overflow,
|
3918 |
|
|
// it is the responsiblity of software to insert a membar after at most 256 rmo stores.
|
3919 |
|
|
// 03/08/2003 now change from 256 to 16
|
3920 |
|
|
// 8 outstanding instead of 16
|
3921 |
|
|
|
3922 |
|
|
wire [3:0] ackcnt0,ackcnt1,ackcnt2,ackcnt3 ;
|
3923 |
|
|
wire [3:0] ackcnt0_din,ackcnt1_din,ackcnt2_din,ackcnt3_din ;
|
3924 |
|
|
|
3925 |
|
|
// st_rmo_issue/st_rmo_ack vectors are one hot.
|
3926 |
|
|
// Adders(2). Need two as two separate threads can be incremented and decremented
|
3927 |
|
|
// in a cycle.
|
3928 |
|
|
wire [3:0] ackcnt_incr, ackcnt_decr ;
|
3929 |
|
|
wire [3:0] ackcnt_mx_incr, ackcnt_mx_decr ;
|
3930 |
|
|
|
3931 |
|
|
wire [3:0] acknt_mx_incr_sel;
|
3932 |
|
|
assign acknt_mx_incr_sel[3:0] = lsu_stb_rmo_st_issue[3:0];
|
3933 |
|
|
|
3934 |
|
|
assign ackcnt_mx_incr[3:0] =
|
3935 |
|
|
(acknt_mx_incr_sel[0] ? ackcnt0[3:0] : 4'b0) |
|
3936 |
|
|
(acknt_mx_incr_sel[1] ? ackcnt1[3:0] : 4'b0) |
|
3937 |
|
|
(acknt_mx_incr_sel[2] ? ackcnt2[3:0] : 4'b0) |
|
3938 |
|
|
(acknt_mx_incr_sel[3] ? ackcnt3[3:0] : 4'b0) ;
|
3939 |
|
|
|
3940 |
|
|
|
3941 |
|
|
wire [3:0] acknt_mx_decr_sel;
|
3942 |
|
|
assign acknt_mx_decr_sel[3:0] = lsu_cpx_rmo_st_ack[3:0];
|
3943 |
|
|
|
3944 |
|
|
assign ackcnt_mx_decr[3:0] =
|
3945 |
|
|
(acknt_mx_decr_sel[0] ? ackcnt0[3:0] : 4'b0 ) |
|
3946 |
|
|
(acknt_mx_decr_sel[1] ? ackcnt1[3:0] : 4'b0 ) |
|
3947 |
|
|
(acknt_mx_decr_sel[2] ? ackcnt2[3:0] : 4'b0 ) |
|
3948 |
|
|
(acknt_mx_decr_sel[3] ? ackcnt3[3:0] : 4'b0 ) ;
|
3949 |
|
|
|
3950 |
|
|
|
3951 |
|
|
assign ackcnt_incr[3:0] = ackcnt_mx_incr[3:0] + 4'b0001 ;
|
3952 |
|
|
assign ackcnt_decr[3:0] = ackcnt_mx_decr[3:0] - 4'b0001 ;
|
3953 |
|
|
|
3954 |
|
|
assign ackcnt0_din[3:0] = lsu_cpx_rmo_st_ack[0] ? ackcnt_decr[3:0] : ackcnt_incr[3:0] ;
|
3955 |
|
|
assign ackcnt1_din[3:0] = lsu_cpx_rmo_st_ack[1] ? ackcnt_decr[3:0] : ackcnt_incr[3:0] ;
|
3956 |
|
|
assign ackcnt2_din[3:0] = lsu_cpx_rmo_st_ack[2] ? ackcnt_decr[3:0] : ackcnt_incr[3:0] ;
|
3957 |
|
|
assign ackcnt3_din[3:0] = lsu_cpx_rmo_st_ack[3] ? ackcnt_decr[3:0] : ackcnt_incr[3:0] ;
|
3958 |
|
|
|
3959 |
|
|
wire [3:0] ackcnt_en ;
|
3960 |
|
|
// if both occur in the same cycle then they cancel out.
|
3961 |
|
|
assign ackcnt_en[0] = lsu_stb_rmo_st_issue[0] ^ lsu_cpx_rmo_st_ack[0] ;
|
3962 |
|
|
assign ackcnt_en[1] = lsu_stb_rmo_st_issue[1] ^ lsu_cpx_rmo_st_ack[1] ;
|
3963 |
|
|
assign ackcnt_en[2] = lsu_stb_rmo_st_issue[2] ^ lsu_cpx_rmo_st_ack[2] ;
|
3964 |
|
|
assign ackcnt_en[3] = lsu_stb_rmo_st_issue[3] ^ lsu_cpx_rmo_st_ack[3] ;
|
3965 |
|
|
|
3966 |
|
|
// Thread0
|
3967 |
|
|
dffre_s #(4) ackcnt0_ff (
|
3968 |
|
|
.din (ackcnt0_din[3:0]),
|
3969 |
|
|
.q (ackcnt0[3:0]),
|
3970 |
|
|
.rst (reset), .en (ackcnt_en[0]),
|
3971 |
|
|
.clk (clk),
|
3972 |
|
|
.se (se), .si (), .so ()
|
3973 |
|
|
);
|
3974 |
|
|
|
3975 |
|
|
// Thread1
|
3976 |
|
|
dffre_s #(4) ackcnt1_ff (
|
3977 |
|
|
.din (ackcnt1_din[3:0]),
|
3978 |
|
|
.q (ackcnt1[3:0]),
|
3979 |
|
|
.rst (reset), .en (ackcnt_en[1]),
|
3980 |
|
|
.clk (clk),
|
3981 |
|
|
.se (se), .si (), .so ()
|
3982 |
|
|
);
|
3983 |
|
|
|
3984 |
|
|
// Thread2
|
3985 |
|
|
dffre_s #(4) ackcnt2_ff (
|
3986 |
|
|
.din (ackcnt2_din[3:0]),
|
3987 |
|
|
.q (ackcnt2[3:0]),
|
3988 |
|
|
.rst (reset), .en (ackcnt_en[2]),
|
3989 |
|
|
.clk (clk),
|
3990 |
|
|
.se (se), .si (), .so ()
|
3991 |
|
|
);
|
3992 |
|
|
|
3993 |
|
|
// Thread3
|
3994 |
|
|
dffre_s #(4) ackcnt3_ff (
|
3995 |
|
|
.din (ackcnt3_din[3:0]),
|
3996 |
|
|
.q (ackcnt3[3:0]),
|
3997 |
|
|
.rst (reset), .en (ackcnt_en[3]),
|
3998 |
|
|
.clk (clk),
|
3999 |
|
|
.se (se), .si (), .so ()
|
4000 |
|
|
);
|
4001 |
|
|
|
4002 |
|
|
assign no_spc_rmo_st[0] = ~(|ackcnt0[3:0]) ;
|
4003 |
|
|
assign no_spc_rmo_st[1] = ~(|ackcnt1[3:0]) ;
|
4004 |
|
|
assign no_spc_rmo_st[2] = ~(|ackcnt2[3:0]) ;
|
4005 |
|
|
assign no_spc_rmo_st[3] = ~(|ackcnt3[3:0]) ;
|
4006 |
|
|
|
4007 |
|
|
//8 outstanding rmo st will throttle the PCX issue st
|
4008 |
|
|
assign lsu_outstanding_rmo_st_max [0] = ackcnt0[3];
|
4009 |
|
|
assign lsu_outstanding_rmo_st_max [1] = ackcnt1[3];
|
4010 |
|
|
assign lsu_outstanding_rmo_st_max [2] = ackcnt2[3];
|
4011 |
|
|
assign lsu_outstanding_rmo_st_max [3] = ackcnt3[3];
|
4012 |
|
|
|
4013 |
|
|
// streaming unit does not have to care about outstanding rmo sparc-stores.
|
4014 |
|
|
// membar will take care of that. spu must insert appr. delay in sampling signal.
|
4015 |
|
|
|
4016 |
|
|
/*dff #(4) spustb_d1 ( // moved to stb_rwctl
|
4017 |
|
|
.din (lsu_stb_empty[3:0]),
|
4018 |
|
|
.q (lsu_spu_stb_empty[3:0]),
|
4019 |
|
|
.clk (clk),
|
4020 |
|
|
.se (se), .si (), .so ()
|
4021 |
|
|
); */
|
4022 |
|
|
|
4023 |
|
|
//assign lsu_spu_stb_empty[3:0] = lsu_stb_empty[3:0] ;
|
4024 |
|
|
|
4025 |
|
|
//=========================================================================================
|
4026 |
|
|
// Thread Staging
|
4027 |
|
|
//=========================================================================================
|
4028 |
|
|
|
4029 |
|
|
// Thread staging can be optimized.
|
4030 |
|
|
|
4031 |
|
|
dff_s #(2) thrid_stgd (
|
4032 |
|
|
.din (ifu_lsu_thrid_s[1:0]),
|
4033 |
|
|
.q (thrid_d[1:0]),
|
4034 |
|
|
.clk (clk),
|
4035 |
|
|
.se (se), .si (), .so ()
|
4036 |
|
|
);
|
4037 |
|
|
|
4038 |
|
|
dff_s #(2) lsu_tlu_thrid_stgd (
|
4039 |
|
|
.din (ifu_lsu_thrid_s[1:0]),
|
4040 |
|
|
.q (lsu_tlu_thrid_d[1:0]),
|
4041 |
|
|
.clk (clk),
|
4042 |
|
|
.se (se), .si (), .so ()
|
4043 |
|
|
);
|
4044 |
|
|
|
4045 |
|
|
//assign lsu_tlu_thrid_d[1:0] = thrid_d[1:0] ;
|
4046 |
|
|
|
4047 |
|
|
assign thread0_d = ~thrid_d[1] & ~thrid_d[0] ;
|
4048 |
|
|
assign thread1_d = ~thrid_d[1] & thrid_d[0] ;
|
4049 |
|
|
assign thread2_d = thrid_d[1] & ~thrid_d[0] ;
|
4050 |
|
|
assign thread3_d = thrid_d[1] & thrid_d[0] ;
|
4051 |
|
|
|
4052 |
|
|
dff_s #(2) thrid_stge (
|
4053 |
|
|
.din (thrid_d[1:0]),
|
4054 |
|
|
.q (thrid_e[1:0]),
|
4055 |
|
|
.clk (clk),
|
4056 |
|
|
.se (se), .si (), .so ()
|
4057 |
|
|
);
|
4058 |
|
|
|
4059 |
|
|
assign thread0_e = ~thrid_e[1] & ~thrid_e[0] ;
|
4060 |
|
|
assign thread1_e = ~thrid_e[1] & thrid_e[0] ;
|
4061 |
|
|
assign thread2_e = thrid_e[1] & ~thrid_e[0] ;
|
4062 |
|
|
assign thread3_e = thrid_e[1] & thrid_e[0] ;
|
4063 |
|
|
|
4064 |
|
|
dff_s #(2) thrid_stgm (
|
4065 |
|
|
.din (thrid_e[1:0]),
|
4066 |
|
|
.q (thrid_m[1:0]),
|
4067 |
|
|
.clk (clk),
|
4068 |
|
|
.se (se), .si (), .so ()
|
4069 |
|
|
);
|
4070 |
|
|
|
4071 |
|
|
assign thread0_m = ~thrid_m[1] & ~thrid_m[0] ;
|
4072 |
|
|
assign thread1_m = ~thrid_m[1] & thrid_m[0] ;
|
4073 |
|
|
assign thread2_m = thrid_m[1] & ~thrid_m[0] ;
|
4074 |
|
|
assign thread3_m = thrid_m[1] & thrid_m[0] ;
|
4075 |
|
|
|
4076 |
|
|
bw_u1_buf_30x UZfix_thread0_m ( .a(thread0_m), .z(lsu_dctldp_thread0_m) );
|
4077 |
|
|
bw_u1_buf_30x UZfix_thread1_m ( .a(thread1_m), .z(lsu_dctldp_thread1_m) );
|
4078 |
|
|
bw_u1_buf_30x UZfix_thread2_m ( .a(thread2_m), .z(lsu_dctldp_thread2_m) );
|
4079 |
|
|
bw_u1_buf_30x UZfix_thread3_m ( .a(thread3_m), .z(lsu_dctldp_thread3_m) );
|
4080 |
|
|
|
4081 |
|
|
dff_s #(2) thrid_stgg (
|
4082 |
|
|
.din (thrid_m[1:0]),
|
4083 |
|
|
.q (thrid_g[1:0]),
|
4084 |
|
|
.clk (clk),
|
4085 |
|
|
.se (se), .si (), .so ()
|
4086 |
|
|
);
|
4087 |
|
|
|
4088 |
|
|
assign thread0_g = ~thrid_g[1] & ~thrid_g[0] ;
|
4089 |
|
|
assign thread1_g = ~thrid_g[1] & thrid_g[0] ;
|
4090 |
|
|
assign thread2_g = thrid_g[1] & ~thrid_g[0] ;
|
4091 |
|
|
assign thread3_g = thrid_g[1] & thrid_g[0] ;
|
4092 |
|
|
|
4093 |
|
|
dff_s #(2) thrid_stgw2 (
|
4094 |
|
|
.din (thrid_g[1:0]),
|
4095 |
|
|
.q (thrid_w2[1:0]),
|
4096 |
|
|
.clk (clk),
|
4097 |
|
|
.se (se), .si (), .so ()
|
4098 |
|
|
);
|
4099 |
|
|
|
4100 |
|
|
assign thread0_w2 = ~thrid_w2[1] & ~thrid_w2[0] ;
|
4101 |
|
|
assign thread1_w2 = ~thrid_w2[1] & thrid_w2[0] ;
|
4102 |
|
|
assign thread2_w2 = thrid_w2[1] & ~thrid_w2[0] ;
|
4103 |
|
|
assign thread3_w2 = thrid_w2[1] & thrid_w2[0] ;
|
4104 |
|
|
|
4105 |
|
|
dff_s #(2) thrid_stgw3 (
|
4106 |
|
|
.din (thrid_w2[1:0]),
|
4107 |
|
|
.q (thrid_w3[1:0]),
|
4108 |
|
|
.clk (clk),
|
4109 |
|
|
.se (se), .si (), .so ()
|
4110 |
|
|
);
|
4111 |
|
|
|
4112 |
|
|
assign thread0_w3 = ~thrid_w3[1] & ~thrid_w3[0] ;
|
4113 |
|
|
assign thread1_w3 = ~thrid_w3[1] & thrid_w3[0] ;
|
4114 |
|
|
assign thread2_w3 = thrid_w3[1] & ~thrid_w3[0] ;
|
4115 |
|
|
assign thread3_w3 = thrid_w3[1] & thrid_w3[0] ;
|
4116 |
|
|
|
4117 |
|
|
//dff #(4) thrid_stgw3 (
|
4118 |
|
|
// .din ({thread0_w2,thread1_w2,thread2_w2,thread3_w2}),
|
4119 |
|
|
// .q ({thread0_w3,thread1_w3,thread2_w3,thread3_w3}),
|
4120 |
|
|
// .clk (clk),
|
4121 |
|
|
// .se (se), .si (), .so ()
|
4122 |
|
|
// );
|
4123 |
|
|
|
4124 |
|
|
// ldxa thread id
|
4125 |
|
|
|
4126 |
|
|
assign ldxa_thrid_w2[1:0] = tlu_lsu_ldxa_tid_w2[1:0] ;
|
4127 |
|
|
|
4128 |
|
|
assign tlu_ldxa_thread0_w2 = ~ldxa_thrid_w2[1] & ~ldxa_thrid_w2[0] ;
|
4129 |
|
|
assign tlu_ldxa_thread1_w2 = ~ldxa_thrid_w2[1] & ldxa_thrid_w2[0] ;
|
4130 |
|
|
assign tlu_ldxa_thread2_w2 = ldxa_thrid_w2[1] & ~ldxa_thrid_w2[0] ;
|
4131 |
|
|
assign tlu_ldxa_thread3_w2 = ldxa_thrid_w2[1] & ldxa_thrid_w2[0] ;
|
4132 |
|
|
|
4133 |
|
|
assign spu_stxa_thread0 = ~spu_lsu_stxa_ack_tid[1] & ~spu_lsu_stxa_ack_tid[0] ;
|
4134 |
|
|
assign spu_stxa_thread1 = ~spu_lsu_stxa_ack_tid[1] & spu_lsu_stxa_ack_tid[0] ;
|
4135 |
|
|
assign spu_stxa_thread2 = spu_lsu_stxa_ack_tid[1] & ~spu_lsu_stxa_ack_tid[0] ;
|
4136 |
|
|
assign spu_stxa_thread3 = spu_lsu_stxa_ack_tid[1] & spu_lsu_stxa_ack_tid[0] ;
|
4137 |
|
|
|
4138 |
|
|
assign spu_ldxa_thread0_w2 = ~spu_lsu_ldxa_tid_w2[1] & ~spu_lsu_ldxa_tid_w2[0] ;
|
4139 |
|
|
assign spu_ldxa_thread1_w2 = ~spu_lsu_ldxa_tid_w2[1] & spu_lsu_ldxa_tid_w2[0] ;
|
4140 |
|
|
assign spu_ldxa_thread2_w2 = spu_lsu_ldxa_tid_w2[1] & ~spu_lsu_ldxa_tid_w2[0] ;
|
4141 |
|
|
assign spu_ldxa_thread3_w2 = spu_lsu_ldxa_tid_w2[1] & spu_lsu_ldxa_tid_w2[0] ;
|
4142 |
|
|
|
4143 |
|
|
assign ifu_ldxa_thread0_w2 = ~ifu_lsu_ldxa_tid_w2[1] & ~ifu_lsu_ldxa_tid_w2[0] ;
|
4144 |
|
|
assign ifu_ldxa_thread1_w2 = ~ifu_lsu_ldxa_tid_w2[1] & ifu_lsu_ldxa_tid_w2[0] ;
|
4145 |
|
|
assign ifu_ldxa_thread2_w2 = ifu_lsu_ldxa_tid_w2[1] & ~ifu_lsu_ldxa_tid_w2[0] ;
|
4146 |
|
|
assign ifu_ldxa_thread3_w2 = ifu_lsu_ldxa_tid_w2[1] & ifu_lsu_ldxa_tid_w2[0] ;
|
4147 |
|
|
|
4148 |
|
|
wire [1:0] ifu_nontlb_asi_tid ;
|
4149 |
|
|
dff_s #(2) iasi_tid (
|
4150 |
|
|
.din (lsu_ifu_asi_thrid[1:0]),
|
4151 |
|
|
.q (ifu_nontlb_asi_tid[1:0]),
|
4152 |
|
|
.clk (clk),
|
4153 |
|
|
.se (se), .si (), .so ()
|
4154 |
|
|
);
|
4155 |
|
|
|
4156 |
|
|
assign ifu_stxa_thread0_w2 = ~ifu_nontlb_asi_tid[1] & ~ifu_nontlb_asi_tid[0] ;
|
4157 |
|
|
assign ifu_stxa_thread1_w2 = ~ifu_nontlb_asi_tid[1] & ifu_nontlb_asi_tid[0] ;
|
4158 |
|
|
assign ifu_stxa_thread2_w2 = ifu_nontlb_asi_tid[1] & ~ifu_nontlb_asi_tid[0] ;
|
4159 |
|
|
assign ifu_stxa_thread3_w2 = ifu_nontlb_asi_tid[1] & ifu_nontlb_asi_tid[0] ;
|
4160 |
|
|
|
4161 |
|
|
assign tlu_stxa_thread0_w2 = ~tlu_lsu_stxa_ack_tid[1] & ~tlu_lsu_stxa_ack_tid[0] ;
|
4162 |
|
|
assign tlu_stxa_thread1_w2 = ~tlu_lsu_stxa_ack_tid[1] & tlu_lsu_stxa_ack_tid[0] ;
|
4163 |
|
|
assign tlu_stxa_thread2_w2 = tlu_lsu_stxa_ack_tid[1] & ~tlu_lsu_stxa_ack_tid[0] ;
|
4164 |
|
|
assign tlu_stxa_thread3_w2 = tlu_lsu_stxa_ack_tid[1] & tlu_lsu_stxa_ack_tid[0] ;
|
4165 |
|
|
|
4166 |
|
|
//=========================================================================================
|
4167 |
|
|
// Exception Handling
|
4168 |
|
|
//=========================================================================================
|
4169 |
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|
4170 |
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|
4171 |
|
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// tlb related exceptions/errors
|
4172 |
|
|
//SC assign tlb_daccess_excptn_e =
|
4173 |
|
|
//SC ((rd_only_ltlb_asi_e & st_inst_vld_e) |
|
4174 |
|
|
//SC (wr_only_ltlb_asi_e & ld_inst_vld_e)) & alt_space_e ;
|
4175 |
|
|
|
4176 |
|
|
//SC assign tlb_daccess_error_e =
|
4177 |
|
|
//SC ((dfill_tlb_asi_e & ~lsu_tlb_writeable) |
|
4178 |
|
|
//SC (ifill_tlb_asi_e & ~ifu_lsu_tlb_writeable)) & st_inst_vld_e & alt_space_e ;
|
4179 |
|
|
|
4180 |
|
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//SC dff #(2) tlbex_stgm (
|
4181 |
|
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//SC .din ({tlb_daccess_excptn_e,tlb_daccess_error_e}),
|
4182 |
|
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//SC .q ({tlb_daccess_excptn_m,tlb_daccess_error_m}),
|
4183 |
|
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//SC .clk (clk),
|
4184 |
|
|
//SC .se (se), .si (), .so ()
|
4185 |
|
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//SC );
|
4186 |
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|
|
4187 |
|
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//SC dff #(2) tlbex_stgg (
|
4188 |
|
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//SC .din ({tlb_daccess_excptn_m,tlb_daccess_error_m}),
|
4189 |
|
|
//SC .q ({tlb_daccess_excptn_g,tlb_daccess_error_g}),
|
4190 |
|
|
//SC .clk (clk),
|
4191 |
|
|
//SC .se (se), .si (), .so ()
|
4192 |
|
|
//SC );
|
4193 |
|
|
|
4194 |
|
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//assign pstate_priv_m =
|
4195 |
|
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// thread0_m ? tlu_lsu_pstate_priv[0] :
|
4196 |
|
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// thread1_m ? tlu_lsu_pstate_priv[1] :
|
4197 |
|
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// thread2_m ? tlu_lsu_pstate_priv[2] :
|
4198 |
|
|
// tlu_lsu_pstate_priv[3] ;
|
4199 |
|
|
|
4200 |
|
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//SC mux4ds #(1) pstate_priv_m_mux (
|
4201 |
|
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//SC .in0 (tlu_lsu_pstate_priv[0]),
|
4202 |
|
|
//SC .in1 (tlu_lsu_pstate_priv[1]),
|
4203 |
|
|
//SC .in2 (tlu_lsu_pstate_priv[2]),
|
4204 |
|
|
//SC .in3 (tlu_lsu_pstate_priv[3]),
|
4205 |
|
|
//SC .sel0 (thread0_m),
|
4206 |
|
|
//SC .sel1 (thread1_m),
|
4207 |
|
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//SC .sel2 (thread2_m),
|
4208 |
|
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//SC .sel3 (thread3_m),
|
4209 |
|
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//SC .dout (pstate_priv_m)
|
4210 |
|
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//SC );
|
4211 |
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|
|
4212 |
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//SC dff priv_stgg (
|
4213 |
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//SC .din (pstate_priv_m),
|
4214 |
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//SC .q (pstate_priv),
|
4215 |
|
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//SC .clk (clk),
|
4216 |
|
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//SC .se (se), .si (), .so ()
|
4217 |
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//SC );
|
4218 |
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|
4219 |
|
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// privilege violation - priv page accessed in user mode
|
4220 |
|
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//SC assign priv_pg_usr_mode = // data access exception; TT=h30
|
4221 |
|
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//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~(pstate_priv | hpv_priv) & tlb_rd_tte_data[`STLB_DATA_P] ;
|
4222 |
|
|
|
4223 |
|
|
// protection violation - store to a page that does not have write permission
|
4224 |
|
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//SC assign nonwr_pg_st_access = // data access protection; TT=h33
|
4225 |
|
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//SC st_inst_vld_unflushed &
|
4226 |
|
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//SC ~tlb_rd_tte_data[`STLB_DATA_W] & ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
|
4227 |
|
|
//lsu_dtlb_bypass_g) ; // W=1 in bypass mode - In bypass mode this trap will never happen !!!
|
4228 |
|
|
|
4229 |
|
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//SC wire daccess_prot ;
|
4230 |
|
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//SC assign daccess_prot = nonwr_pg_st_access ;
|
4231 |
|
|
//((~lsu_dtlb_bypass_g & tlb_cam_hit_g) | (tlb_byp_asi_g & lsu_alt_space_g)) ;
|
4232 |
|
|
|
4233 |
|
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// access to a page marked with the nfo with an asi other than nfo asi.
|
4234 |
|
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//SC assign nfo_pg_nonnfo_asi = // data access exception; TT=h30
|
4235 |
|
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//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & // any access
|
4236 |
|
|
//SC ((~nofault_asi_g & lsu_alt_space_g) | ~lsu_alt_space_g) // in alternate space or not
|
4237 |
|
|
//SC & tlb_rd_tte_data[`STLB_DATA_NFO] ;
|
4238 |
|
|
|
4239 |
|
|
// as_if_usr asi accesses priv page.
|
4240 |
|
|
//SC assign as_if_usr_priv_pg = // data access exception; TT=h30
|
4241 |
|
|
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & as_if_user_asi_g & lsu_alt_space_g &
|
4242 |
|
|
//SC tlb_rd_tte_data[`STLB_DATA_P] ;
|
4243 |
|
|
|
4244 |
|
|
|
4245 |
|
|
// non-cacheable address - iospace or cp=0 (???)
|
4246 |
|
|
// atomic access to non-cacheable space.
|
4247 |
|
|
//SC assign atm_access_w_nc = atomic_g & tlb_pgnum[39] ; // io space
|
4248 |
|
|
|
4249 |
|
|
// atomic inst with unsupported asi.
|
4250 |
|
|
//SC assign atm_access_unsup_asi = atomic_g & ~atomic_asi_g & lsu_alt_space_g ;
|
4251 |
|
|
|
4252 |
|
|
//SC wire tlb_tte_vld_g ;
|
4253 |
|
|
//SC assign tlb_tte_vld_g = ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
|
4254 |
|
|
|
4255 |
|
|
//SC wire pg_with_ebit ;
|
4256 |
|
|
//SC assign pg_with_ebit =
|
4257 |
|
|
//SC (tlb_rd_tte_data[`STLB_DATA_E] & tlb_tte_vld_g) | // tte
|
4258 |
|
|
//SC (lsu_dtlb_bypass_g & ~(phy_use_ec_asi_g & lsu_alt_space_g)) | // regular bypass
|
4259 |
|
|
//SC (tlb_byp_asi_g & ~phy_use_ec_asi_g & lsu_alt_space_g) ; // phy_byp
|
4260 |
|
|
|
4261 |
|
|
//SC wire spec_access_epage ;
|
4262 |
|
|
//SC assign spec_access_epage =
|
4263 |
|
|
//SC ((ld_inst_vld_unflushed & nofault_asi_g & lsu_alt_space_g) | // spec load
|
4264 |
|
|
//SC flsh_inst_g) & // flush inst
|
4265 |
|
|
//SC pg_with_ebit ; // page with side effects
|
4266 |
|
|
// tlb_rd_tte_data[`STLB_DATA_E] ; // page with side effects
|
4267 |
|
|
|
4268 |
|
|
//SC wire quad_asi_non_ldstda ;
|
4269 |
|
|
// quad-asi used with non ldda/stda
|
4270 |
|
|
// remove st_inst_vld - stquad unused
|
4271 |
|
|
// the equation may be incorrect - needs to be for a non-ldda
|
4272 |
|
|
//SC assign quad_asi_non_ldstda = quad_asi_g & lsu_alt_space_g & ~ldst_dbl_g &
|
4273 |
|
|
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) ;
|
4274 |
|
|
// need to put in similar exception for binit st
|
4275 |
|
|
//SC wire binit_asi_non_ldda ;
|
4276 |
|
|
//SC assign binit_asi_non_ldda = binit_quad_asi_g & lsu_alt_space_g & ~ldst_dbl_g &
|
4277 |
|
|
//SC (ld_inst_vld_unflushed) ;
|
4278 |
|
|
//SC wire blk_asi_non_ldstdfa ;
|
4279 |
|
|
//SC assign blk_asi_non_ldstdfa = blk_asi_g & lsu_alt_space_g &
|
4280 |
|
|
//SC ~(ldst_dbl_g & fp_ldst_g) & (ld_inst_vld_unflushed | st_inst_vld_unflushed) ;
|
4281 |
|
|
|
4282 |
|
|
// trap on illegal asi
|
4283 |
|
|
//SC wire illegal_asi_trap_g ;
|
4284 |
|
|
//SC assign illegal_asi_trap_g =
|
4285 |
|
|
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) &
|
4286 |
|
|
//SC lsu_alt_space_g & ~recognized_asi_g & lsu_inst_vld_w ;
|
4287 |
|
|
|
4288 |
|
|
// This can be pushed back into previous cycle.
|
4289 |
|
|
//SC wire wr_to_strm_sync ;
|
4290 |
|
|
//SC assign wr_to_strm_sync =
|
4291 |
|
|
//SC strm_asi & ((ldst_va_g[7:0] == 8'hA0) | (ldst_va_g[7:0] == 8'h68)) &
|
4292 |
|
|
//SC st_inst_vld_unflushed & lsu_alt_space_g ;
|
4293 |
|
|
|
4294 |
|
|
// This should not be double-anded with tlb_tte_vld_g. Check !!!
|
4295 |
|
|
//SC assign daccess_excptn =
|
4296 |
|
|
//SC ((priv_pg_usr_mode | as_if_usr_priv_pg | nfo_pg_nonnfo_asi |
|
4297 |
|
|
//SC atm_access_w_nc | atm_access_unsup_asi))
|
4298 |
|
|
//SC & tlb_tte_vld_g |
|
4299 |
|
|
//SC spec_access_epage |
|
4300 |
|
|
//SC asi_related_trap_g | quad_asi_non_ldstda | tlb_daccess_excptn_g |
|
4301 |
|
|
//SC illegal_asi_trap_g | spv_use_hpv | binit_asi_non_ldda | wr_to_strm_sync |
|
4302 |
|
|
//SC blk_asi_non_ldstdfa ;
|
4303 |
|
|
|
4304 |
|
|
// HPV Changes
|
4305 |
|
|
// Push back into previous stage.
|
4306 |
|
|
// qualification with hpv_priv and hpstate_en required to ensure hypervisor
|
4307 |
|
|
// is not trying to access.
|
4308 |
|
|
|
4309 |
|
|
//assign hpv_priv_e =
|
4310 |
|
|
// thread0_e ? tlu_lsu_hpv_priv[0] :
|
4311 |
|
|
// thread1_e ? tlu_lsu_hpv_priv[1] :
|
4312 |
|
|
// thread2_e ? tlu_lsu_hpv_priv[2] :
|
4313 |
|
|
// tlu_lsu_hpv_priv[3] ;
|
4314 |
|
|
|
4315 |
|
|
// Timing change :
|
4316 |
|
|
|
4317 |
|
|
wire [3:0] hpv_priv_d1 ;
|
4318 |
|
|
wire [3:0] hpstate_en_d1 ;
|
4319 |
|
|
|
4320 |
|
|
dff_s #(8) hpv_stgd1 (
|
4321 |
|
|
.din ({tlu_lsu_hpv_priv[3:0],tlu_lsu_hpstate_en[3:0]}),
|
4322 |
|
|
.q ({hpv_priv_d1[3:0],hpstate_en_d1[3:0]}),
|
4323 |
|
|
.clk (clk),
|
4324 |
|
|
.se (se), .si (), .so ()
|
4325 |
|
|
);
|
4326 |
|
|
|
4327 |
|
|
mux4ds #(1) hpv_priv_e_mux (
|
4328 |
|
|
.in0 (hpv_priv_d1[0]),
|
4329 |
|
|
.in1 (hpv_priv_d1[1]),
|
4330 |
|
|
.in2 (hpv_priv_d1[2]),
|
4331 |
|
|
.in3 (hpv_priv_d1[3]),
|
4332 |
|
|
.sel0 (thread0_e),
|
4333 |
|
|
.sel1 (thread1_e),
|
4334 |
|
|
.sel2 (thread2_e),
|
4335 |
|
|
.sel3 (thread3_e),
|
4336 |
|
|
.dout (hpv_priv_e)
|
4337 |
|
|
);
|
4338 |
|
|
|
4339 |
|
|
//assign hpstate_en_e =
|
4340 |
|
|
// thread0_e ? tlu_lsu_hpstate_en[0] :
|
4341 |
|
|
// thread1_e ? tlu_lsu_hpstate_en[1] :
|
4342 |
|
|
// thread2_e ? tlu_lsu_hpstate_en[2] :
|
4343 |
|
|
// tlu_lsu_hpstate_en[3] ;
|
4344 |
|
|
|
4345 |
|
|
mux4ds #(1) hpstate_en_e_mux (
|
4346 |
|
|
.in0 (hpstate_en_d1[0]),
|
4347 |
|
|
.in1 (hpstate_en_d1[1]),
|
4348 |
|
|
.in2 (hpstate_en_d1[2]),
|
4349 |
|
|
.in3 (hpstate_en_d1[3]),
|
4350 |
|
|
.sel0 (thread0_e),
|
4351 |
|
|
.sel1 (thread1_e),
|
4352 |
|
|
.sel2 (thread2_e),
|
4353 |
|
|
.sel3 (thread3_e),
|
4354 |
|
|
.dout (hpstate_en_e)
|
4355 |
|
|
);
|
4356 |
|
|
|
4357 |
|
|
dff_s #(2) hpv_stgm (
|
4358 |
|
|
.din ({hpv_priv_e, hpstate_en_e}),
|
4359 |
|
|
.q ({hpv_priv_m, hpstate_en_m}),
|
4360 |
|
|
.clk (clk),
|
4361 |
|
|
.se (se), .si (), .so ()
|
4362 |
|
|
);
|
4363 |
|
|
|
4364 |
|
|
//dff #(2) hpv_stgg (
|
4365 |
|
|
// .din ({hpv_priv_m, hpstate_en_m}),
|
4366 |
|
|
// .q ({hpv_priv, hpstate_en}),
|
4367 |
|
|
// .clk (clk),
|
4368 |
|
|
// .se (se), .si (), .so ()
|
4369 |
|
|
// );
|
4370 |
|
|
|
4371 |
|
|
/*assign priv_action = (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~lsu_asi_state[7] &
|
4372 |
|
|
~pstate_priv & ~(hpv_priv & hpstate_en) & lsu_alt_space_g ;*/
|
4373 |
|
|
// Generate a stage earlier
|
4374 |
|
|
//SC assign priv_action_m = (ld_inst_vld_m | st_inst_vld_m) & ~lsu_dctl_asi_state_m[7] &
|
4375 |
|
|
//SC ~pstate_priv_m & ~(hpv_priv_m & hpstate_en_m) & lsu_alt_space_m ;
|
4376 |
|
|
|
4377 |
|
|
//SC dff pact_stgg (
|
4378 |
|
|
//SC .din (priv_action_m),
|
4379 |
|
|
//SC .q (priv_action),
|
4380 |
|
|
//SC .clk (clk),
|
4381 |
|
|
//SC .se (se), .si (), .so ()
|
4382 |
|
|
//SC );
|
4383 |
|
|
|
4384 |
|
|
// Take data_access exception if supervisor uses hypervisor asi
|
4385 |
|
|
//SC wire hpv_asi_range ;
|
4386 |
|
|
//SC assign hpv_asi_range =
|
4387 |
|
|
//SC ~lsu_asi_state[7] & (
|
4388 |
|
|
//SC (~lsu_asi_state[6] & lsu_asi_state[5] & lsu_asi_state[4]) | // 0x3?
|
4389 |
|
|
//SC ( lsu_asi_state[6])); // 0x4?,5?,6?,7?
|
4390 |
|
|
|
4391 |
|
|
// Take data_access exception if supervisor uses hypervisor asi
|
4392 |
|
|
//SC `ifdef SPARC_HPV_EN
|
4393 |
|
|
//SC assign spv_use_hpv = (ld_inst_vld_unflushed | st_inst_vld_unflushed) &
|
4394 |
|
|
//SC hpv_asi_range &
|
4395 |
|
|
//SC //~lsu_asi_state[7] & lsu_asi_state[6] & lsu_asi_state[5] & // 0x30-0x7f
|
4396 |
|
|
//SC pstate_priv & ~hpv_priv & lsu_alt_space_g ;
|
4397 |
|
|
//SC `else
|
4398 |
|
|
//SC assign spv_use_hpv = 1'b0 ;
|
4399 |
|
|
//SC `endif
|
4400 |
|
|
|
4401 |
|
|
|
4402 |
|
|
// EARLY TRAPS
|
4403 |
|
|
|
4404 |
|
|
// memory address not aligned
|
4405 |
|
|
//SC wire qw_align_addr,blk_align_addr ;
|
4406 |
|
|
//SC assign hw_align_addr = ~ldst_va_m[0] ; // half-word addr
|
4407 |
|
|
//SC assign wd_align_addr = ~ldst_va_m[1] & ~ldst_va_m[0] ; // word addr
|
4408 |
|
|
//SC assign dw_align_addr = ~ldst_va_m[2] & ~ldst_va_m[1] & ~ldst_va_m[0] ; // dw addr
|
4409 |
|
|
//SC assign qw_align_addr = ~ldst_va_m[3] & ~ldst_va_m[2] & ~ldst_va_m[1] & ~ldst_va_m[0] ; // qw addr
|
4410 |
|
|
//SC assign blk_align_addr =
|
4411 |
|
|
//SC ~ldst_va_m[5] & ~ldst_va_m[4] & ~ldst_va_m[3] &
|
4412 |
|
|
//SC ~ldst_va_m[2] & ~ldst_va_m[1] & ~ldst_va_m[0] ; // 64B aligned addr for block ld/st
|
4413 |
|
|
|
4414 |
|
|
//assign byte_size = ~ldst_sz_m[1] & ~ldst_sz_m[0] ; // byte size
|
4415 |
|
|
//assign hw_size = ~ldst_sz_m[1] & ldst_sz_m[0] ; // half-word size
|
4416 |
|
|
//assign wd_size = ldst_sz_m[1] & ~ldst_sz_m[0] ; // word size
|
4417 |
|
|
//assign dw_size = ldst_sz_m[1] & ldst_sz_m[0] ; // double-word size
|
4418 |
|
|
|
4419 |
|
|
//assign byte_size = byte_m;
|
4420 |
|
|
assign hw_size = hword_m;
|
4421 |
|
|
assign wd_size = word_m;
|
4422 |
|
|
assign dw_size = dword_m;
|
4423 |
|
|
|
4424 |
|
|
//SC assign mem_addr_not_align
|
4425 |
|
|
//SC = ((hw_size & ~hw_align_addr) | // half-word check
|
4426 |
|
|
//SC (wd_size & ~wd_align_addr) | // word check
|
4427 |
|
|
//SC (dw_size & ~dw_align_addr) | // double word check
|
4428 |
|
|
//SC ((quad_asi_m | binit_quad_asi_m) & lsu_alt_space_m & ldst_dbl_m & ~qw_align_addr) | // quad word check
|
4429 |
|
|
//SC (blk_asi_m & lsu_alt_space_m & fp_ldst_m & ldst_dbl_m & ~blk_align_addr)) & // 64B blk ld/st check
|
4430 |
|
|
//SC //(blk_asi_m & lsu_alt_space_m & blk_asi_m & ~blk_align_addr)) & // 64B blk ld/st check
|
4431 |
|
|
//SC (ld_inst_vld_m | st_inst_vld_m) ;
|
4432 |
|
|
|
4433 |
|
|
//SC assign stdf_maddr_not_align
|
4434 |
|
|
//SC = st_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr ;
|
4435 |
|
|
|
4436 |
|
|
//SC assign lddf_maddr_not_align
|
4437 |
|
|
//SC = ld_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr ;
|
4438 |
|
|
|
4439 |
|
|
// internal asi access by ld/st other than ldxa/stxa/lddfa/stdfa.
|
4440 |
|
|
// qual with ldst_dbl_m needed. lda and stda should take trap if accessing internal asi.
|
4441 |
|
|
//SC assign asi_internal_non_xdw
|
4442 |
|
|
//SC = (st_inst_vld_m | ld_inst_vld_m) & lsu_alt_space_m & asi_internal_m & ~(dw_size & ~ldst_dbl_m) ;
|
4443 |
|
|
|
4444 |
|
|
|
4445 |
|
|
// asi related
|
4446 |
|
|
// rd-only mmu asi requiring va decode.
|
4447 |
|
|
//SC wire mmu_rd_only_asi_wva_m ;
|
4448 |
|
|
//SC assign mmu_rd_only_asi_wva_m =
|
4449 |
|
|
//SC ((lsu_dctl_asi_state_m[7:0]==8'h58) & (
|
4450 |
|
|
//SC (ldst_va_m[8:0] == 9'h000) | // dtag_target
|
4451 |
|
|
//SC (ldst_va_m[8:0] == 9'h020))) | // dsync_far
|
4452 |
|
|
//SC ((lsu_dctl_asi_state_m[7:0]==8'h50) &
|
4453 |
|
|
//SC (ldst_va_m[8:0] == 9'h000)) ; // itag_target
|
4454 |
|
|
|
4455 |
|
|
//SC assign wr_to_rd_only_asi =
|
4456 |
|
|
//SC (mmu_rd_only_asi_wva_m |// mmu with non-unique asi
|
4457 |
|
|
//SC mmu_rd_only_asi_m | // mmu with unique asi
|
4458 |
|
|
//SC rd_only_asi_m) // non mmu
|
4459 |
|
|
//SC & st_inst_vld_m & lsu_alt_space_m ;
|
4460 |
|
|
|
4461 |
|
|
//SC assign rd_of_wr_only_asi = wr_only_asi_m & ld_inst_vld_m & lsu_alt_space_m ;
|
4462 |
|
|
//SC assign unimp_asi_used = unimp_asi_m & (ld_inst_vld_m | st_inst_vld_m) & lsu_alt_space_m ;
|
4463 |
|
|
//assign asi_related_trap_m = wr_to_rd_only_asi | rd_of_wr_only_asi | unimp_asi_used | asi_internal_non_xdw ;
|
4464 |
|
|
|
4465 |
|
|
//SC assign early_trap_vld_m = stdf_maddr_not_align | lddf_maddr_not_align | mem_addr_not_align ;
|
4466 |
|
|
|
4467 |
|
|
//SC assign lsu_tlu_misalign_addr_ldst_atm_m = early_trap_vld_m ;
|
4468 |
|
|
|
4469 |
|
|
// mux select order must be maintained
|
4470 |
|
|
//SC assign early_ttype_m[8:0] =
|
4471 |
|
|
//SC stdf_maddr_not_align ? 9'h036 :
|
4472 |
|
|
//SC lddf_maddr_not_align ? 9'h035 :
|
4473 |
|
|
//SC mem_addr_not_align ? 9'h034 : 9'hxxx ;
|
4474 |
|
|
|
4475 |
|
|
//SC dff #(11) etrp_stgg (
|
4476 |
|
|
//SC .din ({early_ttype_m[8:0],early_trap_vld_m,asi_related_trap_m}),
|
4477 |
|
|
//SC .q ({early_ttype_g[8:0],early_trap_vld_g,asi_related_trap_g}),
|
4478 |
|
|
//SC .clk (clk),
|
4479 |
|
|
//SC .se (se), .si (), .so ()
|
4480 |
|
|
//SC );
|
4481 |
|
|
|
4482 |
|
|
//SC wire nceen_pipe_g ;
|
4483 |
|
|
//SC assign nceen_pipe_g =
|
4484 |
|
|
//SC (thread0_g & ifu_lsu_nceen[0]) | (thread1_g & ifu_lsu_nceen[1]) |
|
4485 |
|
|
//SC (thread2_g & ifu_lsu_nceen[2]) | (thread3_g & ifu_lsu_nceen[3]) ;
|
4486 |
|
|
//SC wire nceen_fill_e,nceen_fill_m,nceen_fill_g ;
|
4487 |
|
|
//SC assign nceen_fill_e =
|
4488 |
|
|
//SC (dfill_thread0 & ifu_lsu_nceen[0]) | (dfill_thread1 & ifu_lsu_nceen[1]) |
|
4489 |
|
|
//SC (dfill_thread2 & ifu_lsu_nceen[2]) | (dfill_thread3 & ifu_lsu_nceen[3]) ;
|
4490 |
|
|
|
4491 |
|
|
//SC dff #(1) nce_stgm (
|
4492 |
|
|
//SC .din (nceen_fill_e),
|
4493 |
|
|
//SC .q (nceen_fill_m),
|
4494 |
|
|
//SC .clk (clk),
|
4495 |
|
|
//SC .se (se), .si (), .so ()
|
4496 |
|
|
//SC );
|
4497 |
|
|
|
4498 |
|
|
//SC dff #(1) nce_stgg (
|
4499 |
|
|
//SC .din (nceen_fill_m),
|
4500 |
|
|
//SC .q (nceen_fill_g),
|
4501 |
|
|
//SC .clk (clk),
|
4502 |
|
|
//SC .se (se), .si (), .so ()
|
4503 |
|
|
//SC );
|
4504 |
|
|
|
4505 |
|
|
//SC assign daccess_error = 1'b0 ;
|
4506 |
|
|
// Commented out currently for timing reasons. This needs to be
|
4507 |
|
|
// rolled into the ttype_vld sent to the tlu, but can be left out
|
4508 |
|
|
// of the flush sent to the remaining units.
|
4509 |
|
|
/*((tte_data_perror_unc) & nceen_pipe_g & // on xslate
|
4510 |
|
|
~(early_trap_vld_g | priv_action | va_wtchpt_match | dmmu_miss_g)) |
|
4511 |
|
|
tlb_asi_unc_err_g | // asi read
|
4512 |
|
|
(unc_err_trap_g & nceen_fill_g) | // cache data
|
4513 |
|
|
tlb_daccess_error_g ; // tlb not writeable */
|
4514 |
|
|
|
4515 |
|
|
//SC assign lsu_tlu_async_dacc_err_g = unc_err_trap_g | tlb_asi_unc_err_g ;
|
4516 |
|
|
|
4517 |
|
|
//SC assign lsu_tlu_dmmu_miss_g = dmmu_miss_g ;
|
4518 |
|
|
|
4519 |
|
|
wire cam_real_m ;
|
4520 |
|
|
dff_s real_stgm (
|
4521 |
|
|
.din (lsu_dtlb_cam_real_e),
|
4522 |
|
|
.q (cam_real_m),
|
4523 |
|
|
.clk (clk),
|
4524 |
|
|
.se (se), .si (), .so ()
|
4525 |
|
|
);
|
4526 |
|
|
|
4527 |
|
|
// dff real_stgg (
|
4528 |
|
|
// .din (cam_real_m),
|
4529 |
|
|
// .q (cam_real_g),
|
4530 |
|
|
// .clk (clk),
|
4531 |
|
|
// .se (se), .si (), .so ()
|
4532 |
|
|
// );
|
4533 |
|
|
|
4534 |
|
|
assign lsu_tlu_nonalt_ldst_m = (st_inst_vld_m | ld_inst_vld_m) & ~lsu_alt_space_m ;
|
4535 |
|
|
assign lsu_tlu_xslating_ldst_m = (st_inst_vld_m | ld_inst_vld_m) &
|
4536 |
|
|
(((~asi_internal_m & recognized_asi_m) & lsu_alt_space_m) | // Bug 4327
|
4537 |
|
|
~lsu_alt_space_m) ;
|
4538 |
|
|
|
4539 |
|
|
assign ctxt_sel_e[0] = thread_pctxt ;
|
4540 |
|
|
assign ctxt_sel_e[1] = thread_sctxt ;
|
4541 |
|
|
assign ctxt_sel_e[2] =
|
4542 |
|
|
thread_nctxt |
|
4543 |
|
|
(~(thread_pctxt | thread_sctxt) & // default to nucleus - translating asi
|
4544 |
|
|
~(alt_space_e & (asi_internal_e | ~recognized_asi_e ))) ; //bug3660
|
4545 |
|
|
// nontranslating asi to select 11 in CT
|
4546 |
|
|
// field of dsfsr.
|
4547 |
|
|
|
4548 |
|
|
dff_s #(3) ctxsel (
|
4549 |
|
|
.din (ctxt_sel_e[2:0]),
|
4550 |
|
|
.q (lsu_tlu_ctxt_sel_m[2:0]),
|
4551 |
|
|
.clk (clk),
|
4552 |
|
|
.se (se), .si (), .so ()
|
4553 |
|
|
);
|
4554 |
|
|
|
4555 |
|
|
assign lsu_tlu_nucleus_ctxt_m = lsu_tlu_ctxt_sel_m[2] ;
|
4556 |
|
|
|
4557 |
|
|
assign lsu_tlu_write_op_m = st_inst_vld_m | atomic_m ;
|
4558 |
|
|
|
4559 |
|
|
// va_oor_m check needs to be in case of bypass, pstate.am=1, internal and illegal asi.
|
4560 |
|
|
// pstate.am squashing is done locally in tlu.
|
4561 |
|
|
|
4562 |
|
|
assign lsu_tlu_squash_va_oor_m =
|
4563 |
|
|
dtlb_bypass_m | // bypass
|
4564 |
|
|
//sta_internal_m | lda_internal_m | // internal asi
|
4565 |
|
|
(asi_internal_m & lsu_alt_space_m) | // Bug 5156
|
4566 |
|
|
(~recognized_asi_tmp & lsu_alt_space_m) ; // illegal asi // Timing change.
|
4567 |
|
|
|
4568 |
|
|
assign lsu_squash_va_oor_m = lsu_tlu_squash_va_oor_m;
|
4569 |
|
|
|
4570 |
|
|
//=========================================================================================
|
4571 |
|
|
// Generate Flush Pipe
|
4572 |
|
|
//=========================================================================================
|
4573 |
|
|
|
4574 |
|
|
//SC wire other_flush_pipe_w ;
|
4575 |
|
|
// lsu_tlu_ttype_vld needs to be optimized in terms of timing.
|
4576 |
|
|
//SC assign other_flush_pipe_w = tlu_early_flush_pipe_w | (lsu_tlu_ttype_vld_m2 & lsu_inst_vld_w);
|
4577 |
|
|
//SC assign lsu_ifu_flush_pipe_w = other_flush_pipe_w ;
|
4578 |
|
|
//SC assign lsu_exu_flush_pipe_w = other_flush_pipe_w ;
|
4579 |
|
|
//SC assign lsu_ffu_flush_pipe_w = other_flush_pipe_w ;
|
4580 |
|
|
|
4581 |
|
|
//SC //assign lsu_flush_pipe_w = other_flush_pipe_w | ifu_tlu_flush_w ;
|
4582 |
|
|
|
4583 |
|
|
//=========================================================================================
|
4584 |
|
|
// Early Traps to SPU
|
4585 |
|
|
//=========================================================================================
|
4586 |
|
|
|
4587 |
|
|
// detect st to ma/strm sync - data-access exception.
|
4588 |
|
|
//SC wire st_to_sync_dexcp_m ;
|
4589 |
|
|
// qual with alt_space not required - spu will do it.
|
4590 |
|
|
//SC assign st_to_sync_dexcp_m =
|
4591 |
|
|
//SC strm_asi_m & ((ldst_va_m[7:0] == 8'ha0) | (ldst_va_m[7:0] == 8'h68)) & st_inst_vld_m ;
|
4592 |
|
|
|
4593 |
|
|
//SC wire spu_early_flush_m ;
|
4594 |
|
|
|
4595 |
|
|
//SC assign spu_early_flush_m =
|
4596 |
|
|
//SC priv_action_m |
|
4597 |
|
|
//SC mem_addr_not_align |
|
4598 |
|
|
//SC st_to_sync_dexcp_m ;
|
4599 |
|
|
|
4600 |
|
|
//SC dff eflushspu_g (
|
4601 |
|
|
//SC .din (spu_early_flush_m),
|
4602 |
|
|
//SC .q (lsu_spu_early_flush_g),
|
4603 |
|
|
//SC .clk (clk),
|
4604 |
|
|
//SC .se (se), .si (), .so ()
|
4605 |
|
|
//SC );
|
4606 |
|
|
|
4607 |
|
|
//SC dff eflushtlu_g (
|
4608 |
|
|
//SC .din (spu_early_flush_m),
|
4609 |
|
|
//SC .q (lsu_tlu_early_flush_w),
|
4610 |
|
|
//SC .clk (clk),
|
4611 |
|
|
//SC .se (se), .si (), .so ()
|
4612 |
|
|
//SC );
|
4613 |
|
|
|
4614 |
|
|
//=========================================================================================
|
4615 |
|
|
// Parity Error Checking
|
4616 |
|
|
//=========================================================================================
|
4617 |
|
|
|
4618 |
|
|
// DCache Parity Error
|
4619 |
|
|
// - Parity Check is done for entire 64b. No attempt is made to match on size. A
|
4620 |
|
|
// parity error will force a miss and refetch a line to the same way of the cache.
|
4621 |
|
|
// - Logging of error is done in g-stage of issue.
|
4622 |
|
|
// - Trap taken on data return
|
4623 |
|
|
|
4624 |
|
|
wire dcache_perr_en ;
|
4625 |
|
|
assign dcache_perr_en =
|
4626 |
|
|
dcache_enable_g & ~(asi_internal_g & lsu_alt_space_g) &
|
4627 |
|
|
~atomic_g &
|
4628 |
|
|
// dcache_rd_parity_err qualified with cache_way_hit - could be x.
|
4629 |
|
|
(lsu_dtlb_bypass_g | (~lsu_dtlb_bypass_g & tlb_cam_hit_g)) ;
|
4630 |
|
|
assign dcache_rd_parity_error = dcache_rparity_err_wb & dcache_perr_en ;
|
4631 |
|
|
|
4632 |
|
|
// dtag parity error gets priority over dcache priority.
|
4633 |
|
|
assign lsu_dcache_data_perror_g =
|
4634 |
|
|
dcache_rd_parity_error & ld_inst_vld_unflushed & lsu_inst_vld_w & ~dtag_perror_g &
|
4635 |
|
|
dcache_perr_en ;
|
4636 |
|
|
// dcache_enable_g & ~(asi_internal_g & lsu_alt_space_g) &
|
4637 |
|
|
// ~atomic_g ;
|
4638 |
|
|
|
4639 |
|
|
// DTLB Parity Errors.
|
4640 |
|
|
// ASI read of Tag/Data :
|
4641 |
|
|
// - uncorrectible error
|
4642 |
|
|
// - logging occurs on read.
|
4643 |
|
|
// - precise trap is taken when ldxa completes if nceen set.
|
4644 |
|
|
// - if not set then ldxa is allowed to complete.
|
4645 |
|
|
// CAM Read of Tag/Data :
|
4646 |
|
|
// - correctible if locked bit not set.
|
4647 |
|
|
// - takes disrupting trap later.
|
4648 |
|
|
// - uncorrectible if locked bit set.
|
4649 |
|
|
// - both are treated as precise traps.
|
4650 |
|
|
// - if errors not enabled, then load completes as if hit in L1.
|
4651 |
|
|
// ** TLB error will cause a trap which will preclude concurrent dcache,dtag **
|
4652 |
|
|
// ** parity errors. **
|
4653 |
|
|
|
4654 |
|
|
//SC assign tte_data_parity_error =
|
4655 |
|
|
//SC tlb_rd_tte_data_parity ^ lsu_rd_tte_data_parity ;
|
4656 |
|
|
//SC assign tte_tag_parity_error =
|
4657 |
|
|
//SC tlb_rd_tte_tag_parity ^ lsu_rd_tte_tag_parity ;
|
4658 |
|
|
|
4659 |
|
|
// cam related tte data parity error - error assumed correctible if locked
|
4660 |
|
|
// bit is not set. Will cause a dmmu_miss for correction.
|
4661 |
|
|
// qualify with cam_hit ??
|
4662 |
|
|
//SC assign tte_data_perror_corr =
|
4663 |
|
|
//SC tte_data_parity_error & ~tlb_rd_tte_data_locked & tlb_tte_vld_g &
|
4664 |
|
|
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w ;
|
4665 |
|
|
// same as above except error is treated as uncorrectible. This is to be posted to
|
4666 |
|
|
// error status register which will cause a disrupting trap later.
|
4667 |
|
|
//SC assign tte_data_perror_unc =
|
4668 |
|
|
//SC tte_data_parity_error & tlb_rd_tte_data_locked & tlb_tte_vld_g &
|
4669 |
|
|
//SC (ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w ;
|
4670 |
|
|
// Asi rd parity error detection
|
4671 |
|
|
//SC assign asi_tte_data_perror =
|
4672 |
|
|
//SC tte_data_parity_error & data_rd_vld_g ;
|
4673 |
|
|
// For data tte read, both tag and data arrays are read.
|
4674 |
|
|
// Parity error on asi read of tag should not be reported.
|
4675 |
|
|
//SC assign asi_tte_tag_perror =
|
4676 |
|
|
//SC tte_tag_parity_error & tag_rd_vld_g & ~data_rd_vld_g ;
|
4677 |
|
|
//SC assign lsu_tlu_asi_rd_unc = asi_tte_data_perror | asi_tte_tag_perror ;
|
4678 |
|
|
|
4679 |
|
|
// asi rd parity errors need to be reported thru asi bus
|
4680 |
|
|
/*assign lsu_ifu_tlb_data_ce = tte_data_perror_corr ;
|
4681 |
|
|
assign lsu_ifu_tlb_data_ue = tte_data_perror_unc | asi_tte_data_perror ;
|
4682 |
|
|
assign lsu_ifu_tlb_tag_ue = asi_tte_tag_perror ; */
|
4683 |
|
|
|
4684 |
|
|
|
4685 |
|
|
//SC wire tlb_data_ue_g ;
|
4686 |
|
|
//SC assign tlb_data_ue_g = tte_data_perror_unc | asi_tte_data_perror ;
|
4687 |
|
|
|
4688 |
|
|
//SC dff #(3) terr_stgd1 (
|
4689 |
|
|
//SC .din ({tte_data_perror_corr,tlb_data_ue_g,asi_tte_tag_perror}),
|
4690 |
|
|
//SC .q ({lsu_ifu_tlb_data_ce,lsu_ifu_tlb_data_ue,lsu_ifu_tlb_tag_ue}),
|
4691 |
|
|
//SC .clk (clk),
|
4692 |
|
|
//SC .se (se), .si (), .so ()
|
4693 |
|
|
//SC );
|
4694 |
|
|
|
4695 |
|
|
// Dtag Parity Error
|
4696 |
|
|
// - corrected thru special mechanism
|
4697 |
|
|
// - correctible error
|
4698 |
|
|
// - Trap taken on data return
|
4699 |
|
|
|
4700 |
|
|
// move parity error calculation to g stage
|
4701 |
|
|
|
4702 |
|
|
dff_s #(4) dva_vld_g_ff (
|
4703 |
|
|
.din (dva_vld_m[3:0]),
|
4704 |
|
|
.q (dva_vld_g[3:0]),
|
4705 |
|
|
.clk (clk),
|
4706 |
|
|
.se (se), .si (), .so ()
|
4707 |
|
|
);
|
4708 |
|
|
|
4709 |
|
|
assign dva_vld_m_bf[3:0] = dva_vld_m[3:0];
|
4710 |
|
|
|
4711 |
|
|
wire dtag_perr_en ;
|
4712 |
|
|
assign dtag_perr_en =
|
4713 |
|
|
dcache_enable_g & ~(asi_internal_g & lsu_alt_space_g) & // Bug 3541
|
4714 |
|
|
~(lsu_alt_space_g & blk_asi_g) & // Bug 3926.
|
4715 |
|
|
~atomic_g & // Bug 4274,4297
|
4716 |
|
|
~pref_inst_g ; // Bug 5046
|
4717 |
|
|
assign dtag_parity_error[0] =
|
4718 |
|
|
lsu_rd_dtag_parity_g[0] & dva_vld_g[0] & dtag_perr_en;
|
4719 |
|
|
assign dtag_parity_error[1] =
|
4720 |
|
|
lsu_rd_dtag_parity_g[1] & dva_vld_g[1] & dtag_perr_en ;
|
4721 |
|
|
assign dtag_parity_error[2] =
|
4722 |
|
|
lsu_rd_dtag_parity_g[2] & dva_vld_g[2] & dtag_perr_en ;
|
4723 |
|
|
assign dtag_parity_error[3] =
|
4724 |
|
|
lsu_rd_dtag_parity_g[3] & dva_vld_g[3] & dtag_perr_en ;
|
4725 |
|
|
|
4726 |
|
|
assign dtag_perror_g = |dtag_parity_error[3:0] ;
|
4727 |
|
|
assign lsu_dcache_tag_perror_g =
|
4728 |
|
|
(|dtag_parity_error[3:0]) & ld_inst_vld_unflushed & lsu_inst_vld_w &
|
4729 |
|
|
// Correction pkt should not be generated to io.
|
4730 |
|
|
~(tlb_pgnum[39] & (lsu_dtlb_bypass_g | (~lsu_dtlb_bypass_g & tlb_cam_hit_g))) ;
|
4731 |
|
|
// (|dtag_parity_error[3:0]) & ld_inst_vld_unflushed & lsu_inst_vld_w &
|
4732 |
|
|
// ~(lsu_alt_space_g & blk_asi_g) & // Bug 3926.
|
4733 |
|
|
// // Correction pkt should not be generated to io.
|
4734 |
|
|
// ~(tlb_pgnum[39] & (lsu_dtlb_bypass_g | (~lsu_dtlb_bypass_g & tlb_cam_hit_g))) &
|
4735 |
|
|
// ~atomic_g ; // Bug 4274,4297
|
4736 |
|
|
//=========================================================================================
|
4737 |
|
|
// Error Related Traps
|
4738 |
|
|
//=========================================================================================
|
4739 |
|
|
|
4740 |
|
|
//bug6382/eco6621
|
4741 |
|
|
dff_s #(2) derrtrp_stgm (
|
4742 |
|
|
.din ({lsu_cpx_ld_dtag_perror_e & ~ignore_fill, lsu_cpx_ld_dcache_perror_e & ~ignore_fill}),
|
4743 |
|
|
.q ({dtag_error_m,dcache_error_m}),
|
4744 |
|
|
.clk (clk),
|
4745 |
|
|
.se (se), .si (), .so ()
|
4746 |
|
|
);
|
4747 |
|
|
|
4748 |
|
|
dff_s #(2) derrtrp_stgg (
|
4749 |
|
|
.din ({dtag_error_m,dcache_error_m}),
|
4750 |
|
|
.q ({dtag_error_g,dcache_error_g}),
|
4751 |
|
|
.clk (clk),
|
4752 |
|
|
.se (se), .si (), .so ()
|
4753 |
|
|
);
|
4754 |
|
|
|
4755 |
|
|
dff_s #(2) derrtrp_stgw2 (
|
4756 |
|
|
.din ({dtag_error_g,dcache_error_g}),
|
4757 |
|
|
.q ({dtag_error_w2,dcache_error_w2}),
|
4758 |
|
|
.clk (clk),
|
4759 |
|
|
.se (se), .si (), .so ()
|
4760 |
|
|
);
|
4761 |
|
|
|
4762 |
|
|
assign lsu_ifu_dcache_data_perror = dcache_error_w2 & ~bld_squash_err_w2; //bug6382/eco6621
|
4763 |
|
|
assign lsu_ifu_dcache_tag_perror = dtag_error_w2 ;
|
4764 |
|
|
|
4765 |
|
|
assign l2_unc_error_e = lsu_cpx_pkt_ld_err[1] & l2fill_vld_e & ~ignore_fill ; // Bug 4998
|
4766 |
|
|
assign l2_corr_error_e = lsu_cpx_pkt_ld_err[0] & l2fill_vld_e & ~ignore_fill ;
|
4767 |
|
|
|
4768 |
|
|
dff_s #(2) lerrtrp_stgm (
|
4769 |
|
|
.din ({l2_unc_error_e,l2_corr_error_e}),
|
4770 |
|
|
.q ({l2_unc_error_m,l2_corr_error_m}),
|
4771 |
|
|
.clk (clk),
|
4772 |
|
|
.se (se), .si (), .so ()
|
4773 |
|
|
);
|
4774 |
|
|
|
4775 |
|
|
dff_s #(2) lerrtrp_stgg (
|
4776 |
|
|
.din ({l2_unc_error_m,l2_corr_error_m}),
|
4777 |
|
|
.q ({l2_unc_error_g,l2_corr_error_g}),
|
4778 |
|
|
.clk (clk),
|
4779 |
|
|
.se (se), .si (), .so ()
|
4780 |
|
|
);
|
4781 |
|
|
|
4782 |
|
|
dff_s #(2) lerrtrp_stgw2 (
|
4783 |
|
|
.din ({l2_unc_error_g,l2_corr_error_g}),
|
4784 |
|
|
.q ({l2_unc_error_w2,l2_corr_error_w2}),
|
4785 |
|
|
.clk (clk),
|
4786 |
|
|
.se (se), .si (), .so ()
|
4787 |
|
|
);
|
4788 |
|
|
|
4789 |
|
|
assign lsu_ifu_l2_unc_error = // Bug 4315
|
4790 |
|
|
(l2_unc_error_w2 | bld_unc_err_pend_w2) & ~lsu_ifu_err_addr_b39 & ~bld_squash_err_w2 ;
|
4791 |
|
|
assign lsu_ifu_l2_corr_error =
|
4792 |
|
|
(l2_corr_error_w2 | bld_corr_err_pend_w2) & ~bld_squash_err_w2 ;
|
4793 |
|
|
|
4794 |
|
|
wire fill_err_trap_e ;
|
4795 |
|
|
|
4796 |
|
|
//assign unc_err_trap_e =
|
4797 |
|
|
assign fill_err_trap_e =
|
4798 |
|
|
(lsu_cpx_pkt_ld_err[1] & l2fill_vld_e) ;
|
4799 |
|
|
/*(lsu_cpx_atm_st_err[1] & lsu_atm_st_cmplt_e)) &
|
4800 |
|
|
((dfill_thread0 & ifu_lsu_nceen[0]) |
|
4801 |
|
|
(dfill_thread1 & ifu_lsu_nceen[1]) |
|
4802 |
|
|
(dfill_thread2 & ifu_lsu_nceen[2]) |
|
4803 |
|
|
(dfill_thread3 & ifu_lsu_nceen[3])) ; */ // Bug 3624
|
4804 |
|
|
|
4805 |
|
|
assign unc_err_trap_e = fill_err_trap_e ;
|
4806 |
|
|
|
4807 |
|
|
/*assign corr_err_trap_e =
|
4808 |
|
|
((lsu_cpx_pkt_ld_err[0] | lsu_cpx_ld_dtag_perror_e | lsu_cpx_ld_dcache_perror_e) &
|
4809 |
|
|
l2fill_vld_e) |
|
4810 |
|
|
(lsu_cpx_atm_st_err[0] & lsu_atm_st_cmplt_e)) &
|
4811 |
|
|
& ~unc_err_trap_e &
|
4812 |
|
|
((dfill_thread0 & ifu_lsu_ceen[0]) |
|
4813 |
|
|
(dfill_thread1 & ifu_lsu_ceen[1]) |
|
4814 |
|
|
(dfill_thread2 & ifu_lsu_ceen[2]) |
|
4815 |
|
|
(dfill_thread3 & ifu_lsu_ceen[3])) ; */
|
4816 |
|
|
|
4817 |
|
|
|
4818 |
|
|
dff_s #(1) errtrp_stgm (
|
4819 |
|
|
.din ({unc_err_trap_e}),
|
4820 |
|
|
.q ({unc_err_trap_m}),
|
4821 |
|
|
.clk (clk),
|
4822 |
|
|
.se (se), .si (), .so ()
|
4823 |
|
|
);
|
4824 |
|
|
|
4825 |
|
|
dff_s #(1) errtrp_stgg (
|
4826 |
|
|
.din ({unc_err_trap_m}),
|
4827 |
|
|
.q ({unc_err_trap_g}),
|
4828 |
|
|
.clk (clk),
|
4829 |
|
|
.se (se), .si (), .so ()
|
4830 |
|
|
);
|
4831 |
|
|
|
4832 |
|
|
// The tlu should source demap_thrid for all tlb operations !!!
|
4833 |
|
|
dff_s #(2) filla_stgm (
|
4834 |
|
|
.din ({lsu_dfill_tid_e[1:0]}),
|
4835 |
|
|
.q ({dfill_tid_m[1:0]}),
|
4836 |
|
|
.clk (clk),
|
4837 |
|
|
.se (se), .si (), .so ()
|
4838 |
|
|
);
|
4839 |
|
|
|
4840 |
|
|
dff_s #(2) filla_stgg (
|
4841 |
|
|
.din ({dfill_tid_m[1:0]}),
|
4842 |
|
|
.q ({dfill_tid_g[1:0]}),
|
4843 |
|
|
.clk (clk),
|
4844 |
|
|
.se (se), .si (), .so ()
|
4845 |
|
|
);
|
4846 |
|
|
|
4847 |
|
|
|
4848 |
|
|
|
4849 |
|
|
//=========================================================================================
|
4850 |
|
|
// LSU to IRF Data Bypass Control
|
4851 |
|
|
//=========================================================================================
|
4852 |
|
|
|
4853 |
|
|
assign spu_trap = spu_lsu_unc_error_w2 ;
|
4854 |
|
|
assign spu_trap0 = spu_trap & spu_ldxa_thread0_w2 ;
|
4855 |
|
|
assign spu_trap1 = spu_trap & spu_ldxa_thread1_w2 ;
|
4856 |
|
|
assign spu_trap2 = spu_trap & spu_ldxa_thread2_w2 ;
|
4857 |
|
|
assign spu_trap3 = spu_trap & spu_ldxa_thread3_w2 ;
|
4858 |
|
|
|
4859 |
|
|
assign spu_ttype[6:0] = spu_lsu_int_w2 ? 7'h70 : 7'h32 ;
|
4860 |
|
|
|
4861 |
|
|
dff_s #(2) lfraw_stgw2 (
|
4862 |
|
|
.din ({ld_inst_vld_g,fp_ldst_g}),
|
4863 |
|
|
.q ({ld_inst_vld_w2,fp_ldst_w2}),
|
4864 |
|
|
.clk (clk),
|
4865 |
|
|
.se (se), .si (), .so ()
|
4866 |
|
|
);
|
4867 |
|
|
|
4868 |
|
|
dff_s #(2) lfraw_stgw3 (
|
4869 |
|
|
.din ({ld_stb_full_raw_w2, ld_inst_vld_w2}),
|
4870 |
|
|
.q ({ld_stb_full_raw_w3, ld_inst_vld_w3}),
|
4871 |
|
|
.clk (clk),
|
4872 |
|
|
.se (se), .si (), .so ()
|
4873 |
|
|
);
|
4874 |
|
|
|
4875 |
|
|
// Delay all ldbyp*vld_en by a cycle for write of unc error
|
4876 |
|
|
//dff #(4) lbypen_stgd1 (
|
4877 |
|
|
// .din ({ldbyp0_vld_en,ldbyp1_vld_en,ldbyp2_vld_en,ldbyp3_vld_en}),
|
4878 |
|
|
// .q ({ldbyp0_vld_en_d1,ldbyp1_vld_en_d1,ldbyp2_vld_en_d1,ldbyp3_vld_en_d1}),
|
4879 |
|
|
// .clk (clk),
|
4880 |
|
|
// .se (se), .si (), .so ()
|
4881 |
|
|
// );
|
4882 |
|
|
|
4883 |
|
|
|
4884 |
|
|
wire fp_ldst_thrd0_w2,fp_ldst_thrd1_w2,fp_ldst_thrd2_w2,fp_ldst_thrd3_w2 ;
|
4885 |
|
|
wire fp_ldst_thrd0_w3,fp_ldst_thrd1_w3,fp_ldst_thrd2_w3,fp_ldst_thrd3_w3 ;
|
4886 |
|
|
wire fp_ldst_thrd0_w4,fp_ldst_thrd1_w4,fp_ldst_thrd2_w4,fp_ldst_thrd3_w4 ;
|
4887 |
|
|
wire fp_ldst_thrd0_w5,fp_ldst_thrd1_w5,fp_ldst_thrd2_w5,fp_ldst_thrd3_w5 ;
|
4888 |
|
|
|
4889 |
|
|
//RAW read STB at W3 (changed from W2)
|
4890 |
|
|
|
4891 |
|
|
dff_s #(4) fp_ldst_stg_w3 (
|
4892 |
|
|
.din ({fp_ldst_thrd0_w2,fp_ldst_thrd1_w2,fp_ldst_thrd2_w2,fp_ldst_thrd3_w2}),
|
4893 |
|
|
.q ({fp_ldst_thrd0_w3,fp_ldst_thrd1_w3,fp_ldst_thrd2_w3,fp_ldst_thrd3_w3}),
|
4894 |
|
|
.clk (clk),
|
4895 |
|
|
.se (se), .si (), .so ()
|
4896 |
|
|
);
|
4897 |
|
|
|
4898 |
|
|
dff_s #(4) fp_ldst_stg_w4 (
|
4899 |
|
|
.din ({fp_ldst_thrd0_w3,fp_ldst_thrd1_w3,fp_ldst_thrd2_w3,fp_ldst_thrd3_w3}),
|
4900 |
|
|
.q ({fp_ldst_thrd0_w4,fp_ldst_thrd1_w4,fp_ldst_thrd2_w4,fp_ldst_thrd3_w4}),
|
4901 |
|
|
.clk (clk),
|
4902 |
|
|
.se (se), .si (), .so ()
|
4903 |
|
|
);
|
4904 |
|
|
|
4905 |
|
|
dff_s #(4) fp_ldst_stg_w5 (
|
4906 |
|
|
.din ({fp_ldst_thrd0_w4,fp_ldst_thrd1_w4,fp_ldst_thrd2_w4,fp_ldst_thrd3_w4}),
|
4907 |
|
|
.q ({fp_ldst_thrd0_w5,fp_ldst_thrd1_w5,fp_ldst_thrd2_w5,fp_ldst_thrd3_w5}),
|
4908 |
|
|
.clk (clk),
|
4909 |
|
|
.se (se), .si (), .so ()
|
4910 |
|
|
);
|
4911 |
|
|
|
4912 |
|
|
// THREAD 0
|
4913 |
|
|
|
4914 |
|
|
wire tte_data_perror_unc_w2,asi_tte_data_perror_w2,asi_tte_tag_perror_w2 ;
|
4915 |
|
|
// if nceen/ceen=0, then tte_data_perror* are not logged for trap generation. Earlier error-reporting
|
4916 |
|
|
// is however never screened off.
|
4917 |
|
|
// asi_tte* however has to be logged in order to report errors thru the asiQ. Traps must be squashed.
|
4918 |
|
|
dff_s #(3) ltlbrd_w2 (
|
4919 |
|
|
.din ({tte_data_perror_unc_en,asi_tte_data_perror,asi_tte_tag_perror}),
|
4920 |
|
|
.q ({tte_data_perror_unc_w2,asi_tte_data_perror_w2,asi_tte_tag_perror_w2}),
|
4921 |
|
|
.clk (clk),
|
4922 |
|
|
.se (se), .si (), .so ()
|
4923 |
|
|
);
|
4924 |
|
|
|
4925 |
|
|
|
4926 |
|
|
// Error Table for Queue
|
4927 |
|
|
// ** In all cases; squash writes to irf.
|
4928 |
|
|
// | Error Reporting | Trap ? |
|
4929 |
|
|
// ifu_lsu_asi_rd_unc | NA;done by ifu | daccess-error |
|
4930 |
|
|
// tte_data_perror_unc_w2 | sync;in pipe | daccess-error |
|
4931 |
|
|
// tte_data_perror_corr_w2 | sync;in pipe | dmmu-miss | --> NA !! all unc.
|
4932 |
|
|
// asi_tte_data_perror_w2 | async;out of Q | daccess-error |
|
4933 |
|
|
// asi_tte_tag_perror_w2 | async;out of Q | daccess-error |
|
4934 |
|
|
|
4935 |
|
|
wire [3:0] tlb_err_en_w2 ;
|
4936 |
|
|
// used for xslate errors - enable queues
|
4937 |
|
|
//assign tlb_err_en_w2[0] = (tte_data_perror_unc_w2 | tte_data_perror_corr_w2) & thread0_w2 ;
|
4938 |
|
|
assign tlb_err_en_w2[0] = tte_data_perror_unc_w2 & thread0_w2 ;
|
4939 |
|
|
assign tlb_err_en_w2[1] = tte_data_perror_unc_w2 & thread1_w2 ;
|
4940 |
|
|
assign tlb_err_en_w2[2] = tte_data_perror_unc_w2 & thread2_w2 ;
|
4941 |
|
|
assign tlb_err_en_w2[3] = tte_data_perror_unc_w2 & thread3_w2 ;
|
4942 |
|
|
|
4943 |
|
|
assign ldbyp0_vld_rst =
|
4944 |
|
|
(reset | (ld_thrd_byp_sel_e[0])) |
|
4945 |
|
|
atm_st_cmplt0 ; // Bug 4048
|
4946 |
|
|
|
4947 |
|
|
// thread qualification required.
|
4948 |
|
|
//assign ldbyp0_vld_en = (lmq_byp_data_en_w2[0] &
|
4949 |
|
|
// ~(|lmq_byp_data_sel0[2:1])) // do not set vld for cas/stdbl
|
4950 |
|
|
// | spu_trap0 ;
|
4951 |
|
|
|
4952 |
|
|
wire atm_ld_w_uerr ;
|
4953 |
|
|
assign atm_ld_w_uerr = l2fill_vld_e & lsu_cpx_pkt_atm_st_cmplt & lsu_cpx_pkt_ld_err[1] ;
|
4954 |
|
|
|
4955 |
|
|
//bug6525 notes
|
4956 |
|
|
// spu ldxa and spu trap can async with the main pipe, and cause more than one ldbyp*_vld_en asserted
|
4957 |
|
|
// at the same cycle
|
4958 |
|
|
assign ldbyp0_vld_en = lmq_byp_data_raw_sel_d2[0] | //ld hit stb RAW bypass
|
4959 |
|
|
lmq_byp_data_sel0[3] | //ldxa (ifu, spu*, lsu)
|
4960 |
|
|
(atm_ld_w_uerr & lsu_nceen_d1[0] & dfill_thread0) | //atomic
|
4961 |
|
|
lmq_byp_data_fmx_sel[0] | //tlu ldxa
|
4962 |
|
|
tlb_err_en_w2[0] | //tlb parity err
|
4963 |
|
|
spu_trap0 ; //spu trap*
|
4964 |
|
|
|
4965 |
|
|
assign fp_ldst_thrd0_w2 = fp_ldst_w2 & thread0_w2 & ld_inst_vld_w2 ;
|
4966 |
|
|
|
4967 |
|
|
// ld valid
|
4968 |
|
|
wire ldbyp0_vld_tmp ;
|
4969 |
|
|
dffre_s #(1) ldbyp0_vld_ff (
|
4970 |
|
|
.din (ldbyp0_vld_en),
|
4971 |
|
|
.q (ldbyp0_vld_tmp),
|
4972 |
|
|
.rst (ldbyp0_vld_rst), .en (ldbyp0_vld_en),
|
4973 |
|
|
.clk (clk),
|
4974 |
|
|
.se (se), .si (), .so ()
|
4975 |
|
|
);
|
4976 |
|
|
// Bug 5379 - make ld ue invisible in q until atm st ack resets.
|
4977 |
|
|
|
4978 |
|
|
assign ldbyp0_vld = ldbyp0_vld_tmp & ~pend_atm_ld_ue[0] ;
|
4979 |
|
|
|
4980 |
|
|
|
4981 |
|
|
// assumes that rw_index is not reset at mmu.
|
4982 |
|
|
wire [6:0] misc_data_in ;
|
4983 |
|
|
wire [6:0] misc_data0,misc_data1,misc_data2,misc_data3 ;
|
4984 |
|
|
wire misc_sel ;
|
4985 |
|
|
wire [5:0] rw_index_d1 ;
|
4986 |
|
|
dff_s #(6) rwind_d1 (
|
4987 |
|
|
.din (tlu_dtlb_rw_index_g[5:0]),
|
4988 |
|
|
.q (rw_index_d1[5:0]),
|
4989 |
|
|
.clk (clk),
|
4990 |
|
|
.se (se), .si (), .so ()
|
4991 |
|
|
);
|
4992 |
|
|
assign misc_sel = asi_tte_data_perror_w2 | asi_tte_tag_perror_w2 ;
|
4993 |
|
|
assign misc_data_in[6:0] = misc_sel ? {1'b0,rw_index_d1[5:0]} : spu_ttype[6:0] ;
|
4994 |
|
|
|
4995 |
|
|
dffe_s #(9) ldbyp0_other_ff (
|
4996 |
|
|
.din ({fp_ldst_thrd0_w5,spu_trap0,misc_data_in[6:0]}), //bug6525 fix2
|
4997 |
|
|
.q ({ldbyp0_fpld,spubyp0_trap,misc_data0[6:0]}),
|
4998 |
|
|
.en (ldbyp0_vld_en),
|
4999 |
|
|
.clk (clk),
|
5000 |
|
|
.se (se), .si (), .so ()
|
5001 |
|
|
);
|
5002 |
|
|
|
5003 |
|
|
|
5004 |
|
|
dffre_s #(5) ldbyp0_err_ff (
|
5005 |
|
|
.din ({tte_data_perror_unc_w2,atm_ld_w_uerr,
|
5006 |
|
|
asi_tte_data_perror_w2,asi_tte_tag_perror_w2,ifu_lsu_asi_rd_unc}),
|
5007 |
|
|
.q ({cam_perr_unc0,pend_atm_ld_ue[0],asi_data_perr0,asi_tag_perr0,
|
5008 |
|
|
ifu_unc_err0}),
|
5009 |
|
|
.rst (ldbyp0_vld_rst), .en (ldbyp0_vld_en & ~spu_trap0 & ~lmq_byp_ldxa_sel0[1]), //bug6525 fix2
|
5010 |
|
|
.clk (clk),
|
5011 |
|
|
.se (se), .si (), .so ()
|
5012 |
|
|
);
|
5013 |
|
|
|
5014 |
|
|
|
5015 |
|
|
//assign ldbyp0_unc_err = ldbyp0_unc_err_q & ifu_lsu_nceen[0] ;
|
5016 |
|
|
|
5017 |
|
|
// THREAD 1
|
5018 |
|
|
|
5019 |
|
|
assign ldbyp1_vld_rst =
|
5020 |
|
|
(reset | (ld_thrd_byp_sel_e[1])) |
|
5021 |
|
|
atm_st_cmplt1 ; // Bug 4048
|
5022 |
|
|
|
5023 |
|
|
assign fp_ldst_thrd1_w2 = fp_ldst_w2 & thread1_w2 & ld_inst_vld_w2 ;
|
5024 |
|
|
|
5025 |
|
|
// thread qualification required.
|
5026 |
|
|
//assign ldbyp1_vld_en = (lmq_byp_data_en_w2[1] &
|
5027 |
|
|
// ~(|lmq_byp_data_sel1[2:1])) | // do not set vld for cas/stdbl
|
5028 |
|
|
// | spu_trap1 ;
|
5029 |
|
|
|
5030 |
|
|
assign ldbyp1_vld_en = lmq_byp_data_raw_sel_d2[1] |
|
5031 |
|
|
lmq_byp_data_sel1[3] |
|
5032 |
|
|
(atm_ld_w_uerr & lsu_nceen_d1[1] & dfill_thread1) |
|
5033 |
|
|
lmq_byp_data_fmx_sel[1] |
|
5034 |
|
|
tlb_err_en_w2[1] |
|
5035 |
|
|
spu_trap1 ;
|
5036 |
|
|
|
5037 |
|
|
// ld valid
|
5038 |
|
|
wire ldbyp1_vld_tmp ;
|
5039 |
|
|
dffre_s #(1) ldbyp1_vld_ff (
|
5040 |
|
|
.din (ldbyp1_vld_en),
|
5041 |
|
|
.q (ldbyp1_vld_tmp),
|
5042 |
|
|
.rst (ldbyp1_vld_rst), .en (ldbyp1_vld_en),
|
5043 |
|
|
.clk (clk),
|
5044 |
|
|
.se (se), .si (), .so ()
|
5045 |
|
|
);
|
5046 |
|
|
assign ldbyp1_vld = ldbyp1_vld_tmp & ~pend_atm_ld_ue[1] ;
|
5047 |
|
|
|
5048 |
|
|
|
5049 |
|
|
dffe_s #(9) ldbyp1_other_ff (
|
5050 |
|
|
.din ({fp_ldst_thrd1_w5,spu_trap1,misc_data_in[6:0]}), //bug6525 fix2
|
5051 |
|
|
.q ({ldbyp1_fpld,spubyp1_trap,misc_data1[6:0]}),
|
5052 |
|
|
.en (ldbyp1_vld_en),
|
5053 |
|
|
.clk (clk),
|
5054 |
|
|
.se (se), .si (), .so ()
|
5055 |
|
|
);
|
5056 |
|
|
|
5057 |
|
|
// The tlb rd unc errors are delayed a cycle wrt to ldxa_data
|
5058 |
|
|
// No reset required
|
5059 |
|
|
dffre_s #(5) ldbyp1_err_ff (
|
5060 |
|
|
.din ({tte_data_perror_unc_w2,atm_ld_w_uerr,
|
5061 |
|
|
asi_tte_data_perror_w2,asi_tte_tag_perror_w2,ifu_lsu_asi_rd_unc}),
|
5062 |
|
|
.q ({cam_perr_unc1,pend_atm_ld_ue[1],asi_data_perr1,asi_tag_perr1,
|
5063 |
|
|
ifu_unc_err1}),
|
5064 |
|
|
.rst (ldbyp1_vld_rst), .en (ldbyp1_vld_en & ~spu_trap1 & ~lmq_byp_ldxa_sel1[1]), //bug6525 fix2
|
5065 |
|
|
.clk (clk),
|
5066 |
|
|
.se (se), .si (), .so ()
|
5067 |
|
|
);
|
5068 |
|
|
|
5069 |
|
|
//assign ldbyp1_unc_err = ldbyp1_unc_err_q & ifu_lsu_nceen[1] ;
|
5070 |
|
|
|
5071 |
|
|
// THREAD 2
|
5072 |
|
|
|
5073 |
|
|
assign ldbyp2_vld_rst =
|
5074 |
|
|
(reset | (ld_thrd_byp_sel_e[2])) |
|
5075 |
|
|
atm_st_cmplt2 ; // Bug 4048
|
5076 |
|
|
|
5077 |
|
|
// thread qualification required.
|
5078 |
|
|
//assign ldbyp2_vld_en = (lmq_byp_data_en_w2[2] &
|
5079 |
|
|
// ~(|lmq_byp_data_sel2[2:1])) | // do not set vld for cas/stdbl
|
5080 |
|
|
// spu_trap2 ;
|
5081 |
|
|
|
5082 |
|
|
assign ldbyp2_vld_en = lmq_byp_data_raw_sel_d2[2] |
|
5083 |
|
|
lmq_byp_data_sel2[3] |
|
5084 |
|
|
(atm_ld_w_uerr & lsu_nceen_d1[2] & dfill_thread2) |
|
5085 |
|
|
lmq_byp_data_fmx_sel[2] |
|
5086 |
|
|
tlb_err_en_w2[2] |
|
5087 |
|
|
spu_trap2 ;
|
5088 |
|
|
|
5089 |
|
|
assign fp_ldst_thrd2_w2 = fp_ldst_w2 & thread2_w2 & ld_inst_vld_w2 ;
|
5090 |
|
|
|
5091 |
|
|
// ld valid
|
5092 |
|
|
wire ldbyp2_vld_tmp ;
|
5093 |
|
|
dffre_s #(1) ldbyp2_vld_ff (
|
5094 |
|
|
.din (ldbyp2_vld_en),
|
5095 |
|
|
.q (ldbyp2_vld_tmp),
|
5096 |
|
|
.rst (ldbyp2_vld_rst), .en (ldbyp2_vld_en),
|
5097 |
|
|
.clk (clk),
|
5098 |
|
|
.se (se), .si (), .so ()
|
5099 |
|
|
);
|
5100 |
|
|
assign ldbyp2_vld = ldbyp2_vld_tmp & ~pend_atm_ld_ue[2] ;
|
5101 |
|
|
|
5102 |
|
|
dffe_s #(9) ldbyp2_other_ff (
|
5103 |
|
|
.din ({fp_ldst_thrd2_w5,spu_trap2,misc_data_in[6:0]}), //bug6525 fix2
|
5104 |
|
|
.q ({ldbyp2_fpld,spubyp2_trap,misc_data2[6:0]}),
|
5105 |
|
|
.en (ldbyp2_vld_en),
|
5106 |
|
|
.clk (clk),
|
5107 |
|
|
.se (se), .si (), .so ()
|
5108 |
|
|
);
|
5109 |
|
|
|
5110 |
|
|
dffre_s #(5) ldbyp2_err_ff (
|
5111 |
|
|
.din ({tte_data_perror_unc_w2, atm_ld_w_uerr,
|
5112 |
|
|
asi_tte_data_perror_w2,asi_tte_tag_perror_w2,ifu_lsu_asi_rd_unc}),
|
5113 |
|
|
.q ({cam_perr_unc2,pend_atm_ld_ue[2],asi_data_perr2,asi_tag_perr2,
|
5114 |
|
|
ifu_unc_err2}),
|
5115 |
|
|
.rst (ldbyp2_vld_rst), .en (ldbyp2_vld_en & ~spu_trap2 & ~lmq_byp_ldxa_sel2[1]), //bug6525 fix2
|
5116 |
|
|
.clk (clk),
|
5117 |
|
|
.se (se), .si (), .so ()
|
5118 |
|
|
);
|
5119 |
|
|
|
5120 |
|
|
//assign ldbyp2_unc_err = ldbyp2_unc_err_q & ifu_lsu_nceen[2] ;
|
5121 |
|
|
|
5122 |
|
|
// THREAD 3
|
5123 |
|
|
|
5124 |
|
|
assign ldbyp3_vld_rst =
|
5125 |
|
|
(reset | (ld_thrd_byp_sel_e[3])) |
|
5126 |
|
|
atm_st_cmplt3 ; // Bug 4048
|
5127 |
|
|
|
5128 |
|
|
// thread qualification required.
|
5129 |
|
|
//assign ldbyp3_vld_en = (lmq_byp_data_en_w2[3] &
|
5130 |
|
|
// ~(|lmq_byp_data_sel3[2:1])) | // do not set vld for cas/stdbl
|
5131 |
|
|
// | spu_trap3 ;
|
5132 |
|
|
|
5133 |
|
|
assign ldbyp3_vld_en = lmq_byp_data_raw_sel_d2[3] |
|
5134 |
|
|
lmq_byp_data_sel3[3] |
|
5135 |
|
|
(atm_ld_w_uerr & lsu_nceen_d1[3] & dfill_thread3) |
|
5136 |
|
|
lmq_byp_data_fmx_sel[3] |
|
5137 |
|
|
tlb_err_en_w2[3] |
|
5138 |
|
|
spu_trap3 ;
|
5139 |
|
|
|
5140 |
|
|
assign fp_ldst_thrd3_w2 = fp_ldst_w2 & thread3_w2 & ld_inst_vld_w2 ;
|
5141 |
|
|
|
5142 |
|
|
// ld valid
|
5143 |
|
|
wire ldbyp3_vld_tmp ;
|
5144 |
|
|
dffre_s #(1) ldbyp3_vld_ff (
|
5145 |
|
|
.din (ldbyp3_vld_en),
|
5146 |
|
|
.q (ldbyp3_vld_tmp),
|
5147 |
|
|
.rst (ldbyp3_vld_rst), .en (ldbyp3_vld_en),
|
5148 |
|
|
.clk (clk),
|
5149 |
|
|
.se (se), .si (), .so ()
|
5150 |
|
|
);
|
5151 |
|
|
assign ldbyp3_vld = ldbyp3_vld_tmp & ~pend_atm_ld_ue[3] ;
|
5152 |
|
|
|
5153 |
|
|
|
5154 |
|
|
dffe_s #(9) ldbyp3_other_ff (
|
5155 |
|
|
.din ({fp_ldst_thrd3_w5,spu_trap3,misc_data_in[6:0]}), //bug6525 fix2
|
5156 |
|
|
.q ({ldbyp3_fpld,spubyp3_trap,misc_data3[6:0]}),
|
5157 |
|
|
.en (ldbyp3_vld_en),
|
5158 |
|
|
.clk (clk),
|
5159 |
|
|
.se (se), .si (), .so ()
|
5160 |
|
|
);
|
5161 |
|
|
|
5162 |
|
|
dffre_s #(5) ldbyp3_err_ff (
|
5163 |
|
|
.din ({tte_data_perror_unc_w2,atm_ld_w_uerr,
|
5164 |
|
|
asi_tte_data_perror_w2,asi_tte_tag_perror_w2,ifu_lsu_asi_rd_unc}),
|
5165 |
|
|
.q ({cam_perr_unc3,pend_atm_ld_ue[3],asi_data_perr3,asi_tag_perr3,
|
5166 |
|
|
ifu_unc_err3}),
|
5167 |
|
|
.rst (ldbyp3_vld_rst), .en (ldbyp3_vld_en & ~spu_trap3 & ~lmq_byp_ldxa_sel3[1]), //bug6525 fix2
|
5168 |
|
|
.clk (clk),
|
5169 |
|
|
.se (se), .si (), .so ()
|
5170 |
|
|
);
|
5171 |
|
|
|
5172 |
|
|
//assign ldbyp3_unc_err = ldbyp3_unc_err_q & ifu_lsu_nceen[3] ;
|
5173 |
|
|
|
5174 |
|
|
//assign ld_any_byp_data_vld =
|
5175 |
|
|
// ldbyp0_vld | ldbyp1_vld | ldbyp2_vld | ldbyp3_vld ;
|
5176 |
|
|
|
5177 |
|
|
dff_s #(4) stgm_sqshcmplt (
|
5178 |
|
|
.din (squash_byp_cmplt[3:0]),
|
5179 |
|
|
.q (squash_byp_cmplt_m[3:0]),
|
5180 |
|
|
.clk (clk),
|
5181 |
|
|
.se (se), .si (), .so ()
|
5182 |
|
|
);
|
5183 |
|
|
|
5184 |
|
|
dff_s #(4) stgg_sqshcmplt (
|
5185 |
|
|
.din (squash_byp_cmplt_m[3:0]),
|
5186 |
|
|
.q (squash_byp_cmplt_g[3:0]),
|
5187 |
|
|
.clk (clk),
|
5188 |
|
|
.se (se), .si (), .so ()
|
5189 |
|
|
);
|
5190 |
|
|
|
5191 |
|
|
assign fpld_byp_data_vld =
|
5192 |
|
|
(ld_thrd_byp_sel_g[0] & ldbyp0_fpld & ~squash_byp_cmplt_g[0]) | // Bug 4998
|
5193 |
|
|
(ld_thrd_byp_sel_g[1] & ldbyp1_fpld & ~squash_byp_cmplt_g[1]) |
|
5194 |
|
|
(ld_thrd_byp_sel_g[2] & ldbyp2_fpld & ~squash_byp_cmplt_g[2]) |
|
5195 |
|
|
(ld_thrd_byp_sel_g[3] & ldbyp3_fpld & ~squash_byp_cmplt_g[3]) ;
|
5196 |
|
|
|
5197 |
|
|
//assign intld_byp_data_vld = |intld_byp_cmplt[3:0] ;
|
5198 |
|
|
// squash for spu-trap situation.
|
5199 |
|
|
assign intld_byp_data_vld_e =
|
5200 |
|
|
//(intld_byp_cmplt[0] & ~spubyp0_trap) |
|
5201 |
|
|
(intld_byp_cmplt[0]) | // squash now thru squash_byp_cmplt
|
5202 |
|
|
(intld_byp_cmplt[1]) |
|
5203 |
|
|
(intld_byp_cmplt[2]) |
|
5204 |
|
|
(intld_byp_cmplt[3]) ;
|
5205 |
|
|
|
5206 |
|
|
dff_s stgm_ibvld (
|
5207 |
|
|
.din (intld_byp_data_vld_e),
|
5208 |
|
|
.q (intld_byp_data_vld_m),
|
5209 |
|
|
.clk (clk),
|
5210 |
|
|
.se (se), .si (), .so ()
|
5211 |
|
|
);
|
5212 |
|
|
|
5213 |
|
|
// to be removed - intld_byp_data_vld in lsu_mon.v
|
5214 |
|
|
/*
|
5215 |
|
|
dff_s stgg_ibvld (
|
5216 |
|
|
.din (intld_byp_data_vld_m),
|
5217 |
|
|
.q (intld_byp_data_vld),
|
5218 |
|
|
.clk (clk),
|
5219 |
|
|
.se (se), .si (), .so ()
|
5220 |
|
|
);
|
5221 |
|
|
*/
|
5222 |
|
|
assign spubyp_trap_active_e =
|
5223 |
|
|
//(intld_byp_cmplt[0] & spubyp0_trap) | // Bug 4040
|
5224 |
|
|
(ld_thrd_byp_sel_e[0] & spubyp0_trap) |
|
5225 |
|
|
(ld_thrd_byp_sel_e[1] & spubyp1_trap) |
|
5226 |
|
|
(ld_thrd_byp_sel_e[2] & spubyp2_trap) |
|
5227 |
|
|
(ld_thrd_byp_sel_e[3] & spubyp3_trap) ;
|
5228 |
|
|
|
5229 |
|
|
dff_s stgm_strmtrp (
|
5230 |
|
|
.din (spubyp_trap_active_e),
|
5231 |
|
|
.q (spubyp_trap_active_m),
|
5232 |
|
|
.clk (clk),
|
5233 |
|
|
.se (se), .si (), .so ()
|
5234 |
|
|
);
|
5235 |
|
|
|
5236 |
|
|
dff_s stgg_strmtrp (
|
5237 |
|
|
.din (spubyp_trap_active_m),
|
5238 |
|
|
.q (spubyp_trap_active_g),
|
5239 |
|
|
.clk (clk),
|
5240 |
|
|
.se (se), .si (), .so ()
|
5241 |
|
|
);
|
5242 |
|
|
|
5243 |
|
|
assign spubyp0_ttype[6:0] = misc_data0[6:0] ;
|
5244 |
|
|
assign spubyp1_ttype[6:0] = misc_data1[6:0] ;
|
5245 |
|
|
assign spubyp2_ttype[6:0] = misc_data2[6:0] ;
|
5246 |
|
|
assign spubyp3_ttype[6:0] = misc_data3[6:0] ;
|
5247 |
|
|
|
5248 |
|
|
mux4ds #(7) mux_spubyp_ttype (
|
5249 |
|
|
.in0(spubyp0_ttype[6:0]),
|
5250 |
|
|
.in1(spubyp1_ttype[6:0]),
|
5251 |
|
|
.in2(spubyp2_ttype[6:0]),
|
5252 |
|
|
.in3(spubyp3_ttype[6:0]),
|
5253 |
|
|
.sel0(ld_thrd_byp_mxsel_m[0]),
|
5254 |
|
|
.sel1(ld_thrd_byp_mxsel_m[1]),
|
5255 |
|
|
.sel2(ld_thrd_byp_mxsel_m[2]),
|
5256 |
|
|
.sel3(ld_thrd_byp_mxsel_m[3]),
|
5257 |
|
|
.dout(spubyp_ttype[6:0])
|
5258 |
|
|
);
|
5259 |
|
|
|
5260 |
|
|
assign intld_byp_cmplt[0] = (ld_thrd_byp_sel_e[0] & ~(ldbyp0_fpld | squash_byp_cmplt[0])) ;
|
5261 |
|
|
assign intld_byp_cmplt[1] = (ld_thrd_byp_sel_e[1] & ~(ldbyp1_fpld | squash_byp_cmplt[1])) ;
|
5262 |
|
|
assign intld_byp_cmplt[2] = (ld_thrd_byp_sel_e[2] & ~(ldbyp2_fpld | squash_byp_cmplt[2])) ;
|
5263 |
|
|
assign intld_byp_cmplt[3] = (ld_thrd_byp_sel_e[3] & ~(ldbyp3_fpld | squash_byp_cmplt[3])) ;
|
5264 |
|
|
|
5265 |
|
|
dff_s #(2) stgm_l2fv (
|
5266 |
|
|
.din ({l2fill_vld_e,lsu_l2fill_fpld_e}),
|
5267 |
|
|
.q ({l2fill_vld_m,l2fill_fpld_m}),
|
5268 |
|
|
.clk (clk),
|
5269 |
|
|
.se (se), .si (), .so ()
|
5270 |
|
|
);
|
5271 |
|
|
|
5272 |
|
|
dff_s #(2) stgg_l2fv (
|
5273 |
|
|
.din ({l2fill_vld_m,l2fill_fpld_m}),
|
5274 |
|
|
.q ({l2fill_vld_g,l2fill_fpld_g}),
|
5275 |
|
|
.clk (clk),
|
5276 |
|
|
.se (se), .si (), .so ()
|
5277 |
|
|
);
|
5278 |
|
|
|
5279 |
|
|
// write to irf will need to be postphoned by a few cycles.
|
5280 |
|
|
// may wish to find more bubbles by counting misses !!!
|
5281 |
|
|
//assign lsu_irf_byp_data_src[0] = ld_inst_vld_unflushed ;
|
5282 |
|
|
//assign lsu_irf_byp_data_src[1] = l2fill_vld_g ;
|
5283 |
|
|
//assign lsu_irf_byp_data_src[2] =
|
5284 |
|
|
// ~l2fill_vld_g & // no dfq fill
|
5285 |
|
|
// ~ld_inst_vld_unflushed ; // no ld/st in pipe.
|
5286 |
|
|
|
5287 |
|
|
//~(ld_inst_vld_unflushed | st_inst_vld_unflushed) ; // no ld/st in pipe.
|
5288 |
|
|
// Timing Change.
|
5289 |
|
|
//ld_any_byp_data_vld ; // full raw bypasses data
|
5290 |
|
|
|
5291 |
|
|
|
5292 |
|
|
// Store to load full raw bypassing. Plus ldxa data bypassing.
|
5293 |
|
|
// ldxa-data may be bypassed asap if port available.
|
5294 |
|
|
// ldxa/stb raw and atomics assumed to be mutually exclusive.
|
5295 |
|
|
|
5296 |
|
|
wire int_ldxa_vld ;
|
5297 |
|
|
assign int_ldxa_vld = tlu_lsu_int_ldxa_vld_w2 & ~tlu_lsu_int_ld_ill_va_w2 ;
|
5298 |
|
|
assign lmq_byp_data_fmx_sel[0] = int_ldxa_vld & thread0_w2 ;
|
5299 |
|
|
assign lmq_byp_data_fmx_sel[1] = int_ldxa_vld & thread1_w2 ;
|
5300 |
|
|
assign lmq_byp_data_fmx_sel[2] = int_ldxa_vld & thread2_w2 ;
|
5301 |
|
|
assign lmq_byp_data_fmx_sel[3] = int_ldxa_vld & thread3_w2 ;
|
5302 |
|
|
|
5303 |
|
|
assign lmq_byp_data_en_w2[0] = (|lmq_byp_data_sel0[3:0]) | lmq_byp_data_fmx_sel[0] ;
|
5304 |
|
|
assign lmq_byp_data_en_w2[1] = (|lmq_byp_data_sel1[3:0]) | lmq_byp_data_fmx_sel[1] ;
|
5305 |
|
|
assign lmq_byp_data_en_w2[2] = (|lmq_byp_data_sel2[3:0]) | lmq_byp_data_fmx_sel[2] ;
|
5306 |
|
|
assign lmq_byp_data_en_w2[3] = (|lmq_byp_data_sel3[3:0]) | lmq_byp_data_fmx_sel[3] ;
|
5307 |
|
|
|
5308 |
|
|
/*
|
5309 |
|
|
assign stq_pkt2_data_en[0] =
|
5310 |
|
|
st_inst_vld_g & ldst_dbl_g & quad_asi_g & thread0_g ;
|
5311 |
|
|
assign stq_pkt2_data_en[1] =
|
5312 |
|
|
st_inst_vld_g & ldst_dbl_g & quad_asi_g & thread1_g ;
|
5313 |
|
|
assign stq_pkt2_data_en[2] =
|
5314 |
|
|
st_inst_vld_g & ldst_dbl_g & quad_asi_g & thread2_g ;
|
5315 |
|
|
assign stq_pkt2_data_en[3] =
|
5316 |
|
|
st_inst_vld_g & ldst_dbl_g & quad_asi_g & thread3_g ;
|
5317 |
|
|
*/
|
5318 |
|
|
|
5319 |
|
|
// casxa to be decoded as doubleword.
|
5320 |
|
|
// casa to be decoded as word.
|
5321 |
|
|
// ldstuba to be decoded as byte.
|
5322 |
|
|
// casa, casxa and ldstuba needed to be decoded as alternate space insts with optional
|
5323 |
|
|
// imm_asi use.
|
5324 |
|
|
// An atomic will switch out a thread.
|
5325 |
|
|
|
5326 |
|
|
|
5327 |
|
|
wire ifu_ldxa_vld, spu_ldxa_vld ;
|
5328 |
|
|
assign ifu_ldxa_vld = ifu_lsu_ldxa_data_vld_w2 & ~ifu_lsu_ldxa_illgl_va_w2 ;
|
5329 |
|
|
//assign tlu_ldxa_vld = tlu_lsu_ldxa_data_vld_w2 & ~tlu_lsu_ldxa_illgl_va_w2 ;
|
5330 |
|
|
assign spu_ldxa_vld = spu_lsu_ldxa_data_vld_w2 & ~spu_lsu_ldxa_illgl_va_w2 ;
|
5331 |
|
|
|
5332 |
|
|
wire int_ldxa_ivld ;
|
5333 |
|
|
assign int_ldxa_ivld = tlu_lsu_int_ldxa_vld_w2 & tlu_lsu_int_ld_ill_va_w2 ;
|
5334 |
|
|
// ldxa data returns need to cmplt thread without writing to register file
|
5335 |
|
|
assign ldxa_illgl_va_cmplt[0] =
|
5336 |
|
|
((ifu_lsu_ldxa_data_vld_w2 & ifu_lsu_ldxa_illgl_va_w2) & ifu_ldxa_thread0_w2) |
|
5337 |
|
|
//((tlu_lsu_ldxa_data_vld_w2 & tlu_lsu_ldxa_illgl_va_w2) & tlu_ldxa_thread0_w2) |
|
5338 |
|
|
((spu_lsu_ldxa_data_vld_w2 & spu_lsu_ldxa_illgl_va_w2) & spu_ldxa_thread0_w2) |
|
5339 |
|
|
(int_ldxa_ivld & thread0_w2) |
|
5340 |
|
|
lsu_asi_illgl_va_cmplt_w2[0] ;
|
5341 |
|
|
assign ldxa_illgl_va_cmplt[1] =
|
5342 |
|
|
((ifu_lsu_ldxa_data_vld_w2 & ifu_lsu_ldxa_illgl_va_w2) & ifu_ldxa_thread1_w2) |
|
5343 |
|
|
//((tlu_lsu_ldxa_data_vld_w2 & tlu_lsu_ldxa_illgl_va_w2) & tlu_ldxa_thread1_w2) |
|
5344 |
|
|
((spu_lsu_ldxa_data_vld_w2 & spu_lsu_ldxa_illgl_va_w2) & spu_ldxa_thread1_w2) |
|
5345 |
|
|
(int_ldxa_ivld & thread1_w2) |
|
5346 |
|
|
lsu_asi_illgl_va_cmplt_w2[1] ;
|
5347 |
|
|
assign ldxa_illgl_va_cmplt[2] =
|
5348 |
|
|
((ifu_lsu_ldxa_data_vld_w2 & ifu_lsu_ldxa_illgl_va_w2) & ifu_ldxa_thread2_w2) |
|
5349 |
|
|
//((tlu_lsu_ldxa_data_vld_w2 & tlu_lsu_ldxa_illgl_va_w2) & tlu_ldxa_thread2_w2) |
|
5350 |
|
|
((spu_lsu_ldxa_data_vld_w2 & spu_lsu_ldxa_illgl_va_w2) & spu_ldxa_thread2_w2) |
|
5351 |
|
|
(int_ldxa_ivld & thread2_w2) |
|
5352 |
|
|
lsu_asi_illgl_va_cmplt_w2[2] ;
|
5353 |
|
|
assign ldxa_illgl_va_cmplt[3] =
|
5354 |
|
|
((ifu_lsu_ldxa_data_vld_w2 & ifu_lsu_ldxa_illgl_va_w2) & ifu_ldxa_thread3_w2) |
|
5355 |
|
|
//((tlu_lsu_ldxa_data_vld_w2 & tlu_lsu_ldxa_illgl_va_w2) & tlu_ldxa_thread3_w2) |
|
5356 |
|
|
((spu_lsu_ldxa_data_vld_w2 & spu_lsu_ldxa_illgl_va_w2) & spu_ldxa_thread3_w2) |
|
5357 |
|
|
(int_ldxa_ivld & thread3_w2) |
|
5358 |
|
|
lsu_asi_illgl_va_cmplt_w2[3] ;
|
5359 |
|
|
|
5360 |
|
|
dff_s #(4) illglva_cmplt_d1 (
|
5361 |
|
|
.din (ldxa_illgl_va_cmplt[3:0]),
|
5362 |
|
|
.q (ldxa_illgl_va_cmplt_d1[3:0]),
|
5363 |
|
|
.clk (clk),
|
5364 |
|
|
.se (se), .si (), .so ()
|
5365 |
|
|
);
|
5366 |
|
|
|
5367 |
|
|
// Thread0
|
5368 |
|
|
// Should be able to remove thread qualification for full-raw.
|
5369 |
|
|
// Could have and e stage store and w2 stage stb rd in same cycle !!! Qualify select3
|
5370 |
|
|
// with select0 to give the earlier event priority.
|
5371 |
|
|
assign lmq_byp_ldxa_sel0[0] = ifu_ldxa_vld & ifu_ldxa_thread0_w2 ;
|
5372 |
|
|
//assign lmq_byp_ldxa_sel0[1] = tlu_ldxa_vld & tlu_ldxa_thread0_w2 ;
|
5373 |
|
|
assign lmq_byp_ldxa_sel0[1] = spu_ldxa_vld & spu_ldxa_thread0_w2 ;
|
5374 |
|
|
assign lmq_byp_ldxa_sel0[2] = (lsu_asi_rd_en_w2 & thread0_w2) | ldxa_tlbrd0_w3 ;
|
5375 |
|
|
|
5376 |
|
|
wire fraw_annul0,fraw_annul1,fraw_annul2,fraw_annul3 ;
|
5377 |
|
|
wire ldst_miss0,ldst_miss1,ldst_miss2,ldst_miss3 ;
|
5378 |
|
|
|
5379 |
|
|
//RAW read STB at W3 (not W2)
|
5380 |
|
|
// E M W W2 W3 w4
|
5381 |
|
|
//LD cam_hit RD STB, flop in byp FFs
|
5382 |
|
|
//inst+1 D E
|
5383 |
|
|
//inst+2 D E <= squash (stxa) rs3_e to write into byp FFs
|
5384 |
|
|
//
|
5385 |
|
|
assign fraw_annul0 = ld_stb_full_raw_w3 & thread0_w3 & ld_inst_vld_w3;
|
5386 |
|
|
assign fraw_annul1 = ld_stb_full_raw_w3 & thread1_w3 & ld_inst_vld_w3;
|
5387 |
|
|
assign fraw_annul2 = ld_stb_full_raw_w3 & thread2_w3 & ld_inst_vld_w3;
|
5388 |
|
|
assign fraw_annul3 = ld_stb_full_raw_w3 & thread3_w3 & ld_inst_vld_w3;
|
5389 |
|
|
|
5390 |
|
|
assign ldst_miss0 = lsu_ldst_miss_w2 & thread0_w2 ;
|
5391 |
|
|
assign ldst_miss1 = lsu_ldst_miss_w2 & thread1_w2 ;
|
5392 |
|
|
assign ldst_miss2 = lsu_ldst_miss_w2 & thread2_w2 ;
|
5393 |
|
|
assign ldst_miss3 = lsu_ldst_miss_w2 & thread3_w2 ;
|
5394 |
|
|
|
5395 |
|
|
wire fraw_annul0_d1,fraw_annul1_d1,fraw_annul2_d1,fraw_annul3_d1 ;
|
5396 |
|
|
wire ldst_miss0_d1,ldst_miss1_d1,ldst_miss2_d1,ldst_miss3_d1 ;
|
5397 |
|
|
|
5398 |
|
|
dff_s #(4) fraw_d1 (
|
5399 |
|
|
.din ({fraw_annul3,fraw_annul2,fraw_annul1,fraw_annul0}),
|
5400 |
|
|
.q ({fraw_annul3_d1,fraw_annul2_d1,fraw_annul1_d1,fraw_annul0_d1}),
|
5401 |
|
|
.clk (clk),
|
5402 |
|
|
.se (se), .si (), .so ()
|
5403 |
|
|
);
|
5404 |
|
|
|
5405 |
|
|
dff_s #(4) ldstm_d1 (
|
5406 |
|
|
.din ({ldst_miss3,ldst_miss2,ldst_miss1,ldst_miss0}),
|
5407 |
|
|
.q ({ldst_miss3_d1,ldst_miss2_d1,ldst_miss1_d1,ldst_miss0_d1}),
|
5408 |
|
|
.clk (clk),
|
5409 |
|
|
.se (se), .si (), .so ()
|
5410 |
|
|
);
|
5411 |
|
|
|
5412 |
|
|
//wire memref_d ;
|
5413 |
|
|
//assign memref_d = ifu_lsu_memref_d ;
|
5414 |
|
|
/*wire mref_vld0,mref_vld1,mref_vld2,mref_vld3;
|
5415 |
|
|
wire mref_vld0_d1,mref_vld1_d1,mref_vld2_d1,mref_vld3_d1;
|
5416 |
|
|
|
5417 |
|
|
// Bug 3053 - prevent overwrite of ldxa data with subsequent st-data
|
5418 |
|
|
assign mref_vld0 = (memref_d | memref_e) & ~(lsu_ldst_miss_w2 & thread0_w2) ;
|
5419 |
|
|
assign mref_vld1 = (memref_d | memref_e) & ~(lsu_ldst_miss_w2 & thread1_w2) ;
|
5420 |
|
|
assign mref_vld2 = (memref_d | memref_e) & ~(lsu_ldst_miss_w2 & thread2_w2) ;
|
5421 |
|
|
assign mref_vld3 = (memref_d | memref_e) & ~(lsu_ldst_miss_w2 & thread3_w2) ;
|
5422 |
|
|
|
5423 |
|
|
dff_s #(4) mrefv_d1 (
|
5424 |
|
|
.din ({mref_vld3,mref_vld2,mref_vld1,mref_vld0}),
|
5425 |
|
|
.q ({mref_vld3_d1,mref_vld2_d1,mref_vld1_d1,mref_vld0_d1}),
|
5426 |
|
|
.clk (clk),
|
5427 |
|
|
.se (se), .si (), .so ()
|
5428 |
|
|
); */
|
5429 |
|
|
|
5430 |
|
|
//RAW timing change
|
5431 |
|
|
assign lmq_byp_data_sel0[0] = ld_stb_full_raw_w3 & ~(ldd_force_l2access_w3 | atomic_w3 | dtlb_perror_en_w3) & thread0_w3 & ld_inst_vld_w3 ;
|
5432 |
|
|
//assign lmq_byp_data_sel0[1] = st_inst_vld_e & thread0_e & ~ifu_lsu_casa_e & ~fraw_annul0 ;
|
5433 |
|
|
// Timing fix - at most ld will also update the bypass buffer also.
|
5434 |
|
|
//assign lmq_byp_data_sel0[1] = memref_e & thread0_e & ~ifu_lsu_casa_e & ~fraw_annul0 ; //bug3009
|
5435 |
|
|
assign lmq_byp_data_sel0[1] = ~lmq_byp_data_sel0[0] & memref_e & thread0_e & ~ifu_lsu_casa_e &
|
5436 |
|
|
~(fraw_annul0 | fraw_annul0_d1 | ldst_miss0 | ldst_miss0_d1); // Bug 3053,3180
|
5437 |
|
|
//assign lmq_byp_data_sel0[1] = mref_vld0_d1 & thread0_e & ~ifu_lsu_casa_e & ~(fraw_annul0 | fraw_annul0_d1); // Bug 3053
|
5438 |
|
|
//assign lmq_byp_data_sel0[1] = memref_e & thread0_e & ~ifu_lsu_casa_e & ~(fraw_annul0 | fraw_annul0_d1);
|
5439 |
|
|
assign lmq_byp_data_sel0[2] = ~(|lmq_byp_data_sel0[1:0]) & casa_g & thread0_g & lsu_inst_vld_w & ~fraw_annul0_d1 ;
|
5440 |
|
|
assign lmq_byp_data_sel0[3] = |lmq_byp_ldxa_sel0[2:0];
|
5441 |
|
|
//assign lmq_byp_data_sel0[3] = |lmq_byp_ldxa_sel0[3:0];
|
5442 |
|
|
|
5443 |
|
|
// Thread1
|
5444 |
|
|
assign lmq_byp_ldxa_sel1[0] = ifu_ldxa_vld & ifu_ldxa_thread1_w2 ;
|
5445 |
|
|
//assign lmq_byp_ldxa_sel1[1] = tlu_ldxa_vld & tlu_ldxa_thread1_w2 ;
|
5446 |
|
|
assign lmq_byp_ldxa_sel1[1] = spu_ldxa_vld & spu_ldxa_thread1_w2 ;
|
5447 |
|
|
assign lmq_byp_ldxa_sel1[2] = (lsu_asi_rd_en_w2 & thread1_w2) | ldxa_tlbrd1_w3 ;
|
5448 |
|
|
|
5449 |
|
|
assign lmq_byp_data_sel1[0] = ld_stb_full_raw_w3 & ~(ldd_force_l2access_w3 | atomic_w3 | dtlb_perror_en_w3) & ld_inst_vld_w3 & thread1_w3 ;
|
5450 |
|
|
assign lmq_byp_data_sel1[1] = ~lmq_byp_data_sel1[0] & memref_e & thread1_e & ~ifu_lsu_casa_e &
|
5451 |
|
|
~(fraw_annul1 | fraw_annul1_d1 | ldst_miss1 | ldst_miss1_d1); // Bug 3053,3180
|
5452 |
|
|
//assign lmq_byp_data_sel1[1] = memref_e & thread1_e & ~ifu_lsu_casa_e & ~fraw_annul1; // bug3009
|
5453 |
|
|
//assign lmq_byp_data_sel1[1] = mref_vld1_d1 & thread1_e & ~ifu_lsu_casa_e & ~(fraw_annul1 | fraw_annul1_d1);
|
5454 |
|
|
//assign lmq_byp_data_sel1[1] = memref_e & thread1_e & ~ifu_lsu_casa_e & ~(fraw_annul1 | fraw_annul1_d1); // Bug 3053
|
5455 |
|
|
assign lmq_byp_data_sel1[2] = ~(|lmq_byp_data_sel1[1:0]) & casa_g & thread1_g & lsu_inst_vld_w & ~fraw_annul1_d1 ;
|
5456 |
|
|
assign lmq_byp_data_sel1[3] = |lmq_byp_ldxa_sel1[2:0];
|
5457 |
|
|
|
5458 |
|
|
// Thread2
|
5459 |
|
|
assign lmq_byp_ldxa_sel2[0] = ifu_ldxa_vld & ifu_ldxa_thread2_w2 ;
|
5460 |
|
|
//assign lmq_byp_ldxa_sel2[1] = tlu_ldxa_vld & tlu_ldxa_thread2_w2 ;
|
5461 |
|
|
assign lmq_byp_ldxa_sel2[1] = spu_ldxa_vld & spu_ldxa_thread2_w2 ;
|
5462 |
|
|
assign lmq_byp_ldxa_sel2[2] = (lsu_asi_rd_en_w2 & thread2_w2) | ldxa_tlbrd2_w3 ;
|
5463 |
|
|
|
5464 |
|
|
assign lmq_byp_data_sel2[0] = ld_stb_full_raw_w3 & ~(ldd_force_l2access_w3 | atomic_w3 | dtlb_perror_en_w3) & ld_inst_vld_w3 & thread2_w3 ;
|
5465 |
|
|
//assign lmq_byp_data_sel2[1] = memref_e & thread2_e & ~ifu_lsu_casa_e & ~fraw_annul2; // bug3009
|
5466 |
|
|
assign lmq_byp_data_sel2[1] = ~lmq_byp_data_sel2[0] & memref_e & thread2_e & ~ifu_lsu_casa_e &
|
5467 |
|
|
~(fraw_annul2 | fraw_annul2_d1 | ldst_miss2 | ldst_miss2_d1); // Bug 3053,3180
|
5468 |
|
|
//assign lmq_byp_data_sel2[1] = memref_e & thread2_e & ~ifu_lsu_casa_e & ~(fraw_annul2 | fraw_annul2_d1); // Bug 3053
|
5469 |
|
|
assign lmq_byp_data_sel2[2] = ~(|lmq_byp_data_sel2[1:0]) & casa_g & thread2_g & lsu_inst_vld_w & ~fraw_annul2_d1 ;
|
5470 |
|
|
assign lmq_byp_data_sel2[3] = |lmq_byp_ldxa_sel2[2:0];
|
5471 |
|
|
|
5472 |
|
|
// Thread3
|
5473 |
|
|
assign lmq_byp_ldxa_sel3[0] = ifu_ldxa_vld & ifu_ldxa_thread3_w2 ;
|
5474 |
|
|
//assign lmq_byp_ldxa_sel3[1] = tlu_ldxa_vld & tlu_ldxa_thread3_w2 ;
|
5475 |
|
|
assign lmq_byp_ldxa_sel3[1] = spu_ldxa_vld & spu_ldxa_thread3_w2 ;
|
5476 |
|
|
assign lmq_byp_ldxa_sel3[2] = (lsu_asi_rd_en_w2 & thread3_w2) | ldxa_tlbrd3_w3 ;
|
5477 |
|
|
|
5478 |
|
|
assign lmq_byp_data_sel3[0] = ld_stb_full_raw_w3 & ~(ldd_force_l2access_w3 | atomic_w3 | dtlb_perror_en_w3) & ld_inst_vld_w3 & thread3_w3 ;
|
5479 |
|
|
assign lmq_byp_data_sel3[1] = ~lmq_byp_data_sel3[0] & memref_e & thread3_e & ~ifu_lsu_casa_e &
|
5480 |
|
|
~(fraw_annul3 | fraw_annul3_d1 | ldst_miss3 | ldst_miss3_d1); // Bug 3053,3180
|
5481 |
|
|
//assign lmq_byp_data_sel3[1] = memref_e & thread3_e & ~ifu_lsu_casa_e & ~(fraw_annul3 | fraw_annul3_d1); // Bug 3053
|
5482 |
|
|
assign lmq_byp_data_sel3[2] = ~(|lmq_byp_data_sel3[1:0]) & casa_g & thread3_g & lsu_inst_vld_w & ~fraw_annul3_d1 ;
|
5483 |
|
|
assign lmq_byp_data_sel3[3] = |lmq_byp_ldxa_sel3[2:0];
|
5484 |
|
|
|
5485 |
|
|
|
5486 |
|
|
dff_s #(4) ff_lmq_byp_data_raw_sel_d1 (
|
5487 |
|
|
.din ({lmq_byp_data_sel3[0], lmq_byp_data_sel2[0],
|
5488 |
|
|
lmq_byp_data_sel1[0], lmq_byp_data_sel0[0]}),
|
5489 |
|
|
.q (lmq_byp_data_raw_sel_d1[3:0]),
|
5490 |
|
|
.clk (clk),
|
5491 |
|
|
.se (se), .si (), .so ()
|
5492 |
|
|
);
|
5493 |
|
|
|
5494 |
|
|
dff_s #(4) ff_lmq_byp_data_raw_sel_d2 (
|
5495 |
|
|
.din (lmq_byp_data_raw_sel_d1[3:0]),
|
5496 |
|
|
.q (lmq_byp_data_raw_sel_d2[3:0]),
|
5497 |
|
|
.clk (clk),
|
5498 |
|
|
.se (se), .si (), .so ()
|
5499 |
|
|
);
|
5500 |
|
|
|
5501 |
|
|
wire lsu_irf_raw_byp_e;
|
5502 |
|
|
// Includes both ldxa and raw bypass.
|
5503 |
|
|
assign lsu_irf_raw_byp_e =
|
5504 |
|
|
~l2fill_vld_e & // no dfq fill
|
5505 |
|
|
~(memref_e) ; // no ld/st in pipe.
|
5506 |
|
|
//~(ld_inst_vld_e | st_inst_vld_e) ; // no ld/st in pipe.
|
5507 |
|
|
|
5508 |
|
|
// bug 5379 plus misc (randomize selection to prevent deadlock.
|
5509 |
|
|
wire [3:0] bypass_sel ;
|
5510 |
|
|
assign bypass_sel[0] = lsu_dcache_rand[0] ?
|
5511 |
|
|
ldbyp0_vld : (ldbyp0_vld & ~(ldbyp3_vld | ldbyp2_vld | ldbyp1_vld)) ;
|
5512 |
|
|
assign bypass_sel[1] = lsu_dcache_rand[0] ?
|
5513 |
|
|
(ldbyp1_vld & ~ldbyp0_vld) : (ldbyp1_vld & ~(ldbyp3_vld | ldbyp2_vld)) ;
|
5514 |
|
|
assign bypass_sel[2] = lsu_dcache_rand[0] ?
|
5515 |
|
|
(ldbyp2_vld & ~(ldbyp0_vld | ldbyp1_vld)) : (ldbyp2_vld & ~ldbyp3_vld) ;
|
5516 |
|
|
assign bypass_sel[3] = lsu_dcache_rand[0] ?
|
5517 |
|
|
(ldbyp3_vld & ~(ldbyp0_vld | ldbyp1_vld | ldbyp2_vld)) : ldbyp3_vld ;
|
5518 |
|
|
|
5519 |
|
|
assign ld_thrd_byp_sel_e[0] = bypass_sel[0] & lsu_irf_raw_byp_e ;
|
5520 |
|
|
assign ld_thrd_byp_sel_e[1] = bypass_sel[1] & lsu_irf_raw_byp_e ;
|
5521 |
|
|
assign ld_thrd_byp_sel_e[2] = bypass_sel[2] & lsu_irf_raw_byp_e ;
|
5522 |
|
|
assign ld_thrd_byp_sel_e[3] = bypass_sel[3] & lsu_irf_raw_byp_e ;
|
5523 |
|
|
|
5524 |
|
|
/*assign ld_thrd_byp_sel_e[0] = ldbyp0_vld & lsu_irf_raw_byp_e ;
|
5525 |
|
|
assign ld_thrd_byp_sel_e[1] = ldbyp1_vld & lsu_irf_raw_byp_e &
|
5526 |
|
|
~ldbyp0_vld ;
|
5527 |
|
|
assign ld_thrd_byp_sel_e[2] = ldbyp2_vld & lsu_irf_raw_byp_e &
|
5528 |
|
|
~(ldbyp0_vld | ldbyp1_vld);
|
5529 |
|
|
assign ld_thrd_byp_sel_e[3] = ldbyp3_vld & lsu_irf_raw_byp_e &
|
5530 |
|
|
~(ldbyp0_vld | ldbyp1_vld | ldbyp2_vld) ; */
|
5531 |
|
|
|
5532 |
|
|
|
5533 |
|
|
//assign lsu_ld_thrd_byp_sel_e[2:0] = ld_thrd_byp_sel_e[2:0];
|
5534 |
|
|
bw_u1_buf_30x UZsize_lsu_ld_thrd_byp_sel_e_b2 (.a(ld_thrd_byp_sel_e[2]), .z(lsu_ld_thrd_byp_sel_e[2]));
|
5535 |
|
|
bw_u1_buf_30x UZsize_lsu_ld_thrd_byp_sel_e_b1 (.a(ld_thrd_byp_sel_e[1]), .z(lsu_ld_thrd_byp_sel_e[1]));
|
5536 |
|
|
bw_u1_buf_30x UZsize_lsu_ld_thrd_byp_sel_e_b0 (.a(ld_thrd_byp_sel_e[0]), .z(lsu_ld_thrd_byp_sel_e[0]));
|
5537 |
|
|
|
5538 |
|
|
dff_s #(4) tbyp_stgd1 (
|
5539 |
|
|
.din (ld_thrd_byp_sel_e[3:0]),
|
5540 |
|
|
.q (ld_thrd_byp_sel_m[3:0]),
|
5541 |
|
|
.clk (clk),
|
5542 |
|
|
.se (se), .si (), .so ()
|
5543 |
|
|
);
|
5544 |
|
|
|
5545 |
|
|
//assign ld_thrd_byp_mxsel_m[2:0] = ld_thrd_byp_sel_m[2:0];
|
5546 |
|
|
//assign ld_thrd_byp_mxsel_m[3] = ~|ld_thrd_byp_sel_m[2:0];
|
5547 |
|
|
|
5548 |
|
|
assign ld_thrd_byp_mxsel_m[0] = ld_thrd_byp_sel_m[0] & ~rst_tri_en;
|
5549 |
|
|
assign ld_thrd_byp_mxsel_m[1] = ld_thrd_byp_sel_m[1] & ~rst_tri_en;
|
5550 |
|
|
assign ld_thrd_byp_mxsel_m[2] = ld_thrd_byp_sel_m[2] & ~rst_tri_en;
|
5551 |
|
|
assign ld_thrd_byp_mxsel_m[3] = (~|ld_thrd_byp_sel_m[2:0]) | rst_tri_en;
|
5552 |
|
|
|
5553 |
|
|
dff_s #(4) tbyp_stgd2 (
|
5554 |
|
|
.din (ld_thrd_byp_sel_m[3:0]),
|
5555 |
|
|
.q (ld_thrd_byp_sel_g[3:0]),
|
5556 |
|
|
.clk (clk),
|
5557 |
|
|
.se (se), .si (), .so ()
|
5558 |
|
|
);
|
5559 |
|
|
|
5560 |
|
|
//should move to M stage
|
5561 |
|
|
|
5562 |
|
|
//assign ld_thrd_byp_mxsel_g[2:0] = ld_thrd_byp_sel_g[2:0];
|
5563 |
|
|
//assign ld_thrd_byp_mxsel_g[3] = ~|ld_thrd_byp_sel_g[2:0];
|
5564 |
|
|
|
5565 |
|
|
assign lmq_byp_ldxa_mxsel0[1:0] = lmq_byp_ldxa_sel0[1:0];
|
5566 |
|
|
assign lmq_byp_ldxa_mxsel0[2] = ~|lmq_byp_ldxa_sel0[1:0];
|
5567 |
|
|
assign lmq_byp_ldxa_mxsel1[1:0] = lmq_byp_ldxa_sel1[1:0];
|
5568 |
|
|
assign lmq_byp_ldxa_mxsel1[2] = ~|lmq_byp_ldxa_sel1[1:0];
|
5569 |
|
|
assign lmq_byp_ldxa_mxsel2[1:0] = lmq_byp_ldxa_sel2[1:0];
|
5570 |
|
|
assign lmq_byp_ldxa_mxsel2[2] = ~|lmq_byp_ldxa_sel2[1:0];
|
5571 |
|
|
assign lmq_byp_ldxa_mxsel3[1:0] = lmq_byp_ldxa_sel3[1:0];
|
5572 |
|
|
assign lmq_byp_ldxa_mxsel3[2] = ~|lmq_byp_ldxa_sel3[1:0];
|
5573 |
|
|
|
5574 |
|
|
assign lmq_byp_data_mxsel0[0] = lmq_byp_data_sel0[0] & ~rst_tri_en | sehold;
|
5575 |
|
|
assign lmq_byp_data_mxsel0[1] = lmq_byp_data_sel0[1] & ~rst_tri_en & ~sehold;
|
5576 |
|
|
assign lmq_byp_data_mxsel0[2] = lmq_byp_data_sel0[2] & ~rst_tri_en & ~sehold;
|
5577 |
|
|
assign lmq_byp_data_mxsel0[3] = (~|lmq_byp_data_sel0[2:0] | rst_tri_en) & ~sehold;
|
5578 |
|
|
|
5579 |
|
|
assign lmq_byp_data_mxsel1[0] = lmq_byp_data_sel1[0] & ~rst_tri_en | sehold;
|
5580 |
|
|
assign lmq_byp_data_mxsel1[1] = lmq_byp_data_sel1[1] & ~rst_tri_en & ~sehold;
|
5581 |
|
|
assign lmq_byp_data_mxsel1[2] = lmq_byp_data_sel1[2] & ~rst_tri_en & ~sehold;
|
5582 |
|
|
assign lmq_byp_data_mxsel1[3] = (~|lmq_byp_data_sel1[2:0] | rst_tri_en) & ~sehold;
|
5583 |
|
|
|
5584 |
|
|
assign lmq_byp_data_mxsel2[0] = lmq_byp_data_sel2[0] & ~rst_tri_en | sehold;
|
5585 |
|
|
assign lmq_byp_data_mxsel2[1] = lmq_byp_data_sel2[1] & ~rst_tri_en & ~sehold;
|
5586 |
|
|
assign lmq_byp_data_mxsel2[2] = lmq_byp_data_sel2[2] & ~rst_tri_en & ~sehold;
|
5587 |
|
|
assign lmq_byp_data_mxsel2[3] = (~|lmq_byp_data_sel2[2:0] | rst_tri_en) & ~sehold;
|
5588 |
|
|
|
5589 |
|
|
assign lmq_byp_data_mxsel3[0] = lmq_byp_data_sel3[0] & ~rst_tri_en | sehold;
|
5590 |
|
|
assign lmq_byp_data_mxsel3[1] = lmq_byp_data_sel3[1] & ~rst_tri_en & ~sehold;
|
5591 |
|
|
assign lmq_byp_data_mxsel3[2] = lmq_byp_data_sel3[2] & ~rst_tri_en & ~sehold;
|
5592 |
|
|
assign lmq_byp_data_mxsel3[3] = (~|lmq_byp_data_sel3[2:0] | rst_tri_en) & ~sehold;
|
5593 |
|
|
|
5594 |
|
|
//=========================================================================================
|
5595 |
|
|
// Error Based Traps/Reporting
|
5596 |
|
|
//
|
5597 |
|
|
//=========================================================================================
|
5598 |
|
|
|
5599 |
|
|
// !!! ORIGINAL ABOVE !!!
|
5600 |
|
|
// Error Table for Queue
|
5601 |
|
|
// ** In all cases; squash writes to irf.
|
5602 |
|
|
// | Error Reporting | Trap ? |
|
5603 |
|
|
// ifu_lsu_asi_rd_unc | NA;done by ifu | daccess-error |
|
5604 |
|
|
// tte_data_perror_unc_w2 | sync;in pipe | daccess-error |
|
5605 |
|
|
// tte_data_perror_corr_w2 | sync;in pipe | dmmu-miss |
|
5606 |
|
|
// asi_tte_data_perror_w2 | async;out of Q | daccess-error |
|
5607 |
|
|
// asi_tte_tag_perror_w2 | async;out of Q | daccess-error |
|
5608 |
|
|
|
5609 |
|
|
assign squash_byp_cmplt[0] =
|
5610 |
|
|
((cam_perr_unc0 |
|
5611 |
|
|
asi_data_perr0 |
|
5612 |
|
|
asi_tag_perr0 |
|
5613 |
|
|
ifu_unc_err0 ) & lsu_nceen_d1[0]) |
|
5614 |
|
|
pend_atm_ld_ue[0] |
|
5615 |
|
|
spubyp0_trap ; // Bug 3873. add spu trap squash. (change reverted).
|
5616 |
|
|
assign squash_byp_cmplt[1] =
|
5617 |
|
|
((cam_perr_unc1 | asi_data_perr1 | asi_tag_perr1 | ifu_unc_err1) & lsu_nceen_d1[1]) |
|
5618 |
|
|
pend_atm_ld_ue[1] | spubyp1_trap ;
|
5619 |
|
|
assign squash_byp_cmplt[2] =
|
5620 |
|
|
((cam_perr_unc2 | asi_data_perr2 | asi_tag_perr2 | ifu_unc_err2) & lsu_nceen_d1[2]) |
|
5621 |
|
|
pend_atm_ld_ue[2] | spubyp2_trap ;
|
5622 |
|
|
assign squash_byp_cmplt[3] =
|
5623 |
|
|
((cam_perr_unc3 | asi_data_perr3 | asi_tag_perr3 | ifu_unc_err3) & lsu_nceen_d1[3]) |
|
5624 |
|
|
pend_atm_ld_ue[3] | spubyp3_trap ;
|
5625 |
|
|
|
5626 |
|
|
assign cam_perr_unc_e =
|
5627 |
|
|
(ld_thrd_byp_sel_e[0] & cam_perr_unc0) |
|
5628 |
|
|
(ld_thrd_byp_sel_e[1] & cam_perr_unc1) |
|
5629 |
|
|
(ld_thrd_byp_sel_e[2] & cam_perr_unc2) |
|
5630 |
|
|
(ld_thrd_byp_sel_e[3] & cam_perr_unc3) ;
|
5631 |
|
|
assign asi_data_perr_e =
|
5632 |
|
|
(ld_thrd_byp_sel_e[0] & asi_data_perr0) |
|
5633 |
|
|
(ld_thrd_byp_sel_e[1] & asi_data_perr1) |
|
5634 |
|
|
(ld_thrd_byp_sel_e[2] & asi_data_perr2) |
|
5635 |
|
|
(ld_thrd_byp_sel_e[3] & asi_data_perr3) ;
|
5636 |
|
|
assign asi_tag_perr_e =
|
5637 |
|
|
(ld_thrd_byp_sel_e[0] & asi_tag_perr0) |
|
5638 |
|
|
(ld_thrd_byp_sel_e[1] & asi_tag_perr1) |
|
5639 |
|
|
(ld_thrd_byp_sel_e[2] & asi_tag_perr2) |
|
5640 |
|
|
(ld_thrd_byp_sel_e[3] & asi_tag_perr3) ;
|
5641 |
|
|
assign ifu_unc_err_e =
|
5642 |
|
|
(ld_thrd_byp_sel_e[0] & ifu_unc_err0) |
|
5643 |
|
|
(ld_thrd_byp_sel_e[1] & ifu_unc_err1) |
|
5644 |
|
|
(ld_thrd_byp_sel_e[2] & ifu_unc_err2) |
|
5645 |
|
|
(ld_thrd_byp_sel_e[3] & ifu_unc_err3) ;
|
5646 |
|
|
wire atm_st_unc_err_e,atm_st_unc_err_m,atm_st_unc_err_g ;
|
5647 |
|
|
assign atm_st_unc_err_e =
|
5648 |
|
|
(atm_st_cmplt0 & pend_atm_ld_ue[0]) |
|
5649 |
|
|
(atm_st_cmplt1 & pend_atm_ld_ue[1]) |
|
5650 |
|
|
(atm_st_cmplt2 & pend_atm_ld_ue[2]) |
|
5651 |
|
|
(atm_st_cmplt3 & pend_atm_ld_ue[3]) ;
|
5652 |
|
|
|
5653 |
|
|
dff_s #(5) stgm_tlberr (
|
5654 |
|
|
.din ({cam_perr_unc_e,asi_data_perr_e,
|
5655 |
|
|
asi_tag_perr_e,ifu_unc_err_e,atm_st_unc_err_e}),
|
5656 |
|
|
.q ({cam_perr_unc_m,asi_data_perr_m,
|
5657 |
|
|
asi_tag_perr_m,ifu_unc_err_m,atm_st_unc_err_m}),
|
5658 |
|
|
.clk (clk),
|
5659 |
|
|
.se (se), .si (), .so ()
|
5660 |
|
|
);
|
5661 |
|
|
|
5662 |
|
|
|
5663 |
|
|
dff_s #(5) stgg_tlberr (
|
5664 |
|
|
.din ({cam_perr_unc_m,asi_data_perr_m,
|
5665 |
|
|
asi_tag_perr_m,ifu_unc_err_m,atm_st_unc_err_m}),
|
5666 |
|
|
.q ({cam_perr_unc_g,asi_data_perr_g,
|
5667 |
|
|
asi_tag_perr_g,ifu_unc_err_g,atm_st_unc_err_g}),
|
5668 |
|
|
.clk (clk),
|
5669 |
|
|
.se (se), .si (), .so ()
|
5670 |
|
|
);
|
5671 |
|
|
|
5672 |
|
|
assign lsu_tlb_asi_data_perr_g = asi_data_perr_g ;
|
5673 |
|
|
assign lsu_tlb_asi_tag_perr_g = asi_tag_perr_g ;
|
5674 |
|
|
|
5675 |
|
|
// Asynchronous Trap Reporting to TLU (Traps are still precise).
|
5676 |
|
|
// This version of nceen is meant specifically for trap reporting
|
5677 |
|
|
// out of the asi queue.
|
5678 |
|
|
wire nceen_m, nceen_g ;
|
5679 |
|
|
assign nceen_m =
|
5680 |
|
|
(ld_thrd_byp_sel_m[0] & lsu_nceen_d1[0]) |
|
5681 |
|
|
(ld_thrd_byp_sel_m[1] & lsu_nceen_d1[1]) |
|
5682 |
|
|
(ld_thrd_byp_sel_m[2] & lsu_nceen_d1[2]) |
|
5683 |
|
|
(ld_thrd_byp_sel_m[3] & lsu_nceen_d1[3]) ;
|
5684 |
|
|
|
5685 |
|
|
wire nceen_dfq_m,nceen_dfq_g ;
|
5686 |
|
|
|
5687 |
|
|
// This version is meant specifically for lds reporting traps
|
5688 |
|
|
// from the dfq.
|
5689 |
|
|
assign nceen_dfq_m =
|
5690 |
|
|
((~dfq_tid_m[1] & ~dfq_tid_m[0]) & lsu_nceen_d1[0]) |
|
5691 |
|
|
((~dfq_tid_m[1] & dfq_tid_m[0]) & lsu_nceen_d1[1]) |
|
5692 |
|
|
(( dfq_tid_m[1] & ~dfq_tid_m[0]) & lsu_nceen_d1[2]) |
|
5693 |
|
|
(( dfq_tid_m[1] & dfq_tid_m[0]) & lsu_nceen_d1[3]) ;
|
5694 |
|
|
|
5695 |
|
|
dff_s #(2) trpen_stg (
|
5696 |
|
|
.din ({nceen_m,nceen_dfq_m}),
|
5697 |
|
|
.q ({nceen_g,nceen_dfq_g}),
|
5698 |
|
|
.clk (clk),
|
5699 |
|
|
.se (se), .si (), .so ()
|
5700 |
|
|
);
|
5701 |
|
|
|
5702 |
|
|
|
5703 |
|
|
// l2c/dram
|
5704 |
|
|
wire atm_ld_w_uerr_m ;
|
5705 |
|
|
dff_s #(1) atmldu_stm (
|
5706 |
|
|
.din (atm_ld_w_uerr),
|
5707 |
|
|
.q (atm_ld_w_uerr_m),
|
5708 |
|
|
.clk (clk),
|
5709 |
|
|
.se (se), .si (), .so ()
|
5710 |
|
|
);
|
5711 |
|
|
|
5712 |
|
|
wire pmem_unc_error_m,pmem_unc_error_g ;
|
5713 |
|
|
assign pmem_unc_error_m =
|
5714 |
|
|
l2_unc_error_m & // bug3666
|
5715 |
|
|
~atm_ld_w_uerr_m ; //bug4048 - squash for atm ld with error.
|
5716 |
|
|
|
5717 |
|
|
wire pmem_unc_error_tmp ;
|
5718 |
|
|
dff_s #(1) pmem_stg (
|
5719 |
|
|
.din (pmem_unc_error_m),
|
5720 |
|
|
.q (pmem_unc_error_tmp),
|
5721 |
|
|
.clk (clk),
|
5722 |
|
|
.se (se), .si (), .so ()
|
5723 |
|
|
);
|
5724 |
|
|
|
5725 |
|
|
assign pmem_unc_error_g =
|
5726 |
|
|
(pmem_unc_error_tmp | bld_unc_err_pend_g) & ~bld_squash_err_g ;
|
5727 |
|
|
|
5728 |
|
|
wire async_ttype_vld_g ;
|
5729 |
|
|
wire [6:0] async_ttype_g ;
|
5730 |
|
|
wire [1:0] async_tid_g ;
|
5731 |
|
|
|
5732 |
|
|
//wire st_dtlb_perr_en ;
|
5733 |
|
|
//assign st_dtlb_perr_en = st_inst_vld_unflushed & tte_data_perror_unc & nceen_pipe_g ;
|
5734 |
|
|
|
5735 |
|
|
// traps are not to be taken if enables are not set. The asi rds of the tlb must
|
5736 |
|
|
// thus complete as usual.
|
5737 |
|
|
assign async_ttype_vld_g =
|
5738 |
|
|
(((cam_perr_unc_g | asi_data_perr_g | asi_tag_perr_g | ifu_unc_err_g) & nceen_g) |
|
5739 |
|
|
(pmem_unc_error_g & nceen_dfq_g)) | // Bug 3335,3518
|
5740 |
|
|
atm_st_unc_err_g | // Bug 4048
|
5741 |
|
|
//lsu_defr_trp_taken_g |
|
5742 |
|
|
//st_dtlb_perr_en |
|
5743 |
|
|
//cam_perr_corr_g |
|
5744 |
|
|
spubyp_trap_active_g ;
|
5745 |
|
|
|
5746 |
|
|
wire [6:0] async_ttype_m ;
|
5747 |
|
|
assign async_ttype_m[6:0] =
|
5748 |
|
|
spubyp_trap_active_m ? spubyp_ttype[6:0] : 7'h32 ;
|
5749 |
|
|
|
5750 |
|
|
dff_s #(7) attype_stg (
|
5751 |
|
|
.din (async_ttype_m[6:0]),
|
5752 |
|
|
.q (async_ttype_g[6:0]),
|
5753 |
|
|
.clk (clk),
|
5754 |
|
|
.se (se), .si (), .so ()
|
5755 |
|
|
);
|
5756 |
|
|
|
5757 |
|
|
wire [1:0] async_err_tid_e,async_err_tid_m,async_err_tid_g ;
|
5758 |
|
|
assign async_err_tid_e[0] = ld_thrd_byp_sel_e[1] | ld_thrd_byp_sel_e[3] ;
|
5759 |
|
|
assign async_err_tid_e[1] = ld_thrd_byp_sel_e[3] | ld_thrd_byp_sel_e[2] ;
|
5760 |
|
|
|
5761 |
|
|
dff_s #(2) ldbyperr_stgm (
|
5762 |
|
|
.din (async_err_tid_e[1:0]),
|
5763 |
|
|
.q (async_err_tid_m[1:0]),
|
5764 |
|
|
.clk (clk),
|
5765 |
|
|
.se (se), .si (), .so ()
|
5766 |
|
|
);
|
5767 |
|
|
|
5768 |
|
|
dff_s #(2) ldbyperr_stgg (
|
5769 |
|
|
.din (async_err_tid_m[1:0]),
|
5770 |
|
|
.q (async_err_tid_g[1:0]),
|
5771 |
|
|
.clk (clk),
|
5772 |
|
|
.se (se), .si (), .so ()
|
5773 |
|
|
);
|
5774 |
|
|
|
5775 |
|
|
wire sel_dfq_tid ;
|
5776 |
|
|
assign sel_dfq_tid = pmem_unc_error_g | atm_st_unc_err_g ;
|
5777 |
|
|
assign async_tid_g[1:0] =
|
5778 |
|
|
//lsu_defr_trp_taken_g ? thrid_g[1:0] : // Bug 4660 - remove.
|
5779 |
|
|
sel_dfq_tid ? // Bug 3335,4048
|
5780 |
|
|
dfq_tid_g[1:0] : async_err_tid_g[1:0] ;
|
5781 |
|
|
|
5782 |
|
|
// Delay async_trp interface to TLU by a cycle.
|
5783 |
|
|
|
5784 |
|
|
dff_s #(10) asynctrp_stgw2 (
|
5785 |
|
|
.din ({async_ttype_vld_g,async_tid_g[1:0],async_ttype_g[6:0]}),
|
5786 |
|
|
.q ({lsu_tlu_async_ttype_vld_w2,lsu_tlu_async_tid_w2[1:0],
|
5787 |
|
|
lsu_tlu_async_ttype_w2[6:0]}),
|
5788 |
|
|
.clk (clk),
|
5789 |
|
|
.se (se), .si (), .so ()
|
5790 |
|
|
);
|
5791 |
|
|
|
5792 |
|
|
// Asynchronous Error Reporting to IFU
|
5793 |
|
|
// Partial.
|
5794 |
|
|
|
5795 |
|
|
wire sync_error_sel ;
|
5796 |
|
|
wire memref_m ,memref_g;
|
5797 |
|
|
|
5798 |
|
|
dff_s #(1) memref_stgg (
|
5799 |
|
|
.din (memref_m),
|
5800 |
|
|
.q (memref_g),
|
5801 |
|
|
.clk (clk),
|
5802 |
|
|
.se (se), .si (), .so ()
|
5803 |
|
|
);
|
5804 |
|
|
|
5805 |
|
|
//assign sync_error_sel = tte_data_perror_unc | tte_data_perror_corr ;
|
5806 |
|
|
|
5807 |
|
|
//for in1 or in2 to be selected, memref_g must be 0.
|
5808 |
|
|
//in1 is reported thru the bypass/asi queues, in2 thru the dfq.
|
5809 |
|
|
//So err_addr_sel[0] can be memref_g.
|
5810 |
|
|
assign sync_error_sel = memref_g;
|
5811 |
|
|
|
5812 |
|
|
wire async_error_sel ;
|
5813 |
|
|
assign async_error_sel = asi_data_perr_g | asi_tag_perr_g ;
|
5814 |
|
|
|
5815 |
|
|
assign lsu_err_addr_sel[0] = sync_error_sel & ~rst_tri_en;
|
5816 |
|
|
assign lsu_err_addr_sel[1] = async_error_sel & ~rst_tri_en;
|
5817 |
|
|
assign lsu_err_addr_sel[2] = ~(sync_error_sel | async_error_sel) | rst_tri_en;
|
5818 |
|
|
|
5819 |
|
|
//mux4ds #(6) async_tlb_index_mx(
|
5820 |
|
|
// .in0 (misc_data0[5:0]),
|
5821 |
|
|
// .in1 (misc_data1[5:0]),
|
5822 |
|
|
// .in2 (misc_data2[5:0]),
|
5823 |
|
|
// .in3 (misc_data3[5:0]),
|
5824 |
|
|
// .sel0 (ld_thrd_byp_sel_g[0]),
|
5825 |
|
|
// .sel1 (ld_thrd_byp_sel_g[1]),
|
5826 |
|
|
// .sel2 (ld_thrd_byp_sel_g[2]),
|
5827 |
|
|
// .sel3 (ld_thrd_byp_sel_g[3]),
|
5828 |
|
|
// .dout (async_tlb_index[5:0])
|
5829 |
|
|
// );
|
5830 |
|
|
|
5831 |
|
|
assign async_tlb_index[5:0] =
|
5832 |
|
|
(ld_thrd_byp_sel_g[0] ? misc_data0[5:0] : 6'b0) |
|
5833 |
|
|
(ld_thrd_byp_sel_g[1] ? misc_data1[5:0] : 6'b0) |
|
5834 |
|
|
(ld_thrd_byp_sel_g[2] ? misc_data2[5:0] : 6'b0) |
|
5835 |
|
|
(ld_thrd_byp_sel_g[3] ? misc_data3[5:0] : 6'b0) ;
|
5836 |
|
|
|
5837 |
|
|
wire [1:0] err_tid_g ;
|
5838 |
|
|
//assign err_tid_g[1:0] =
|
5839 |
|
|
// sync_error_sel ? thrid_g[1:0] :
|
5840 |
|
|
// async_error_sel ? async_err_tid_g[1:0] : dfill_tid_g[1:0] ;
|
5841 |
|
|
|
5842 |
|
|
mux3ds #(2) err_tid_mx (
|
5843 |
|
|
.in0 (thrid_g[1:0]),
|
5844 |
|
|
.in1 (async_err_tid_g[1:0]),
|
5845 |
|
|
.in2 (dfill_tid_g[1:0]),
|
5846 |
|
|
.sel0(lsu_err_addr_sel[0]),
|
5847 |
|
|
.sel1(lsu_err_addr_sel[1]),
|
5848 |
|
|
.sel2(lsu_err_addr_sel[2]),
|
5849 |
|
|
.dout(err_tid_g[1:0])
|
5850 |
|
|
);
|
5851 |
|
|
|
5852 |
|
|
// Can shift to m.
|
5853 |
|
|
//assign lsu_tlu_derr_tid_g[1:0] = err_tid_g[1:0] ;
|
5854 |
|
|
|
5855 |
|
|
dff_s #(2) errad_stgg (
|
5856 |
|
|
.din (err_tid_g[1:0]),
|
5857 |
|
|
.q (lsu_ifu_error_tid[1:0]),
|
5858 |
|
|
.clk (clk),
|
5859 |
|
|
.se (se), .si (), .so ()
|
5860 |
|
|
);
|
5861 |
|
|
|
5862 |
|
|
assign lsu_ifu_io_error = //l2_unc_error_w2 & lsu_ifu_err_addr_b39 ;
|
5863 |
|
|
// extend for bld to io space.
|
5864 |
|
|
(l2_unc_error_w2 | bld_unc_err_pend_w2) & lsu_ifu_err_addr_b39 & ~bld_squash_err_w2 ;
|
5865 |
|
|
|
5866 |
|
|
|
5867 |
|
|
//=========================================================================================
|
5868 |
|
|
|
5869 |
|
|
|
5870 |
|
|
wire stxa_internal_cmplt ;
|
5871 |
|
|
assign stxa_internal_cmplt =
|
5872 |
|
|
stxa_internal &
|
5873 |
|
|
~(intrpt_disp_asi_g | stxa_stall_asi_g | (ifu_nontlb_asi_g & ~ifu_asi42_flush_g) | tlb_lng_ltncy_asi_g) &
|
5874 |
|
|
lsu_inst_vld_w & ~dctl_early_flush_w ;
|
5875 |
|
|
//lsu_inst_vld_w & ~dctl_flush_pipe_w ;
|
5876 |
|
|
|
5877 |
|
|
// Need to add stxa's related to ifu non-tlb asi.
|
5878 |
|
|
dff_s stxa_int_d1 (
|
5879 |
|
|
.din (stxa_internal_cmplt),
|
5880 |
|
|
//.din (stxa_internal & ~(stxa_stall_asi_g | tlb_lng_ltncy_asi_g) & lsu_inst_vld_w),
|
5881 |
|
|
.q (stxa_internal_d1),
|
5882 |
|
|
.clk (clk),
|
5883 |
|
|
.se (se), .si (), .so ()
|
5884 |
|
|
);
|
5885 |
|
|
|
5886 |
|
|
dff_s stxa_int_d2 (
|
5887 |
|
|
.din (stxa_internal_d1),
|
5888 |
|
|
.q (stxa_internal_d2),
|
5889 |
|
|
.clk (clk),
|
5890 |
|
|
.se (se), .si (), .so ()
|
5891 |
|
|
);
|
5892 |
|
|
|
5893 |
|
|
|
5894 |
|
|
//=========================================================================================
|
5895 |
|
|
// Replacement Algorithm for Cache
|
5896 |
|
|
//=========================================================================================
|
5897 |
|
|
|
5898 |
|
|
|
5899 |
|
|
|
5900 |
|
|
// Increment Condition.
|
5901 |
|
|
wire lfsr_incr, lfsr_incr_d1 ;
|
5902 |
|
|
assign lfsr_incr =
|
5903 |
|
|
ld_inst_vld_g & ~lsu_way_hit_or & ~ldxa_internal &
|
5904 |
|
|
~ncache_pcx_rq_g ; // must be cacheable
|
5905 |
|
|
|
5906 |
|
|
dff_s lfsrd1_ff (
|
5907 |
|
|
.din (lfsr_incr),
|
5908 |
|
|
.q (lfsr_incr_d1),
|
5909 |
|
|
.clk (clk),
|
5910 |
|
|
.se (se), .si (), .so ()
|
5911 |
|
|
);
|
5912 |
|
|
|
5913 |
|
|
wire lfsr_rst ;
|
5914 |
|
|
assign lfsr_rst =
|
5915 |
|
|
reset |
|
5916 |
|
|
~gdbginit_l | // debug init.
|
5917 |
|
|
dc_direct_map ; // direct map mode will reset.
|
5918 |
|
|
|
5919 |
|
|
// Bug 4027
|
5920 |
|
|
lsu_dcache_lfsr lfsr(.out (lsu_dcache_rand[1:0]),
|
5921 |
|
|
.clk (clk),
|
5922 |
|
|
.advance (lfsr_incr_d1),
|
5923 |
|
|
.reset (lfsr_rst),
|
5924 |
|
|
.se (se),
|
5925 |
|
|
.si (),
|
5926 |
|
|
.so ());
|
5927 |
|
|
|
5928 |
|
|
//assign lsu_dcache_rand[1:0] = dcache_rand[1:0];
|
5929 |
|
|
|
5930 |
|
|
|
5931 |
|
|
/*assign dcache_rand_new[1:0] = dcache_rand[1:0] + {1'b0, lsu_ld_miss_wb} ;
|
5932 |
|
|
dffre_s #(2) drand (
|
5933 |
|
|
.din (dcache_rand_new[1:0]),
|
5934 |
|
|
.q (dcache_rand[1:0]),
|
5935 |
|
|
.rst (reset), .en (lsu_ld_miss_wb),
|
5936 |
|
|
.clk (clk),
|
5937 |
|
|
.se (se), .si (), .so ()
|
5938 |
|
|
);
|
5939 |
|
|
|
5940 |
|
|
assign lsu_dcache_rand[1:0] = dcache_rand[1:0]; */
|
5941 |
|
|
|
5942 |
|
|
//=========================================================================================
|
5943 |
|
|
// Packet Assembly
|
5944 |
|
|
//=========================================================================================
|
5945 |
|
|
|
5946 |
|
|
assign lsu_encd_way_hit[0] = cache_way_hit_buf1[1] | cache_way_hit_buf1[3] ;
|
5947 |
|
|
assign lsu_encd_way_hit[1] = cache_way_hit_buf1[2] | cache_way_hit_buf1[3] ;
|
5948 |
|
|
|
5949 |
|
|
//assign lsu_way_hit_or = |lsu_way_hit[3:0];
|
5950 |
|
|
assign lsu_way_hit_or = |cache_way_hit_buf1[3:0]; // Bug 3940
|
5951 |
|
|
|
5952 |
|
|
//assign stb_byp_pkt_vld_e = st_inst_vld_e & ~(ldsta_internal_e & alt_space_e);
|
5953 |
|
|
assign ld_pcx_pkt_vld_e = ld_inst_vld_e & ~(ldsta_internal_e & alt_space_e);
|
5954 |
|
|
|
5955 |
|
|
|
5956 |
|
|
dff_s #(5) pktctl_stgm (
|
5957 |
|
|
.din ({ifu_lsu_ldst_dbl_e, ld_pcx_pkt_vld_e,
|
5958 |
|
|
ifu_lsu_casa_e,ifu_lsu_ldstub_e,ifu_lsu_swap_e}),
|
5959 |
|
|
.q ({ldst_dbl_m, ld_pcx_pkt_vld_m,
|
5960 |
|
|
casa_m,ldstub_m,swap_m}),
|
5961 |
|
|
.clk (clk),
|
5962 |
|
|
.se (se), .si (), .so ()
|
5963 |
|
|
);
|
5964 |
|
|
|
5965 |
|
|
assign atomic_m = casa_m | ldstub_m | swap_m ;
|
5966 |
|
|
|
5967 |
|
|
dff_s #(6) pktctl_stgg (
|
5968 |
|
|
.din ({ldst_dbl_m, ld_pcx_pkt_vld_m,
|
5969 |
|
|
casa_m,ldstub_m,swap_m,atomic_m}),
|
5970 |
|
|
.q ({ldst_dbl_g, ld_pcx_pkt_vld_g,
|
5971 |
|
|
casa_g,ldstub_g,swap_g,atomic_g}),
|
5972 |
|
|
.clk (clk),
|
5973 |
|
|
.se (se), .si (), .so ()
|
5974 |
|
|
);
|
5975 |
|
|
|
5976 |
|
|
dff_s #(2) pktctl_stgw2 (
|
5977 |
|
|
.din ({ldd_force_l2access_g, atomic_g}),
|
5978 |
|
|
.q ({ldd_force_l2access_w2,atomic_w2}),
|
5979 |
|
|
.clk (clk),
|
5980 |
|
|
.se (se), .si (), .so ()
|
5981 |
|
|
);
|
5982 |
|
|
|
5983 |
|
|
dff_s #(2) pktctl_stgw3 (
|
5984 |
|
|
.din ({ldd_force_l2access_w2, atomic_w2}),
|
5985 |
|
|
.q ({ldd_force_l2access_w3, atomic_w3}),
|
5986 |
|
|
.clk (clk),
|
5987 |
|
|
.se (se), .si (), .so ()
|
5988 |
|
|
);
|
5989 |
|
|
|
5990 |
|
|
assign lsu_ldstub_g = ldstub_g ;
|
5991 |
|
|
assign lsu_swap_g = swap_g ;
|
5992 |
|
|
|
5993 |
|
|
// Choose way for load. If load hits in dcache but sent out to xbar because
|
5994 |
|
|
// of partial raw then need to use hit way else use random. Similarly, dcache
|
5995 |
|
|
// parity error will force a miss and fill to same way.
|
5996 |
|
|
|
5997 |
|
|
// Moved to qctl1
|
5998 |
|
|
// For direct-map mode, assume that addition set-index bits 12:11 are
|
5999 |
|
|
// used to file line in set.
|
6000 |
|
|
//assign ld_way[1:0] =
|
6001 |
|
|
// (|lsu_way_hit[3:0]) ?
|
6002 |
|
|
// {lsu_encd_way_hit[1],lsu_encd_way_hit[0]} :
|
6003 |
|
|
// lsu_ld_sec_hit_l2access_g ? lsu_ld_sec_hit_wy_g[1:0] :
|
6004 |
|
|
// (dc_direct_map ? ldst_va_g[12:11] : dcache_rand[1:0]) ;
|
6005 |
|
|
|
6006 |
|
|
// set to 011 for atomic - only cas encoding used for pcx pkt.
|
6007 |
|
|
assign ld_rq_type[2:0] =
|
6008 |
|
|
atomic_g ? 3'b011 : // cas pkt 2/ldstub/swap
|
6009 |
|
|
// (ldst_dbl_g & st_inst_vld_g & quad_asi_g) ? 3'b001 : // stquad - label as store.
|
6010 |
|
|
3'b000 ; // normal load
|
6011 |
|
|
|
6012 |
|
|
|
6013 |
|
|
//assign lmq_pkt_vld_g = ld_pcx_pkt_vld_g | (ldst_dbl_g & st_inst_vld_unflushed) | pref_inst_g ;
|
6014 |
|
|
assign lmq_pkt_vld_g = ld_pcx_pkt_vld_g | pref_inst_g ;
|
6015 |
|
|
|
6016 |
|
|
// Moved to qctl1
|
6017 |
|
|
// 2'b01 encodes ld as st-quad pkt2. 2'b00 needed for cas-pkt2
|
6018 |
|
|
//assign lmq_pkt_way_g[1:0] =
|
6019 |
|
|
//(ldst_dbl_g & st_inst_vld_unflushed & quad_asi_g) ? 2'b01 :
|
6020 |
|
|
// casa_g ? 2'b00 : ld_way[1:0] ;
|
6021 |
|
|
|
6022 |
|
|
// ld is 128b request.
|
6023 |
|
|
wire qword_access_g;
|
6024 |
|
|
assign qword_access_g =
|
6025 |
|
|
(quad_asi_g | blk_asi_g ) & lsu_alt_space_g & ld_inst_vld_unflushed ;
|
6026 |
|
|
|
6027 |
|
|
assign lsu_quad_word_access_g = qword_access_g ;
|
6028 |
|
|
|
6029 |
|
|
wire fp_ld_inst_g ;
|
6030 |
|
|
assign fp_ld_inst_g = fp_ldst_g & ld_inst_vld_g ;
|
6031 |
|
|
|
6032 |
|
|
wire ldst_sz_b0_g ;
|
6033 |
|
|
assign ldst_sz_b0_g =
|
6034 |
|
|
ldst_sz_g[0] &
|
6035 |
|
|
~(ldst_dbl_g & ~fp_ldst_g &
|
6036 |
|
|
(~lsu_alt_space_g | (lsu_alt_space_g & ~quad_asi_g))) ;
|
6037 |
|
|
// word for ld-dbl
|
6038 |
|
|
|
6039 |
|
|
wire asi_real_iomem_m,asi_real_iomem_g ;
|
6040 |
|
|
assign asi_real_iomem_m =
|
6041 |
|
|
(dtlb_bypass_m & (phy_use_ec_asi_m | phy_byp_ec_asi_m) & lsu_alt_space_m) ;
|
6042 |
|
|
|
6043 |
|
|
dff_s #(1) stgg_asir (
|
6044 |
|
|
.din (asi_real_iomem_m),
|
6045 |
|
|
.q (asi_real_iomem_g),
|
6046 |
|
|
.clk (clk),
|
6047 |
|
|
.se (se), .si (), .so ()
|
6048 |
|
|
);
|
6049 |
|
|
|
6050 |
|
|
assign ncache_pcx_rq_g =
|
6051 |
|
|
atomic_g | // cas,ldstub,swap
|
6052 |
|
|
asi_real_iomem_g | // real_mem, real_io
|
6053 |
|
|
~dcache_enable_g | // dcache disabled : Bug 5174 (accidental removal)
|
6054 |
|
|
((tlb_pgnum[39] & ~lsu_dtlb_bypass_g & tlb_cam_hit_g) | // IO - tlb not in bypass
|
6055 |
|
|
(tlb_pgnum[39] & lsu_dtlb_bypass_g)) | // IO - tlb bypass
|
6056 |
|
|
(~lsu_tte_data_cp_g & tlb_cam_hit_g) | // cp bit is clear
|
6057 |
|
|
((quad_asi_g | binit_quad_asi_g | blk_asi_g) & lsu_alt_space_g & ldst_dbl_g & ld_inst_vld_unflushed) | // quad-ld
|
6058 |
|
|
pref_inst_g ; // pref will not alloc. in L2 dir
|
6059 |
|
|
|
6060 |
|
|
//wire dflush_ld_g ;
|
6061 |
|
|
//assign dflush_ld_g = dflush_asi_g & lsu_alt_space_g ;
|
6062 |
|
|
|
6063 |
|
|
// st-quad pkt1 and pkt2 need different addresses !!
|
6064 |
|
|
// ** should be able to reduce the width, rd2,stquad,lmq_pkt_way **
|
6065 |
|
|
//assign ld_pcx_pkt_g[`LMQ_WIDTH-1:0] =
|
6066 |
|
|
|
6067 |
|
|
//bug3601
|
6068 |
|
|
//dbl_data_return will become lmq_ldd
|
6069 |
|
|
//it includes quad ld, int ldd, block ld, all these cases need return data twice.
|
6070 |
|
|
wire dbl_data_return;
|
6071 |
|
|
assign dbl_data_return = ldst_dbl_g & ~ (fp_ldst_g & ~ (blk_asi_g & lsu_alt_space_g));
|
6072 |
|
|
|
6073 |
|
|
assign ld_pcx_pkt_g[`LMQ_WIDTH-1:40] =
|
6074 |
|
|
{lmq_pkt_vld_g,
|
6075 |
|
|
1'b0, //dflush_ld_g, bug 4580
|
6076 |
|
|
pref_inst_g,
|
6077 |
|
|
fp_ld_inst_g,
|
6078 |
|
|
l1hit_sign_extend_g,
|
6079 |
|
|
//lsu_bendian_access_g,
|
6080 |
|
|
bendian_g, // l2fill_bendian removed.
|
6081 |
|
|
ld_rd_g[4:0], // use rd1 only for now.
|
6082 |
|
|
dbl_data_return, //bug 3601
|
6083 |
|
|
//ldst_dbl_g & ~fp_ldst_g, // rd2 used by ld double.
|
6084 |
|
|
{ld_rd_g[4:1],~ld_rd_g[0]}, // rd2 to be used with atomics.
|
6085 |
|
|
ld_rq_type[2:0],
|
6086 |
|
|
ncache_pcx_rq_g, // NC.
|
6087 |
|
|
//lmq_pkt_way_g[1:0], // replacement way
|
6088 |
|
|
2'b00,
|
6089 |
|
|
ldst_sz_g[1],ldst_sz_b0_g};
|
6090 |
|
|
//{tlb_pgnum[39:10], ldst_va_g[9:0]}};
|
6091 |
|
|
|
6092 |
|
|
//=========================================================================================
|
6093 |
|
|
// Byte Masking for writes
|
6094 |
|
|
//=========================================================================================
|
6095 |
|
|
|
6096 |
|
|
// Byte-enables will be generated in cycle prior to fill (E-stage)
|
6097 |
|
|
// Reads and writes are mutex as array is single-ported.
|
6098 |
|
|
// byte-enables are handled thru read-modify-writes.
|
6099 |
|
|
|
6100 |
|
|
// Create 16b Write Mask based on size and va ;
|
6101 |
|
|
// This is to be put in the DFQ once the DFQ is on-line.
|
6102 |
|
|
|
6103 |
|
|
|
6104 |
|
|
wire [2:0] dc_waddr_m ;
|
6105 |
|
|
dff_s #(4) stgm_addr (
|
6106 |
|
|
.din ({memref_e, dcache_wr_addr_e[2:0]}),
|
6107 |
|
|
.q ({memref_m, dc_waddr_m[2:0]}),
|
6108 |
|
|
.clk (clk),
|
6109 |
|
|
.se (se), .si (), .so ()
|
6110 |
|
|
);
|
6111 |
|
|
|
6112 |
|
|
assign lsu_memref_m = memref_m ;
|
6113 |
|
|
|
6114 |
|
|
//wire [3:0] rwaddr_enc ;
|
6115 |
|
|
//assign rwaddr_enc[3:0] = memref_m ?
|
6116 |
|
|
// lsu_ldst_va_b7_b0_m[3:0] : dc_waddr_m[3:0];
|
6117 |
|
|
|
6118 |
|
|
wire [2:0] rwaddr_enc ;
|
6119 |
|
|
assign rwaddr_enc[2:0] = memref_m ?
|
6120 |
|
|
lsu_ldst_va_b7_b0_m[2:0] : dc_waddr_m[2:0];
|
6121 |
|
|
|
6122 |
|
|
|
6123 |
|
|
wire [1:0] wr_size;
|
6124 |
|
|
|
6125 |
|
|
assign wr_size[1:0] = dcache_wr_size_e[1:0];
|
6126 |
|
|
|
6127 |
|
|
wire wr_hword, wr_word, wr_dword;
|
6128 |
|
|
|
6129 |
|
|
//assign wr_byte = ~wr_size[1] & ~wr_size[0] ; // 01
|
6130 |
|
|
assign wr_hword = ~wr_size[1] & wr_size[0] ; // 01
|
6131 |
|
|
assign wr_word = wr_size[1] & ~wr_size[0] ; // 10
|
6132 |
|
|
assign wr_dword = wr_size[1] & wr_size[0] ; // 11
|
6133 |
|
|
|
6134 |
|
|
assign ldst_byte = ~ldst_sz_e[1] & ~ldst_sz_e[0] ; // 01
|
6135 |
|
|
assign ldst_hword = ~ldst_sz_e[1] & ldst_sz_e[0] ; // 01
|
6136 |
|
|
assign ldst_word = ldst_sz_e[1] & ~ldst_sz_e[0] ; // 10
|
6137 |
|
|
assign ldst_dword = ldst_sz_e[1] & ldst_sz_e[0] ; // 11
|
6138 |
|
|
|
6139 |
|
|
// In Bypass mode, endianness is determined by asi.
|
6140 |
|
|
// Need to complete this equation.
|
6141 |
|
|
|
6142 |
|
|
// Note : add MMU disable bypass conditions !!!
|
6143 |
|
|
assign tlb_invert_endian_g = lsu_tlb_invert_endian_g & ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
|
6144 |
|
|
|
6145 |
|
|
// Is qualification with reset needed ?
|
6146 |
|
|
//assign l2fill_bendian_g = lsu_l2fill_bendian_g & ~reset;
|
6147 |
|
|
|
6148 |
|
|
//assign pstate_cle_m =
|
6149 |
|
|
// thread0_m ? tlu_lsu_pstate_cle[0] :
|
6150 |
|
|
// thread1_m ? tlu_lsu_pstate_cle[1] :
|
6151 |
|
|
// thread2_m ? tlu_lsu_pstate_cle[2] :
|
6152 |
|
|
// tlu_lsu_pstate_cle[3] ;
|
6153 |
|
|
|
6154 |
|
|
mux4ds #(1) pstate_cle_e_mux (
|
6155 |
|
|
.in0 (tlu_lsu_pstate_cle[0]),
|
6156 |
|
|
.in1 (tlu_lsu_pstate_cle[1]),
|
6157 |
|
|
.in2 (tlu_lsu_pstate_cle[2]),
|
6158 |
|
|
.in3 (tlu_lsu_pstate_cle[3]),
|
6159 |
|
|
.sel0 (thread0_e),
|
6160 |
|
|
.sel1 (thread1_e),
|
6161 |
|
|
.sel2 (thread2_e),
|
6162 |
|
|
.sel3 (thread3_e),
|
6163 |
|
|
.dout (pstate_cle_e)
|
6164 |
|
|
);
|
6165 |
|
|
|
6166 |
|
|
dff_s #(1) stgm_pstatecle (
|
6167 |
|
|
.din (pstate_cle_e),
|
6168 |
|
|
.q (pstate_cle_m),
|
6169 |
|
|
.clk (clk),
|
6170 |
|
|
.se (se), .si (), .so ()
|
6171 |
|
|
);
|
6172 |
|
|
|
6173 |
|
|
dff_s #(1) stgg_pstatecle (
|
6174 |
|
|
.din (pstate_cle_m),
|
6175 |
|
|
.q (pstate_cle_g),
|
6176 |
|
|
.clk (clk),
|
6177 |
|
|
.se (se), .si (), .so ()
|
6178 |
|
|
);
|
6179 |
|
|
|
6180 |
|
|
//SPARC V9 page 52. pstate.cle should only affect implicit ASI
|
6181 |
|
|
assign l1hit_lendian_g =
|
6182 |
|
|
((non_altspace_ldst_g & (pstate_cle_g ^ tlb_invert_endian_g)) | // non altspace ldst
|
6183 |
|
|
(altspace_ldst_g & (lendian_asi_g ^ tlb_invert_endian_g))) // altspace ldst
|
6184 |
|
|
& ~(asi_internal_g & lsu_alt_space_g); // internal asi is big-endian
|
6185 |
|
|
|
6186 |
|
|
wire l1hit_lendian_predict_m ;
|
6187 |
|
|
// Predict endian-ness in m-stage. Assume tte.IE=0
|
6188 |
|
|
assign l1hit_lendian_predict_m =
|
6189 |
|
|
((non_altspace_ldst_m & pstate_cle_m) | // non altspace ldst
|
6190 |
|
|
(altspace_ldst_m & lendian_asi_m)) // altspace ldst
|
6191 |
|
|
& ~asi_internal_m ; // internal asi is big-endian
|
6192 |
|
|
|
6193 |
|
|
// Further, decode of ASI is not factored into endian calculation.
|
6194 |
|
|
//assign lsu_bendian_access_g = (ld_inst_vld_unflushed | st_inst_vld_unflushed) ?
|
6195 |
|
|
// ~l1hit_lendian_g : l2fill_bendian_g ;
|
6196 |
|
|
|
6197 |
|
|
// m stage endian signal is predicted for in-pipe lds only.
|
6198 |
|
|
wire bendian_pred_m, bendian_pred_g ;
|
6199 |
|
|
assign bendian_pred_m = (ld_inst_vld_m | st_inst_vld_m) ?
|
6200 |
|
|
~l1hit_lendian_predict_m : lsu_l2fill_bendian_m ;
|
6201 |
|
|
|
6202 |
|
|
dff_s #(1) stgg_bendpr(
|
6203 |
|
|
.din (bendian_pred_m),
|
6204 |
|
|
.q (bendian_pred_g),
|
6205 |
|
|
.clk (clk),
|
6206 |
|
|
.se (se), .si (), .so ()
|
6207 |
|
|
);
|
6208 |
|
|
|
6209 |
|
|
// mispredict applies to only in-pipe lds.
|
6210 |
|
|
assign endian_mispred_g = bendian_pred_g ^ ~l1hit_lendian_g ;
|
6211 |
|
|
|
6212 |
|
|
// Staging for alignment on read from l1 or fill to l2.
|
6213 |
|
|
dff_s #(4) stgm_sz (
|
6214 |
|
|
.din ({ldst_byte, ldst_hword, ldst_word, ldst_dword}),
|
6215 |
|
|
.q ({byte_m,hword_m,word_m,dword_m}),
|
6216 |
|
|
.clk (clk),
|
6217 |
|
|
.se (se), .si (), .so ()
|
6218 |
|
|
);
|
6219 |
|
|
|
6220 |
|
|
wire [7:0] rwaddr_dcd_part ;
|
6221 |
|
|
|
6222 |
|
|
assign rwaddr_dcd_part[0] = ~rwaddr_enc[2] & ~rwaddr_enc[1] & ~rwaddr_enc[0] ;
|
6223 |
|
|
assign rwaddr_dcd_part[1] = ~rwaddr_enc[2] & ~rwaddr_enc[1] & rwaddr_enc[0] ;
|
6224 |
|
|
assign rwaddr_dcd_part[2] = ~rwaddr_enc[2] & rwaddr_enc[1] & ~rwaddr_enc[0] ;
|
6225 |
|
|
assign rwaddr_dcd_part[3] = ~rwaddr_enc[2] & rwaddr_enc[1] & rwaddr_enc[0] ;
|
6226 |
|
|
assign rwaddr_dcd_part[4] = rwaddr_enc[2] & ~rwaddr_enc[1] & ~rwaddr_enc[0] ;
|
6227 |
|
|
assign rwaddr_dcd_part[5] = rwaddr_enc[2] & ~rwaddr_enc[1] & rwaddr_enc[0] ;
|
6228 |
|
|
assign rwaddr_dcd_part[6] = rwaddr_enc[2] & rwaddr_enc[1] & ~rwaddr_enc[0] ;
|
6229 |
|
|
assign rwaddr_dcd_part[7] = rwaddr_enc[2] & rwaddr_enc[1] & rwaddr_enc[0] ;
|
6230 |
|
|
|
6231 |
|
|
assign baddr_m[7:0] = rwaddr_dcd_part[7:0];
|
6232 |
|
|
/*
|
6233 |
|
|
assign baddr_m[0] = ~rwaddr_enc[3] & rwaddr_dcd_part[0] ;
|
6234 |
|
|
assign baddr_m[1] = ~rwaddr_enc[3] & rwaddr_dcd_part[1] ;
|
6235 |
|
|
assign baddr_m[2] = ~rwaddr_enc[3] & rwaddr_dcd_part[2] ;
|
6236 |
|
|
assign baddr_m[3] = ~rwaddr_enc[3] & rwaddr_dcd_part[3] ;
|
6237 |
|
|
assign baddr_m[4] = ~rwaddr_enc[3] & rwaddr_dcd_part[4] ;
|
6238 |
|
|
assign baddr_m[5] = ~rwaddr_enc[3] & rwaddr_dcd_part[5] ;
|
6239 |
|
|
assign baddr_m[6] = ~rwaddr_enc[3] & rwaddr_dcd_part[6] ;
|
6240 |
|
|
assign baddr_m[7] = ~rwaddr_enc[3] & rwaddr_dcd_part[7] ;
|
6241 |
|
|
assign baddr_m[8] = rwaddr_enc[3] & rwaddr_dcd_part[0] ;
|
6242 |
|
|
assign baddr_m[9] = rwaddr_enc[3] & rwaddr_dcd_part[1] ;
|
6243 |
|
|
assign baddr_m[10] = rwaddr_enc[3] & rwaddr_dcd_part[2] ;
|
6244 |
|
|
assign baddr_m[11] = rwaddr_enc[3] & rwaddr_dcd_part[3] ;
|
6245 |
|
|
assign baddr_m[12] = rwaddr_enc[3] & rwaddr_dcd_part[4] ;
|
6246 |
|
|
assign baddr_m[13] = rwaddr_enc[3] & rwaddr_dcd_part[5] ;
|
6247 |
|
|
assign baddr_m[14] = rwaddr_enc[3] & rwaddr_dcd_part[6] ;
|
6248 |
|
|
assign baddr_m[15] = rwaddr_enc[3] & rwaddr_dcd_part[7] ;
|
6249 |
|
|
*/
|
6250 |
|
|
// Byte Address to start write from. Quantity can be byte/hword/word/dword.
|
6251 |
|
|
// E-stage decoding for write to cache.
|
6252 |
|
|
|
6253 |
|
|
wire [3:0] waddr_enc ;
|
6254 |
|
|
wire [7:0] waddr_dcd_part ;
|
6255 |
|
|
wire [15:0] waddr_dcd ;
|
6256 |
|
|
|
6257 |
|
|
assign waddr_dcd_part[0] = ~waddr_enc[2] & ~waddr_enc[1] & ~waddr_enc[0] ;
|
6258 |
|
|
assign waddr_dcd_part[1] = ~waddr_enc[2] & ~waddr_enc[1] & waddr_enc[0] ;
|
6259 |
|
|
assign waddr_dcd_part[2] = ~waddr_enc[2] & waddr_enc[1] & ~waddr_enc[0] ;
|
6260 |
|
|
assign waddr_dcd_part[3] = ~waddr_enc[2] & waddr_enc[1] & waddr_enc[0] ;
|
6261 |
|
|
assign waddr_dcd_part[4] = waddr_enc[2] & ~waddr_enc[1] & ~waddr_enc[0] ;
|
6262 |
|
|
assign waddr_dcd_part[5] = waddr_enc[2] & ~waddr_enc[1] & waddr_enc[0] ;
|
6263 |
|
|
assign waddr_dcd_part[6] = waddr_enc[2] & waddr_enc[1] & ~waddr_enc[0] ;
|
6264 |
|
|
assign waddr_dcd_part[7] = waddr_enc[2] & waddr_enc[1] & waddr_enc[0] ;
|
6265 |
|
|
|
6266 |
|
|
assign waddr_dcd[0] = ~waddr_enc[3] & waddr_dcd_part[0] ;
|
6267 |
|
|
assign waddr_dcd[1] = ~waddr_enc[3] & waddr_dcd_part[1] ;
|
6268 |
|
|
assign waddr_dcd[2] = ~waddr_enc[3] & waddr_dcd_part[2] ;
|
6269 |
|
|
assign waddr_dcd[3] = ~waddr_enc[3] & waddr_dcd_part[3] ;
|
6270 |
|
|
assign waddr_dcd[4] = ~waddr_enc[3] & waddr_dcd_part[4] ;
|
6271 |
|
|
assign waddr_dcd[5] = ~waddr_enc[3] & waddr_dcd_part[5] ;
|
6272 |
|
|
assign waddr_dcd[6] = ~waddr_enc[3] & waddr_dcd_part[6] ;
|
6273 |
|
|
assign waddr_dcd[7] = ~waddr_enc[3] & waddr_dcd_part[7] ;
|
6274 |
|
|
assign waddr_dcd[8] = waddr_enc[3] & waddr_dcd_part[0] ;
|
6275 |
|
|
assign waddr_dcd[9] = waddr_enc[3] & waddr_dcd_part[1] ;
|
6276 |
|
|
assign waddr_dcd[10] = waddr_enc[3] & waddr_dcd_part[2] ;
|
6277 |
|
|
assign waddr_dcd[11] = waddr_enc[3] & waddr_dcd_part[3] ;
|
6278 |
|
|
assign waddr_dcd[12] = waddr_enc[3] & waddr_dcd_part[4] ;
|
6279 |
|
|
assign waddr_dcd[13] = waddr_enc[3] & waddr_dcd_part[5] ;
|
6280 |
|
|
assign waddr_dcd[14] = waddr_enc[3] & waddr_dcd_part[6] ;
|
6281 |
|
|
assign waddr_dcd[15] = waddr_enc[3] & waddr_dcd_part[7] ;
|
6282 |
|
|
|
6283 |
|
|
// Byte enables for 16 bytes.
|
6284 |
|
|
//bug6216/eco6624
|
6285 |
|
|
wire write_16byte_e;
|
6286 |
|
|
assign write_16byte_e = l2fill_vld_e | lsu_bist_wvld_e;
|
6287 |
|
|
|
6288 |
|
|
assign byte_wr_enable[15] =
|
6289 |
|
|
write_16byte_e | waddr_dcd[0] ;
|
6290 |
|
|
assign byte_wr_enable[14] =
|
6291 |
|
|
write_16byte_e | waddr_dcd[1] |
|
6292 |
|
|
(wr_hword & waddr_dcd[0]) | (wr_word & waddr_dcd[0]) |
|
6293 |
|
|
(wr_dword & waddr_dcd[0]) ;
|
6294 |
|
|
assign byte_wr_enable[13] =
|
6295 |
|
|
write_16byte_e | waddr_dcd[2] |
|
6296 |
|
|
(wr_word & waddr_dcd[0]) | (wr_dword & waddr_dcd[0]) ;
|
6297 |
|
|
assign byte_wr_enable[12] =
|
6298 |
|
|
write_16byte_e | waddr_dcd[3] |
|
6299 |
|
|
(wr_hword & waddr_dcd[2]) | (wr_word & waddr_dcd[0]) |
|
6300 |
|
|
(wr_dword & waddr_dcd[0]) ;
|
6301 |
|
|
assign byte_wr_enable[11] =
|
6302 |
|
|
write_16byte_e | waddr_dcd[4] |
|
6303 |
|
|
(wr_dword & waddr_dcd[0]) ;
|
6304 |
|
|
assign byte_wr_enable[10] =
|
6305 |
|
|
write_16byte_e | waddr_dcd[5] |
|
6306 |
|
|
(wr_hword & waddr_dcd[4]) | (wr_word & waddr_dcd[4]) |
|
6307 |
|
|
(wr_dword & waddr_dcd[0]) ;
|
6308 |
|
|
assign byte_wr_enable[9] =
|
6309 |
|
|
write_16byte_e | waddr_dcd[6] |
|
6310 |
|
|
(wr_word & waddr_dcd[4]) | (wr_dword & waddr_dcd[0]) ;
|
6311 |
|
|
assign byte_wr_enable[8] =
|
6312 |
|
|
write_16byte_e | waddr_dcd[7] |
|
6313 |
|
|
(wr_hword & waddr_dcd[6]) | (wr_word & waddr_dcd[4]) |
|
6314 |
|
|
(wr_dword & waddr_dcd[0]) ;
|
6315 |
|
|
assign byte_wr_enable[7] =
|
6316 |
|
|
write_16byte_e | waddr_dcd[8] ;
|
6317 |
|
|
assign byte_wr_enable[6] =
|
6318 |
|
|
write_16byte_e | waddr_dcd[9] |
|
6319 |
|
|
(wr_hword & waddr_dcd[8]) | (wr_word & waddr_dcd[8]) |
|
6320 |
|
|
(wr_dword & waddr_dcd[8]) ;
|
6321 |
|
|
assign byte_wr_enable[5] =
|
6322 |
|
|
write_16byte_e | waddr_dcd[10] |
|
6323 |
|
|
(wr_word & waddr_dcd[8]) | (wr_dword & waddr_dcd[8]) ;
|
6324 |
|
|
assign byte_wr_enable[4] =
|
6325 |
|
|
write_16byte_e | waddr_dcd[11] |
|
6326 |
|
|
(wr_hword & waddr_dcd[10]) | (wr_word & waddr_dcd[8]) |
|
6327 |
|
|
(wr_dword & waddr_dcd[8]) ;
|
6328 |
|
|
assign byte_wr_enable[3] =
|
6329 |
|
|
write_16byte_e | waddr_dcd[12] |
|
6330 |
|
|
(wr_dword & waddr_dcd[8]) ;
|
6331 |
|
|
assign byte_wr_enable[2] =
|
6332 |
|
|
write_16byte_e | waddr_dcd[13] |
|
6333 |
|
|
(wr_hword & waddr_dcd[12]) | (wr_word & waddr_dcd[12]) |
|
6334 |
|
|
(wr_dword & waddr_dcd[8]) ;
|
6335 |
|
|
assign byte_wr_enable[1] =
|
6336 |
|
|
write_16byte_e | waddr_dcd[14] |
|
6337 |
|
|
(wr_word & waddr_dcd[12]) | (wr_dword & waddr_dcd[8]) ;
|
6338 |
|
|
assign byte_wr_enable[0] =
|
6339 |
|
|
write_16byte_e | waddr_dcd[15] |
|
6340 |
|
|
(wr_hword & waddr_dcd[14]) | (wr_word & waddr_dcd[12]) |
|
6341 |
|
|
(wr_dword & waddr_dcd[8]) ;
|
6342 |
|
|
|
6343 |
|
|
assign dcache_byte_wr_en_e[15:0] = byte_wr_enable[15:0] ;
|
6344 |
|
|
//assign lsu_st_byte_addr_g[15:0] = byp_baddr_g[15:0] ;
|
6345 |
|
|
|
6346 |
|
|
//=========================================================================================
|
6347 |
|
|
// Sign/Zero-Extension
|
6348 |
|
|
//=========================================================================================
|
6349 |
|
|
|
6350 |
|
|
dff_s #(1) stgm_msb (
|
6351 |
|
|
.din ({lsu_l1hit_sign_extend_e}),
|
6352 |
|
|
.q ({l1hit_sign_extend_m}),
|
6353 |
|
|
.clk (clk),
|
6354 |
|
|
.se (se), .si (), .so ()
|
6355 |
|
|
);
|
6356 |
|
|
|
6357 |
|
|
dff_s #(1) stgg_msb (
|
6358 |
|
|
.din ({l1hit_sign_extend_m}),
|
6359 |
|
|
.q ({l1hit_sign_extend_g}),
|
6360 |
|
|
.clk (clk),
|
6361 |
|
|
.se (se), .si (), .so ()
|
6362 |
|
|
);
|
6363 |
|
|
|
6364 |
|
|
|
6365 |
|
|
//wire [1:0] lsu_byp_misc_sz_g ;
|
6366 |
|
|
|
6367 |
|
|
/*dff #(2) ff_lsu_byp_misc_sz_g (
|
6368 |
|
|
.din (lsu_byp_misc_sz_m[1:0]),
|
6369 |
|
|
.q (lsu_byp_misc_sz_g[1:0]),
|
6370 |
|
|
.clk (clk),
|
6371 |
|
|
.se (se), .si (), .so ()
|
6372 |
|
|
); */
|
6373 |
|
|
|
6374 |
|
|
assign misc_byte_m = ~lsu_byp_misc_sz_m[1] & ~lsu_byp_misc_sz_m[0] ; // 00
|
6375 |
|
|
assign misc_hword_m = ~lsu_byp_misc_sz_m[1] & lsu_byp_misc_sz_m[0] ; // 01
|
6376 |
|
|
assign misc_word_m = lsu_byp_misc_sz_m[1] & ~lsu_byp_misc_sz_m[0] ; // 10
|
6377 |
|
|
assign misc_dword_m = lsu_byp_misc_sz_m[1] & lsu_byp_misc_sz_m[0] ; // 11
|
6378 |
|
|
|
6379 |
|
|
wire byp_byte_m,byp_hword_m,byp_word_m,byp_dword_m;
|
6380 |
|
|
assign byp_byte_m = (ld_inst_vld_m) ? byte_m : misc_byte_m ;
|
6381 |
|
|
assign byp_hword_m = (ld_inst_vld_m) ? hword_m : misc_hword_m ;
|
6382 |
|
|
assign byp_word_m = (ld_inst_vld_m) ? word_m : misc_word_m ;
|
6383 |
|
|
assign byp_dword_m = (ld_inst_vld_m) ? dword_m : misc_dword_m ;
|
6384 |
|
|
|
6385 |
|
|
/*assign byp_byte_g = (|lsu_irf_byp_data_src[2:1]) ? misc_byte_g : byte_g ;
|
6386 |
|
|
assign byp_hword_g = (|lsu_irf_byp_data_src[2:1]) ? misc_hword_g : hword_g ;
|
6387 |
|
|
assign byp_word_g = (|lsu_irf_byp_data_src[2:1]) ? misc_word_g : word_g ;*/
|
6388 |
|
|
|
6389 |
|
|
dff_s #(1) bypsz_stgg(
|
6390 |
|
|
.din ({byp_word_m}),
|
6391 |
|
|
.q ({byp_word_g}),
|
6392 |
|
|
.clk (clk),
|
6393 |
|
|
.se (se), .si (), .so ()
|
6394 |
|
|
);
|
6395 |
|
|
|
6396 |
|
|
//wire [3:0] misc_waddr_m ;
|
6397 |
|
|
//assign misc_waddr_m[3:0] = {lsu_byp_misc_addr_m[3],lsu_byp_misc_addr_m[2]^lsu_byp_ldd_oddrd_m,lsu_byp_misc_addr_m[1:0]} ;
|
6398 |
|
|
|
6399 |
|
|
wire [2:0] misc_waddr_m ;
|
6400 |
|
|
assign misc_waddr_m[2:0] = {lsu_byp_misc_addr_m[2]^lsu_byp_ldd_oddrd_m,lsu_byp_misc_addr_m[1:0]} ;
|
6401 |
|
|
|
6402 |
|
|
//wire [15:0] misc_baddr_m ;
|
6403 |
|
|
wire [7:0] misc_baddr_m ;
|
6404 |
|
|
|
6405 |
|
|
// m-stage decoding
|
6406 |
|
|
// Might be better to stage encoded waddr, mux and then decode.
|
6407 |
|
|
/*
|
6408 |
|
|
assign misc_baddr_m[0] = ~misc_waddr_m[3] & ~misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6409 |
|
|
assign misc_baddr_m[1] = ~misc_waddr_m[3] & ~misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
|
6410 |
|
|
assign misc_baddr_m[2] = ~misc_waddr_m[3] & ~misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6411 |
|
|
assign misc_baddr_m[3] = ~misc_waddr_m[3] & ~misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
|
6412 |
|
|
assign misc_baddr_m[4] = ~misc_waddr_m[3] & misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6413 |
|
|
assign misc_baddr_m[5] = ~misc_waddr_m[3] & misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
|
6414 |
|
|
assign misc_baddr_m[6] = ~misc_waddr_m[3] & misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6415 |
|
|
assign misc_baddr_m[7] = ~misc_waddr_m[3] & misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
|
6416 |
|
|
assign misc_baddr_m[8] = misc_waddr_m[3] & ~misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6417 |
|
|
assign misc_baddr_m[9] = misc_waddr_m[3] & ~misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
|
6418 |
|
|
assign misc_baddr_m[10] = misc_waddr_m[3] & ~misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6419 |
|
|
assign misc_baddr_m[11] = misc_waddr_m[3] & ~misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
|
6420 |
|
|
assign misc_baddr_m[12] = misc_waddr_m[3] & misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6421 |
|
|
assign misc_baddr_m[13] = misc_waddr_m[3] & misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
|
6422 |
|
|
assign misc_baddr_m[14] = misc_waddr_m[3] & misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6423 |
|
|
assign misc_baddr_m[15] = misc_waddr_m[3] & misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
|
6424 |
|
|
*/
|
6425 |
|
|
assign misc_baddr_m[0] = ~misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6426 |
|
|
assign misc_baddr_m[1] = ~misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
|
6427 |
|
|
assign misc_baddr_m[2] = ~misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6428 |
|
|
assign misc_baddr_m[3] = ~misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
|
6429 |
|
|
assign misc_baddr_m[4] = misc_waddr_m[2] & ~misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6430 |
|
|
assign misc_baddr_m[5] = misc_waddr_m[2] & ~misc_waddr_m[1] & misc_waddr_m[0] ;
|
6431 |
|
|
assign misc_baddr_m[6] = misc_waddr_m[2] & misc_waddr_m[1] & ~misc_waddr_m[0] ;
|
6432 |
|
|
assign misc_baddr_m[7] = misc_waddr_m[2] & misc_waddr_m[1] & misc_waddr_m[0] ;
|
6433 |
|
|
|
6434 |
|
|
//wire [15:0] byp_baddr_m ;
|
6435 |
|
|
//assign byp_baddr_m[15:0] = (~(ld_inst_vld_m | st_inst_vld_m)) ? misc_baddr_m[15:0] : baddr_m[15:0] ;
|
6436 |
|
|
wire [7:0] byp_baddr_m ;
|
6437 |
|
|
assign byp_baddr_m[7:0] = (~(ld_inst_vld_m | st_inst_vld_m)) ? misc_baddr_m[7:0] : baddr_m[7:0] ;
|
6438 |
|
|
|
6439 |
|
|
wire l2fill_sign_extend_m;
|
6440 |
|
|
|
6441 |
|
|
assign l2fill_sign_extend_m = lsu_l2fill_sign_extend_m ;
|
6442 |
|
|
//?? why need st ??
|
6443 |
|
|
assign signed_ldst_m = (ld_inst_vld_m | st_inst_vld_m) ?
|
6444 |
|
|
l1hit_sign_extend_m : l2fill_sign_extend_m ;
|
6445 |
|
|
|
6446 |
|
|
//assign unsigned_ldst_m = ~signed_ldst_m ;
|
6447 |
|
|
|
6448 |
|
|
assign signed_ldst_byte_m = signed_ldst_m & byp_byte_m;
|
6449 |
|
|
// assign unsigned_ldst_byte_m = unsigned_ldst_m & byp_byte_m;
|
6450 |
|
|
|
6451 |
|
|
assign signed_ldst_hw_m = signed_ldst_m & ( byp_byte_m | byp_hword_m );
|
6452 |
|
|
// assign unsigned_ldst_hw_m = unsigned_ldst_m & ( byp_byte_m | byp_hword_m );
|
6453 |
|
|
|
6454 |
|
|
assign signed_ldst_w_m = signed_ldst_m & ( byp_byte_m | byp_hword_m | byp_word_m );
|
6455 |
|
|
// assign unsigned_ldst_w_m = unsigned_ldst_m & ( byp_byte_m | byp_hword_m | byp_word_m );
|
6456 |
|
|
|
6457 |
|
|
//C assign align_bytes_msb[7:0] = (ld_inst_vld_unflushed | st_inst_vld_unflushed) ? lsu_l1hit_bytes_msb_g[7:0] :
|
6458 |
|
|
//C (l2fill_vld_g ? l2fill_bytes_msb_g[7:0] : lsu_misc_bytes_msb_g[7:0]) ;
|
6459 |
|
|
|
6460 |
|
|
//assign align_bytes_msb[7:0] = (ld_inst_vld_unflushed | st_inst_vld_unflushed) ? lsu_l1hit_bytes_msb_g[7:0] :
|
6461 |
|
|
// (lsu_irf_byp_data_src[2] ? lsu_misc_bytes_msb_g[7:0] : l2fill_bytes_msb_g[7:0]) ;
|
6462 |
|
|
|
6463 |
|
|
|
6464 |
|
|
// For little-endian accesses, the following morphing must occur to the byte addr.
|
6465 |
|
|
//
|
6466 |
|
|
// Byte Addr(lower 3b)
|
6467 |
|
|
// 000(0) -> 001(1) (hw)
|
6468 |
|
|
// -> 011(3) (w)
|
6469 |
|
|
// -> 111(7) (dw)
|
6470 |
|
|
// 001(1) -> not morphed
|
6471 |
|
|
// 010(2) -> 011(3) (hw)
|
6472 |
|
|
// 011(3) -> not morphed
|
6473 |
|
|
// 100(4) -> 101(5) (hw)
|
6474 |
|
|
// -> 111(7) (w)
|
6475 |
|
|
// 101(5) -> not morphed
|
6476 |
|
|
// 110(6) -> 111(7) (hw)
|
6477 |
|
|
// 111(7) -> not morphed
|
6478 |
|
|
|
6479 |
|
|
wire [7:0] merged_addr_m ;
|
6480 |
|
|
wire [7:0] morphed_addr_m ;
|
6481 |
|
|
|
6482 |
|
|
//wire bendian ;
|
6483 |
|
|
|
6484 |
|
|
//assign merged_addr_m[7:0] = byp_baddr_m[15:8] | byp_baddr_m[7:0] ;
|
6485 |
|
|
assign merged_addr_m[7:0] = byp_baddr_m[7:0] ;
|
6486 |
|
|
|
6487 |
|
|
assign morphed_addr_m[0]
|
6488 |
|
|
= merged_addr_m[0] & ~(~bendian_pred_m & ~byp_byte_m) ;
|
6489 |
|
|
assign morphed_addr_m[1]
|
6490 |
|
|
= merged_addr_m[1] | (merged_addr_m[0] & ~bendian_pred_m & byp_hword_m) ;
|
6491 |
|
|
assign morphed_addr_m[2]
|
6492 |
|
|
= merged_addr_m[2] & ~(~bendian_pred_m & byp_hword_m) ;
|
6493 |
|
|
assign morphed_addr_m[3]
|
6494 |
|
|
= merged_addr_m[3] | (merged_addr_m[0] & ~bendian_pred_m & byp_word_m) |
|
6495 |
|
|
(merged_addr_m[2] & ~bendian_pred_m & byp_hword_m) ;
|
6496 |
|
|
assign morphed_addr_m[4]
|
6497 |
|
|
= merged_addr_m[4] & ~(~bendian_pred_m & (byp_hword_m | byp_word_m)) ;
|
6498 |
|
|
assign morphed_addr_m[5]
|
6499 |
|
|
= merged_addr_m[5] | (merged_addr_m[4] & ~bendian_pred_m & byp_hword_m) ;
|
6500 |
|
|
assign morphed_addr_m[6]
|
6501 |
|
|
= merged_addr_m[6] & ~(~bendian_pred_m & byp_hword_m) ;
|
6502 |
|
|
assign morphed_addr_m[7]
|
6503 |
|
|
= merged_addr_m[7] | (merged_addr_m[0] & ~bendian_pred_m & ~(byp_byte_m | byp_hword_m | byp_word_m)) |
|
6504 |
|
|
(merged_addr_m[4] & ~bendian_pred_m & byp_word_m) | (merged_addr_m[6] & ~bendian_pred_m & byp_hword_m) ;
|
6505 |
|
|
|
6506 |
|
|
|
6507 |
|
|
|
6508 |
|
|
|
6509 |
|
|
//=========================================================================================
|
6510 |
|
|
// ALIGNMENT CONTROL FOR DCDP
|
6511 |
|
|
//=========================================================================================
|
6512 |
|
|
|
6513 |
|
|
// First generate control for swapping related to endianness.
|
6514 |
|
|
// byte7-byte0 is source data from cache etc.
|
6515 |
|
|
// swap7-swap0 is result of endianness swapping.
|
6516 |
|
|
|
6517 |
|
|
// First logical level - Swapping of bytes.
|
6518 |
|
|
// Swap byte 0
|
6519 |
|
|
|
6520 |
|
|
wire swap0_sel_byte0, swap0_sel_byte1, swap0_sel_byte3 ;
|
6521 |
|
|
wire swap1_sel_byte0, swap1_sel_byte1, swap1_sel_byte2, swap1_sel_byte6 ;
|
6522 |
|
|
wire swap2_sel_byte1, swap2_sel_byte2, swap2_sel_byte3, swap2_sel_byte5 ;
|
6523 |
|
|
wire swap3_sel_byte0, swap3_sel_byte2, swap3_sel_byte3, swap3_sel_byte4 ;
|
6524 |
|
|
wire swap4_sel_byte3, swap4_sel_byte4, swap4_sel_byte5 ;
|
6525 |
|
|
wire swap5_sel_byte2, swap5_sel_byte4, swap5_sel_byte5, swap5_sel_byte6 ;
|
6526 |
|
|
wire swap6_sel_byte1, swap6_sel_byte5, swap6_sel_byte6 ;
|
6527 |
|
|
wire swap7_sel_byte0, swap7_sel_byte4, swap7_sel_byte6, swap7_sel_byte7 ;
|
6528 |
|
|
|
6529 |
|
|
//assign bendian = bendian_pred_m ;
|
6530 |
|
|
//assign bendian = lsu_bendian_access_g ;
|
6531 |
|
|
|
6532 |
|
|
assign swap0_sel_byte0 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
|
6533 |
|
|
assign swap0_sel_byte1 = ~bendian_pred_m & byp_hword_m ;
|
6534 |
|
|
assign swap0_sel_byte3 = ~bendian_pred_m & byp_word_m ;
|
6535 |
|
|
// could be substituted with dword encoding.
|
6536 |
|
|
//assign swap0_sel_byte7 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
|
6537 |
|
|
|
6538 |
|
|
// Swap byp_byte_m 1
|
6539 |
|
|
assign swap1_sel_byte0 = ~bendian_pred_m & byp_hword_m ;
|
6540 |
|
|
assign swap1_sel_byte1 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
|
6541 |
|
|
assign swap1_sel_byte2 = ~bendian_pred_m & byp_word_m ;
|
6542 |
|
|
assign swap1_sel_byte6 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
|
6543 |
|
|
|
6544 |
|
|
// Swap byp_byte_m 2
|
6545 |
|
|
assign swap2_sel_byte1 = ~bendian_pred_m & byp_word_m ;
|
6546 |
|
|
assign swap2_sel_byte2 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
|
6547 |
|
|
assign swap2_sel_byte3 = ~bendian_pred_m & byp_hword_m ;
|
6548 |
|
|
assign swap2_sel_byte5 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
|
6549 |
|
|
|
6550 |
|
|
// Swap byp_byte_m 3
|
6551 |
|
|
assign swap3_sel_byte0 = ~bendian_pred_m & byp_word_m ;
|
6552 |
|
|
assign swap3_sel_byte2 = ~bendian_pred_m & byp_hword_m ;
|
6553 |
|
|
assign swap3_sel_byte3 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
|
6554 |
|
|
assign swap3_sel_byte4 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
|
6555 |
|
|
|
6556 |
|
|
// Swap byp_byte_m 4
|
6557 |
|
|
assign swap4_sel_byte3 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
|
6558 |
|
|
assign swap4_sel_byte4 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
|
6559 |
|
|
assign swap4_sel_byte5 = ~bendian_pred_m & byp_hword_m ;
|
6560 |
|
|
//assign swap4_sel_byte7 = ~bendian_pred_m & byp_word_m ;
|
6561 |
|
|
|
6562 |
|
|
// Swap byp_byte_m 5
|
6563 |
|
|
assign swap5_sel_byte2 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
|
6564 |
|
|
assign swap5_sel_byte4 = ~bendian_pred_m & byp_hword_m ;
|
6565 |
|
|
assign swap5_sel_byte5 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
|
6566 |
|
|
assign swap5_sel_byte6 = ~bendian_pred_m & byp_word_m ;
|
6567 |
|
|
|
6568 |
|
|
// Swap byp_byte_m 6
|
6569 |
|
|
assign swap6_sel_byte1 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
|
6570 |
|
|
assign swap6_sel_byte5 = ~bendian_pred_m & byp_word_m ;
|
6571 |
|
|
assign swap6_sel_byte6 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
|
6572 |
|
|
//assign swap6_sel_byte7 = ~bendian_pred_m & byp_hword_m ;
|
6573 |
|
|
|
6574 |
|
|
// Swap byp_byte_m 7
|
6575 |
|
|
assign swap7_sel_byte0 = ~bendian_pred_m & ~(byp_word_m | byp_hword_m | byp_byte_m) ;
|
6576 |
|
|
assign swap7_sel_byte4 = ~bendian_pred_m & byp_word_m ;
|
6577 |
|
|
assign swap7_sel_byte6 = ~bendian_pred_m & byp_hword_m ;
|
6578 |
|
|
assign swap7_sel_byte7 = bendian_pred_m | (~bendian_pred_m & byp_byte_m) ;
|
6579 |
|
|
|
6580 |
|
|
// 2nd logical level - Alignment.
|
6581 |
|
|
// rjust7-rjust0 is result of alignment operation.
|
6582 |
|
|
// sbyte7-sbyte0 is the result of the endian swapping from the 1st logic level.
|
6583 |
|
|
|
6584 |
|
|
wire rjust0_sel_sbyte0, rjust0_sel_sbyte1, rjust0_sel_sbyte2, rjust0_sel_sbyte3 ;
|
6585 |
|
|
wire rjust0_sel_sbyte4, rjust0_sel_sbyte5, rjust0_sel_sbyte6, rjust0_sel_sbyte7 ;
|
6586 |
|
|
wire rjust1_sel_sbyte1, rjust1_sel_sbyte3, rjust1_sel_sbyte5, rjust1_sel_sbyte7 ;
|
6587 |
|
|
wire rjust2_sel_sbyte2, rjust2_sel_sbyte6 ;
|
6588 |
|
|
wire rjust3_sel_sbyte3, rjust3_sel_sbyte7 ;
|
6589 |
|
|
|
6590 |
|
|
// Aligned Byte 0
|
6591 |
|
|
assign rjust0_sel_sbyte0 =
|
6592 |
|
|
~(rjust0_sel_sbyte1 | rjust0_sel_sbyte2 | rjust0_sel_sbyte3 |
|
6593 |
|
|
rjust0_sel_sbyte4 | rjust0_sel_sbyte5 | rjust0_sel_sbyte6 |
|
6594 |
|
|
rjust0_sel_sbyte7) ;
|
6595 |
|
|
assign rjust0_sel_sbyte1 =
|
6596 |
|
|
// ((byp_baddr_m[14] | byp_baddr_m[6]) & byp_byte_m) ;
|
6597 |
|
|
((byp_baddr_m[6]) & byp_byte_m) ;
|
6598 |
|
|
|
6599 |
|
|
assign rjust0_sel_sbyte2 =
|
6600 |
|
|
// ((byp_baddr_m[12] | byp_baddr_m[4]) & byp_hword_m) |
|
6601 |
|
|
((byp_baddr_m[4]) & byp_hword_m) |
|
6602 |
|
|
// ((byp_baddr_m[13] | byp_baddr_m[5]) & byp_byte_m) ;
|
6603 |
|
|
((byp_baddr_m[5]) & byp_byte_m) ;
|
6604 |
|
|
assign rjust0_sel_sbyte3 =
|
6605 |
|
|
// (byp_baddr_m[12] | byp_baddr_m[4]) & byp_byte_m ;
|
6606 |
|
|
(byp_baddr_m[4]) & byp_byte_m ;
|
6607 |
|
|
assign rjust0_sel_sbyte4 =
|
6608 |
|
|
// ((byp_baddr_m[10] | byp_baddr_m[2]) & byp_hword_m) |
|
6609 |
|
|
// ((byp_baddr_m[11] | byp_baddr_m[3]) & byp_byte_m) |
|
6610 |
|
|
// ((byp_baddr_m[8] | byp_baddr_m[0]) & byp_word_m) ;
|
6611 |
|
|
((byp_baddr_m[2]) & byp_hword_m) |
|
6612 |
|
|
((byp_baddr_m[3]) & byp_byte_m) |
|
6613 |
|
|
((byp_baddr_m[0]) & byp_word_m) ;
|
6614 |
|
|
assign rjust0_sel_sbyte5 =
|
6615 |
|
|
// ((byp_baddr_m[10] | byp_baddr_m[2]) & byp_byte_m) ;
|
6616 |
|
|
((byp_baddr_m[2]) & byp_byte_m) ;
|
6617 |
|
|
assign rjust0_sel_sbyte6 =
|
6618 |
|
|
// ((byp_baddr_m[8] | byp_baddr_m[0]) & byp_hword_m) |
|
6619 |
|
|
// ((byp_baddr_m[9] | byp_baddr_m[1]) & byp_byte_m) ;
|
6620 |
|
|
((byp_baddr_m[0]) & byp_hword_m) |
|
6621 |
|
|
((byp_baddr_m[1]) & byp_byte_m) ;
|
6622 |
|
|
assign rjust0_sel_sbyte7 =
|
6623 |
|
|
// (byp_baddr_m[8] | byp_baddr_m[0]) & byp_byte_m ;
|
6624 |
|
|
(byp_baddr_m[0]) & byp_byte_m ;
|
6625 |
|
|
|
6626 |
|
|
// Aligned Byte 1
|
6627 |
|
|
assign rjust1_sel_sbyte1 =
|
6628 |
|
|
~(rjust1_sel_sbyte3 | rjust1_sel_sbyte5 | rjust1_sel_sbyte7) ;
|
6629 |
|
|
assign rjust1_sel_sbyte3 =
|
6630 |
|
|
// (byp_baddr_m[12] | byp_baddr_m[4]) & byp_hword_m ;
|
6631 |
|
|
(byp_baddr_m[4]) & byp_hword_m ;
|
6632 |
|
|
assign rjust1_sel_sbyte5 =
|
6633 |
|
|
// ((byp_baddr_m[10] | byp_baddr_m[2]) & byp_hword_m) |
|
6634 |
|
|
// ((byp_baddr_m[8] | byp_baddr_m[0]) & byp_word_m) ;
|
6635 |
|
|
((byp_baddr_m[2]) & byp_hword_m) |
|
6636 |
|
|
((byp_baddr_m[0]) & byp_word_m) ;
|
6637 |
|
|
assign rjust1_sel_sbyte7 =
|
6638 |
|
|
// (byp_baddr_m[8] | byp_baddr_m[0]) & byp_hword_m ;
|
6639 |
|
|
(byp_baddr_m[0]) & byp_hword_m ;
|
6640 |
|
|
|
6641 |
|
|
// Aligned Byte 2
|
6642 |
|
|
assign rjust2_sel_sbyte2 = ~rjust2_sel_sbyte6 ;
|
6643 |
|
|
//assign rjust2_sel_sbyte6 = (byp_baddr_m[8] | byp_baddr_m[0]) & byp_word_m ;
|
6644 |
|
|
assign rjust2_sel_sbyte6 = (byp_baddr_m[0]) & byp_word_m ;
|
6645 |
|
|
|
6646 |
|
|
// Aligned Byte 3
|
6647 |
|
|
assign rjust3_sel_sbyte3 = ~rjust3_sel_sbyte7 ;
|
6648 |
|
|
//assign rjust3_sel_sbyte7 = (byp_baddr_m[8] | byp_baddr_m[0]) & byp_word_m ;
|
6649 |
|
|
assign rjust3_sel_sbyte7 = (byp_baddr_m[0]) & byp_word_m ;
|
6650 |
|
|
|
6651 |
|
|
// 3rd logical level - Complete alignment. Sign-Extension/Zero-Extension.
|
6652 |
|
|
// merge7-merge0 corresponds to cumulative swapping and alignment result.
|
6653 |
|
|
// byte[7]-byte[0] refers to the original pre-swap/alignment data.
|
6654 |
|
|
|
6655 |
|
|
wire merge7_sel_byte0_m, merge7_sel_byte7_m;
|
6656 |
|
|
wire merge6_sel_byte1_m, merge6_sel_byte6_m;
|
6657 |
|
|
wire merge5_sel_byte2_m, merge5_sel_byte5_m;
|
6658 |
|
|
wire merge4_sel_byte3_m, merge4_sel_byte4_m;
|
6659 |
|
|
wire merge3_sel_byte0_m, merge3_sel_byte3_m;
|
6660 |
|
|
wire merge3_sel_byte4_m, merge3_sel_byte7_m,merge3_sel_byte_m;
|
6661 |
|
|
wire merge2_sel_byte1_m, merge2_sel_byte2_m, merge2_sel_byte5_m;
|
6662 |
|
|
wire merge2_sel_byte6_m, merge2_sel_byte_m;
|
6663 |
|
|
wire merge0_sel_byte0_m, merge0_sel_byte1_m;
|
6664 |
|
|
wire merge0_sel_byte2_m, merge0_sel_byte3_m;
|
6665 |
|
|
wire merge0_sel_byte4_m, merge0_sel_byte5_m;
|
6666 |
|
|
wire merge0_sel_byte6_m;
|
6667 |
|
|
wire merge1_sel_byte0_m, merge1_sel_byte1_m;
|
6668 |
|
|
wire merge1_sel_byte2_m, merge1_sel_byte3_m;
|
6669 |
|
|
wire merge1_sel_byte4_m, merge1_sel_byte5_m;
|
6670 |
|
|
wire merge1_sel_byte6_m, merge1_sel_byte7_m;
|
6671 |
|
|
wire merge0_sel_byte_1h_m,merge1_sel_byte_1h_m, merge1_sel_byte_2h_m;
|
6672 |
|
|
|
6673 |
|
|
// Final Merged Byte 0
|
6674 |
|
|
assign merge0_sel_byte0_m =
|
6675 |
|
|
(rjust0_sel_sbyte0 & swap0_sel_byte0) |
|
6676 |
|
|
(rjust0_sel_sbyte1 & swap1_sel_byte0) |
|
6677 |
|
|
(rjust0_sel_sbyte3 & swap3_sel_byte0) |
|
6678 |
|
|
(rjust0_sel_sbyte7 & swap7_sel_byte0) ;
|
6679 |
|
|
|
6680 |
|
|
assign merge0_sel_byte1_m =
|
6681 |
|
|
(rjust0_sel_sbyte0 & swap0_sel_byte1) |
|
6682 |
|
|
(rjust0_sel_sbyte1 & swap1_sel_byte1) |
|
6683 |
|
|
(rjust0_sel_sbyte2 & swap2_sel_byte1) |
|
6684 |
|
|
(rjust0_sel_sbyte6 & swap6_sel_byte1) ;
|
6685 |
|
|
|
6686 |
|
|
assign merge0_sel_byte2_m =
|
6687 |
|
|
(rjust0_sel_sbyte1 & swap1_sel_byte2) |
|
6688 |
|
|
(rjust0_sel_sbyte2 & swap2_sel_byte2) |
|
6689 |
|
|
(rjust0_sel_sbyte3 & swap3_sel_byte2) |
|
6690 |
|
|
(rjust0_sel_sbyte5 & swap5_sel_byte2) ;
|
6691 |
|
|
|
6692 |
|
|
|
6693 |
|
|
assign merge0_sel_byte3_m =
|
6694 |
|
|
(rjust0_sel_sbyte0 & swap0_sel_byte3) |
|
6695 |
|
|
(rjust0_sel_sbyte2 & swap2_sel_byte3) |
|
6696 |
|
|
(rjust0_sel_sbyte3 & swap3_sel_byte3) |
|
6697 |
|
|
(rjust0_sel_sbyte4 & swap4_sel_byte3) ;
|
6698 |
|
|
|
6699 |
|
|
assign merge0_sel_byte3_default_m = ~ (merge0_sel_byte0_m | merge0_sel_byte1_m | merge0_sel_byte2_m);
|
6700 |
|
|
|
6701 |
|
|
assign merge0_sel_byte4_m =
|
6702 |
|
|
(rjust0_sel_sbyte3 & swap3_sel_byte4) |
|
6703 |
|
|
(rjust0_sel_sbyte4 & swap4_sel_byte4) |
|
6704 |
|
|
(rjust0_sel_sbyte5 & swap5_sel_byte4) |
|
6705 |
|
|
(rjust0_sel_sbyte7 & swap7_sel_byte4) ;
|
6706 |
|
|
|
6707 |
|
|
assign merge0_sel_byte5_m =
|
6708 |
|
|
(rjust0_sel_sbyte2 & swap2_sel_byte5) |
|
6709 |
|
|
(rjust0_sel_sbyte4 & swap4_sel_byte5) |
|
6710 |
|
|
(rjust0_sel_sbyte5 & swap5_sel_byte5) |
|
6711 |
|
|
(rjust0_sel_sbyte6 & swap6_sel_byte5) ;
|
6712 |
|
|
|
6713 |
|
|
assign merge0_sel_byte6_m =
|
6714 |
|
|
(rjust0_sel_sbyte1 & swap1_sel_byte6) |
|
6715 |
|
|
(rjust0_sel_sbyte5 & swap5_sel_byte6) |
|
6716 |
|
|
(rjust0_sel_sbyte6 & swap6_sel_byte6) |
|
6717 |
|
|
(rjust0_sel_sbyte7 & swap7_sel_byte6) ;
|
6718 |
|
|
|
6719 |
|
|
//assign merge0_sel_byte7_m =
|
6720 |
|
|
// (rjust0_sel_sbyte0 & swap0_sel_byte7) |
|
6721 |
|
|
// (rjust0_sel_sbyte4 & swap4_sel_byte7) |
|
6722 |
|
|
// (rjust0_sel_sbyte6 & swap6_sel_byte7) |
|
6723 |
|
|
// (rjust0_sel_sbyte7 & swap7_sel_byte7) ;
|
6724 |
|
|
|
6725 |
|
|
assign merge0_sel_byte7_default_m = ~(merge0_sel_byte4_m | merge0_sel_byte5_m | merge0_sel_byte6_m);
|
6726 |
|
|
|
6727 |
|
|
assign merge0_sel_byte_1h_m =
|
6728 |
|
|
merge0_sel_byte0_m | merge0_sel_byte1_m | merge0_sel_byte2_m | merge0_sel_byte3_m ;
|
6729 |
|
|
|
6730 |
|
|
// Final Merged Byte 1
|
6731 |
|
|
assign merge1_sel_byte0_m =
|
6732 |
|
|
(rjust1_sel_sbyte1 & swap1_sel_byte0) |
|
6733 |
|
|
(rjust1_sel_sbyte3 & swap3_sel_byte0) |
|
6734 |
|
|
(rjust1_sel_sbyte7 & swap7_sel_byte0) ;
|
6735 |
|
|
|
6736 |
|
|
assign merge1_sel_byte1_m =
|
6737 |
|
|
(rjust1_sel_sbyte1 & swap1_sel_byte1) ;
|
6738 |
|
|
|
6739 |
|
|
assign merge1_sel_byte2_m =
|
6740 |
|
|
(rjust1_sel_sbyte1 & swap1_sel_byte2) |
|
6741 |
|
|
(rjust1_sel_sbyte3 & swap3_sel_byte2) |
|
6742 |
|
|
(rjust1_sel_sbyte5 & swap5_sel_byte2) ;
|
6743 |
|
|
|
6744 |
|
|
assign merge1_sel_byte3_m =
|
6745 |
|
|
(rjust1_sel_sbyte3 & swap3_sel_byte3) ;
|
6746 |
|
|
|
6747 |
|
|
assign merge1_sel_byte3_default_m = ~( merge1_sel_byte0_m | merge1_sel_byte1_m | merge1_sel_byte2_m);
|
6748 |
|
|
|
6749 |
|
|
assign merge1_sel_byte4_m =
|
6750 |
|
|
(rjust1_sel_sbyte3 & swap3_sel_byte4) |
|
6751 |
|
|
(rjust1_sel_sbyte5 & swap5_sel_byte4) |
|
6752 |
|
|
(rjust1_sel_sbyte7 & swap7_sel_byte4) ;
|
6753 |
|
|
|
6754 |
|
|
assign merge1_sel_byte5_m =
|
6755 |
|
|
(rjust1_sel_sbyte5 & swap5_sel_byte5) ;
|
6756 |
|
|
|
6757 |
|
|
assign merge1_sel_byte6_m =
|
6758 |
|
|
(rjust1_sel_sbyte1 & swap1_sel_byte6) |
|
6759 |
|
|
(rjust1_sel_sbyte5 & swap5_sel_byte6) |
|
6760 |
|
|
(rjust1_sel_sbyte7 & swap7_sel_byte6) ;
|
6761 |
|
|
|
6762 |
|
|
assign merge1_sel_byte7_m =
|
6763 |
|
|
(rjust1_sel_sbyte7 & swap7_sel_byte7) ;
|
6764 |
|
|
|
6765 |
|
|
assign merge1_sel_byte7_default_m = ~( merge1_sel_byte4_m | merge1_sel_byte5_m | merge1_sel_byte6_m);
|
6766 |
|
|
|
6767 |
|
|
assign merge1_sel_byte_1h_m = ~byp_byte_m &
|
6768 |
|
|
(merge1_sel_byte0_m | merge1_sel_byte1_m | merge1_sel_byte2_m | merge1_sel_byte3_m) ;
|
6769 |
|
|
|
6770 |
|
|
assign merge1_sel_byte_2h_m = ~byp_byte_m &
|
6771 |
|
|
(merge1_sel_byte4_m | merge1_sel_byte5_m | merge1_sel_byte6_m | merge1_sel_byte7_m) ;
|
6772 |
|
|
|
6773 |
|
|
|
6774 |
|
|
// Final Merged Byte 2
|
6775 |
|
|
|
6776 |
|
|
assign merge2_sel_byte1_m =
|
6777 |
|
|
(rjust2_sel_sbyte2 & swap2_sel_byte1) |
|
6778 |
|
|
(rjust2_sel_sbyte6 & swap6_sel_byte1) ;
|
6779 |
|
|
|
6780 |
|
|
assign merge2_sel_byte2_m =
|
6781 |
|
|
(rjust2_sel_sbyte2 & swap2_sel_byte2) ;
|
6782 |
|
|
|
6783 |
|
|
assign merge2_sel_byte5_m =
|
6784 |
|
|
(rjust2_sel_sbyte2 & swap2_sel_byte5) |
|
6785 |
|
|
(rjust2_sel_sbyte6 & swap6_sel_byte5) ;
|
6786 |
|
|
|
6787 |
|
|
assign merge2_sel_byte6_m =
|
6788 |
|
|
(rjust2_sel_sbyte6 & swap6_sel_byte6) ;
|
6789 |
|
|
|
6790 |
|
|
assign merge2_sel_byte6_default_m = ~(merge2_sel_byte1_m | merge2_sel_byte2_m | merge2_sel_byte5_m);
|
6791 |
|
|
|
6792 |
|
|
assign merge2_sel_byte_m = ~byp_byte_m & ~byp_hword_m &
|
6793 |
|
|
(merge2_sel_byte1_m | merge2_sel_byte2_m | merge2_sel_byte5_m | merge2_sel_byte6_m);
|
6794 |
|
|
|
6795 |
|
|
// Final Merged Byte 3
|
6796 |
|
|
assign merge3_sel_byte0_m =
|
6797 |
|
|
(rjust3_sel_sbyte3 & swap3_sel_byte0) |
|
6798 |
|
|
(rjust3_sel_sbyte7 & swap7_sel_byte0) ;
|
6799 |
|
|
|
6800 |
|
|
assign merge3_sel_byte3_m =
|
6801 |
|
|
(rjust3_sel_sbyte3 & swap3_sel_byte3) ;
|
6802 |
|
|
|
6803 |
|
|
assign merge3_sel_byte4_m =
|
6804 |
|
|
(rjust3_sel_sbyte3 & swap3_sel_byte4) |
|
6805 |
|
|
(rjust3_sel_sbyte7 & swap7_sel_byte4) ;
|
6806 |
|
|
|
6807 |
|
|
assign merge3_sel_byte7_m =
|
6808 |
|
|
(rjust3_sel_sbyte7 & swap7_sel_byte7) ;
|
6809 |
|
|
|
6810 |
|
|
assign merge3_sel_byte7_default_m = ~(merge3_sel_byte0_m | merge3_sel_byte3_m | merge3_sel_byte4_m);
|
6811 |
|
|
|
6812 |
|
|
assign merge3_sel_byte_m = ~byp_byte_m & ~byp_hword_m &
|
6813 |
|
|
(merge3_sel_byte0_m | merge3_sel_byte3_m | merge3_sel_byte4_m | merge3_sel_byte7_m);
|
6814 |
|
|
|
6815 |
|
|
// Final Merged Byte 4
|
6816 |
|
|
assign merge4_sel_byte3_m = byp_dword_m & swap4_sel_byte3 ;
|
6817 |
|
|
assign merge4_sel_byte4_m = byp_dword_m & swap4_sel_byte4 ;
|
6818 |
|
|
|
6819 |
|
|
|
6820 |
|
|
// Final Merged Byte 5
|
6821 |
|
|
assign merge5_sel_byte2_m = byp_dword_m & swap5_sel_byte2 ;
|
6822 |
|
|
assign merge5_sel_byte5_m = byp_dword_m & swap5_sel_byte5 ;
|
6823 |
|
|
|
6824 |
|
|
// Final Merged Byte 6
|
6825 |
|
|
assign merge6_sel_byte1_m = byp_dword_m & swap6_sel_byte1 ;
|
6826 |
|
|
assign merge6_sel_byte6_m = byp_dword_m & swap6_sel_byte6 ;
|
6827 |
|
|
|
6828 |
|
|
// Final Merged Byte 7
|
6829 |
|
|
assign merge7_sel_byte0_m = byp_dword_m & swap7_sel_byte0 ;
|
6830 |
|
|
assign merge7_sel_byte7_m = byp_dword_m & swap7_sel_byte7 ;
|
6831 |
|
|
|
6832 |
|
|
|
6833 |
|
|
|
6834 |
|
|
//=========================================================================================
|
6835 |
|
|
// STQ/CAS 2ND PKT FORMATTING
|
6836 |
|
|
//=========================================================================================
|
6837 |
|
|
|
6838 |
|
|
// stq and cas write to an extra buffer. stq always uses a full 64bits.
|
6839 |
|
|
// cas may use either 64b or 32b. stq requires at most endian alignment.
|
6840 |
|
|
// cas may require both address and endian alignment.
|
6841 |
|
|
|
6842 |
|
|
// Byte Alignment. Assume 8 bytes, 7-0
|
6843 |
|
|
// Case 1 : 7,6,5,4,3,2,1,0
|
6844 |
|
|
// Case 2 : 3,2,1,0,0,1,2,3
|
6845 |
|
|
// Case 3 : 0,1,2,3,4,5,6,7
|
6846 |
|
|
|
6847 |
|
|
wire casa_wd_g ;
|
6848 |
|
|
assign casa_wd_g = casa_g & byp_word_g ;
|
6849 |
|
|
wire casa_dwd_g ;
|
6850 |
|
|
assign casa_dwd_g = casa_g & ~byp_word_g ;
|
6851 |
|
|
|
6852 |
|
|
// Change bendian to bendian_g - should not be dependent on fill.
|
6853 |
|
|
|
6854 |
|
|
//assign lsu_atomic_pkt2_bsel_g[2] = // Case 1
|
6855 |
|
|
// (casa_dwd_g & bendian_g) | // bendian stq and dw cas
|
6856 |
|
|
// (casa_wd_g & bendian_g & ldst_va_g[2]) ; // bendian_g wd casa addr to uhalf
|
6857 |
|
|
|
6858 |
|
|
assign lsu_atomic_pkt2_bsel_g[2] = ~| (lsu_atomic_pkt2_bsel_g[1:0]) | rst_tri_en ; //one-hot default
|
6859 |
|
|
|
6860 |
|
|
assign lsu_atomic_pkt2_bsel_g[1] = // Case 2
|
6861 |
|
|
((casa_wd_g & bendian_g & ~ldst_va_g[2]) | // bendian_g wd casa addr to lhalf
|
6862 |
|
|
(casa_wd_g & ~bendian_g & ldst_va_g[2])) & ~rst_tri_en ; // lendian wd casa addr to uhalf
|
6863 |
|
|
assign lsu_atomic_pkt2_bsel_g[0] = // Case 3
|
6864 |
|
|
((casa_dwd_g & ~bendian_g) | // lendian stq and dw cas
|
6865 |
|
|
(casa_wd_g & ~bendian_g & ~ldst_va_g[2])) & ~rst_tri_en ; // lendian wd cas addr to lhalf
|
6866 |
|
|
|
6867 |
|
|
// Alignment done in qdp1
|
6868 |
|
|
|
6869 |
|
|
//=========================================================================================
|
6870 |
|
|
// ASI DECODE
|
6871 |
|
|
//=========================================================================================
|
6872 |
|
|
|
6873 |
|
|
// Note : tlb_byp_asi same as phy_use/phy_byp asi.
|
6874 |
|
|
|
6875 |
|
|
|
6876 |
|
|
lsu_asi_decode asi_decode (/*AUTOINST*/
|
6877 |
|
|
// Outputs
|
6878 |
|
|
.asi_internal_d(asi_internal_d),
|
6879 |
|
|
.nucleus_asi_d(nucleus_asi_d),
|
6880 |
|
|
.primary_asi_d(primary_asi_d),
|
6881 |
|
|
.secondary_asi_d(secondary_asi_d),
|
6882 |
|
|
.lendian_asi_d(lendian_asi_d),
|
6883 |
|
|
.nofault_asi_d(nofault_asi_d),
|
6884 |
|
|
.quad_asi_d (quad_asi_d),
|
6885 |
|
|
.binit_quad_asi_d(binit_quad_asi_d),
|
6886 |
|
|
.dcache_byp_asi_d(dcache_byp_asi_d),
|
6887 |
|
|
.tlb_lng_ltncy_asi_d(tlb_lng_ltncy_asi_d),
|
6888 |
|
|
.tlb_byp_asi_d(tlb_byp_asi_d),
|
6889 |
|
|
.as_if_user_asi_d(as_if_user_asi_d),
|
6890 |
|
|
.atomic_asi_d(atomic_asi_d),
|
6891 |
|
|
.blk_asi_d (blk_asi_d),
|
6892 |
|
|
.dc_diagnstc_asi_d(dc_diagnstc_asi_d),
|
6893 |
|
|
.dtagv_diagnstc_asi_d(dtagv_diagnstc_asi_d),
|
6894 |
|
|
.wr_only_asi_d(wr_only_asi_d),
|
6895 |
|
|
.rd_only_asi_d(rd_only_asi_d),
|
6896 |
|
|
.unimp_asi_d (unimp_asi_d),
|
6897 |
|
|
.ifu_nontlb_asi_d(ifu_nontlb_asi_d),
|
6898 |
|
|
.recognized_asi_d(recognized_asi_d),
|
6899 |
|
|
.ifill_tlb_asi_d(ifill_tlb_asi_d),
|
6900 |
|
|
.dfill_tlb_asi_d(dfill_tlb_asi_d),
|
6901 |
|
|
.rd_only_ltlb_asi_d(rd_only_ltlb_asi_d),
|
6902 |
|
|
.wr_only_ltlb_asi_d(wr_only_ltlb_asi_d),
|
6903 |
|
|
.phy_use_ec_asi_d(phy_use_ec_asi_d),
|
6904 |
|
|
.phy_byp_ec_asi_d(phy_byp_ec_asi_d),
|
6905 |
|
|
.mmu_rd_only_asi_d(mmu_rd_only_asi_d),
|
6906 |
|
|
.intrpt_disp_asi_d(intrpt_disp_asi_d),
|
6907 |
|
|
.dmmu_asi58_d(dmmu_asi58_d),
|
6908 |
|
|
.immu_asi50_d(immu_asi50_d),
|
6909 |
|
|
// Inputs
|
6910 |
|
|
.asi_d (asi_d[7:0]));
|
6911 |
|
|
|
6912 |
|
|
dff_s #(31) asidcd_stge (
|
6913 |
|
|
.din ({asi_internal_d,primary_asi_d,secondary_asi_d,nucleus_asi_d,
|
6914 |
|
|
lendian_asi_d, tlb_byp_asi_d, dcache_byp_asi_d,nofault_asi_d,
|
6915 |
|
|
tlb_lng_ltncy_asi_d,as_if_user_asi_d,atomic_asi_d, blk_asi_d,
|
6916 |
|
|
dc_diagnstc_asi_d,dtagv_diagnstc_asi_d,
|
6917 |
|
|
wr_only_asi_d, rd_only_asi_d,mmu_rd_only_asi_d,unimp_asi_d,dmmu_asi58_d, immu_asi50_d, quad_asi_d, binit_quad_asi_d,
|
6918 |
|
|
ifu_nontlb_asi_d,recognized_asi_d, ifill_tlb_asi_d,
|
6919 |
|
|
dfill_tlb_asi_d, rd_only_ltlb_asi_d,wr_only_ltlb_asi_d,phy_use_ec_asi_d, phy_byp_ec_asi_d, intrpt_disp_asi_d}),
|
6920 |
|
|
.q ({asi_internal_e,primary_asi_e,secondary_asi_e,nucleus_asi_e,
|
6921 |
|
|
lendian_asi_e, tlb_byp_asi_e, dcache_byp_asi_e,nofault_asi_e,
|
6922 |
|
|
tlb_lng_ltncy_asi_e,as_if_user_asi_e,atomic_asi_e, blk_asi_e,
|
6923 |
|
|
dc_diagnstc_asi_e,dtagv_diagnstc_asi_e,
|
6924 |
|
|
wr_only_asi_e, rd_only_asi_e,mmu_rd_only_asi_e,unimp_asi_e,dmmu_asi58_e, immu_asi50_e, quad_asi_e, binit_quad_asi_e,
|
6925 |
|
|
ifu_nontlb_asi_e,recognized_asi_e,ifill_tlb_asi_e,
|
6926 |
|
|
dfill_tlb_asi_e,rd_only_ltlb_asi_e,wr_only_ltlb_asi_e,phy_use_ec_asi_e, phy_byp_ec_asi_e, intrpt_disp_asi_e}),
|
6927 |
|
|
.clk (clk),
|
6928 |
|
|
.se (se), .si (), .so ()
|
6929 |
|
|
);
|
6930 |
|
|
|
6931 |
|
|
assign lsu_ffu_blk_asi_e = blk_asi_e & alt_space_e;
|
6932 |
|
|
assign lsu_quad_asi_e = quad_asi_e ;
|
6933 |
|
|
|
6934 |
|
|
wire unimp_asi_tmp ;
|
6935 |
|
|
dff_s #(23) asidcd_stgm (
|
6936 |
|
|
.din ({asi_internal_e,dcache_byp_asi_e,nofault_asi_e,lendian_asi_e,tlb_lng_ltncy_asi_e,
|
6937 |
|
|
as_if_user_asi_e,atomic_asi_e, blk_asi_e,dc_diagnstc_asi_e,dtagv_diagnstc_asi_e,
|
6938 |
|
|
wr_only_asi_e, rd_only_asi_e,mmu_rd_only_asi_e,unimp_asi_e,dmmu_asi58_e, immu_asi50_e, quad_asi_e,binit_quad_asi_e,recognized_asi_e,
|
6939 |
|
|
ifu_nontlb_asi_e,phy_use_ec_asi_e, phy_byp_ec_asi_e, intrpt_disp_asi_e}),
|
6940 |
|
|
.q ({asi_internal_m,dcache_byp_asi_m,nofault_asi_m,lendian_asi_m,tlb_lng_ltncy_asi_m,
|
6941 |
|
|
as_if_user_asi_m,atomic_asi_m, blk_asi_m,dc_diagnstc_asi_m,dtagv_diagnstc_asi_m,
|
6942 |
|
|
wr_only_asi_m, rd_only_asi_m,mmu_rd_only_asi_m,unimp_asi_tmp,dmmu_asi58_m, immu_asi50_m, quad_asi_m,binit_quad_asi_m,recognized_asi_tmp,
|
6943 |
|
|
ifu_nontlb_asi_m,phy_use_ec_asi_m, phy_byp_ec_asi_m, intrpt_disp_asi_m}),
|
6944 |
|
|
.clk (clk),
|
6945 |
|
|
.se (se), .si (), .so ()
|
6946 |
|
|
);
|
6947 |
|
|
|
6948 |
|
|
assign lsu_blk_asi_m = blk_asi_m ;
|
6949 |
|
|
|
6950 |
|
|
wire pa_wtchpt_unimp_m ; // Bug 3408
|
6951 |
|
|
wire d_tsb_unimp_m, i_tsb_unimp_m, pctxt_unimp_m, sctxt_unimp_m;
|
6952 |
|
|
wire unimp_m;
|
6953 |
|
|
|
6954 |
|
|
assign pa_wtchpt_unimp_m = dmmu_asi58_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h40);
|
6955 |
|
|
assign d_tsb_unimp_m = dmmu_asi58_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h28);
|
6956 |
|
|
assign pctxt_unimp_m = dmmu_asi58_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h8);
|
6957 |
|
|
assign sctxt_unimp_m = dmmu_asi58_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h10);
|
6958 |
|
|
assign i_tsb_unimp_m = immu_asi50_m & (lsu_ldst_va_b7_b0_m[7:0] == 8'h28);
|
6959 |
|
|
assign unimp_m = pa_wtchpt_unimp_m |
|
6960 |
|
|
d_tsb_unimp_m | i_tsb_unimp_m |
|
6961 |
|
|
pctxt_unimp_m | sctxt_unimp_m;
|
6962 |
|
|
|
6963 |
|
|
assign unimp_asi_m = unimp_asi_tmp | unimp_m ;
|
6964 |
|
|
assign recognized_asi_m = recognized_asi_tmp | unimp_m ;
|
6965 |
|
|
|
6966 |
|
|
dff_s #(12) asidcd_stgg (
|
6967 |
|
|
.din ({asi_internal_m,dcache_byp_asi_m, lendian_asi_m,tlb_lng_ltncy_asi_m,
|
6968 |
|
|
blk_asi_m,dc_diagnstc_asi_m,dtagv_diagnstc_asi_m,quad_asi_m,
|
6969 |
|
|
binit_quad_asi_m,recognized_asi_m,ifu_nontlb_asi_m, intrpt_disp_asi_m}),
|
6970 |
|
|
.q ({asi_internal_g,dcache_byp_asi_g, lendian_asi_g,tlb_lng_ltncy_asi_g,
|
6971 |
|
|
blk_asi_g,dc_diagnstc_asi_g,dtagv_diagnstc_asi_g,quad_asi_g,
|
6972 |
|
|
binit_quad_asi_g,recognized_asi_g,ifu_nontlb_asi_g, intrpt_disp_asi_g}),
|
6973 |
|
|
.clk (clk),
|
6974 |
|
|
.se (se), .si (), .so ()
|
6975 |
|
|
);
|
6976 |
|
|
|
6977 |
|
|
//assign lsu_quad_asi_g = quad_asi_g;
|
6978 |
|
|
assign ncache_asild_rq_g = dcache_byp_asi_g & altspace_ldst_g ;
|
6979 |
|
|
|
6980 |
|
|
//st data alignment control signals
|
6981 |
|
|
wire st_sz_hw_g, st_sz_w_g, st_sz_dw_g, stdbl_g;
|
6982 |
|
|
wire stdbl_m;
|
6983 |
|
|
|
6984 |
|
|
//assign stdbl_m = ldst_dbl_m & (~lsu_alt_space_m | (lsu_alt_space_m & ~blk_asi_m)) ;
|
6985 |
|
|
assign stdbl_m = ldst_dbl_m ;
|
6986 |
|
|
|
6987 |
|
|
dff_s #(4) ff_st_sz_m (
|
6988 |
|
|
.din ({hw_size, wd_size, dw_size, stdbl_m }),
|
6989 |
|
|
.q ({st_sz_hw_g, st_sz_w_g, st_sz_dw_g, stdbl_g}),
|
6990 |
|
|
.clk (clk),
|
6991 |
|
|
.se (se), .si (), .so ()
|
6992 |
|
|
);
|
6993 |
|
|
|
6994 |
|
|
|
6995 |
|
|
//assign bendian = lsu_bendian_access_g ; // bendian store
|
6996 |
|
|
|
6997 |
|
|
wire swap_sel_default_g, swap_sel_default_byte_7_2_g, st_hw_le_g,st_w_or_dbl_le_g,st_x_le_g;
|
6998 |
|
|
assign bendian_g = ~l1hit_lendian_g ;
|
6999 |
|
|
//assign swap_sel_default_g = (bendian_g | (~bendian_g & st_sz_b_g)) ;
|
7000 |
|
|
|
7001 |
|
|
assign swap_sel_default_g = ~ (st_hw_le_g | st_w_or_dbl_le_g | st_x_le_g);
|
7002 |
|
|
assign swap_sel_default_byte_7_2_g = ~ (st_w_or_dbl_le_g | st_x_le_g);
|
7003 |
|
|
|
7004 |
|
|
assign st_hw_le_g = (st_sz_hw_g & ~bendian_g) & (~stdbl_g | fp_ldst_g) & st_inst_vld_unflushed ; //0-in bug
|
7005 |
|
|
//bug 3169
|
7006 |
|
|
// std(a) on floating point is the same as stx(a)
|
7007 |
|
|
assign st_w_or_dbl_le_g = ((st_sz_w_g | (stdbl_g & ~fp_ldst_g)) & ~bendian_g) & st_inst_vld_unflushed ;
|
7008 |
|
|
assign st_x_le_g = (st_sz_dw_g & (~stdbl_g | fp_ldst_g) & ~bendian_g) & st_inst_vld_unflushed;
|
7009 |
|
|
|
7010 |
|
|
wire blkst_m_tmp ;
|
7011 |
|
|
dff_s stgm_bst (
|
7012 |
|
|
.din (ffu_lsu_blk_st_e),
|
7013 |
|
|
.q (blkst_m_tmp),
|
7014 |
|
|
.clk (clk),
|
7015 |
|
|
.se (se), .si (), .so ()
|
7016 |
|
|
);
|
7017 |
|
|
|
7018 |
|
|
assign blkst_m = blkst_m_tmp & ~(st_inst_vld_m | flsh_inst_m
|
7019 |
|
|
| ld_inst_vld_m) ; // Bug 3444
|
7020 |
|
|
|
7021 |
|
|
assign lsu_blk_st_m = blkst_m ;
|
7022 |
|
|
|
7023 |
|
|
dff_s stgg_bst (
|
7024 |
|
|
.din (blkst_m),
|
7025 |
|
|
.q (blkst_g),
|
7026 |
|
|
.clk (clk),
|
7027 |
|
|
.se (se), .si (), .so ()
|
7028 |
|
|
);
|
7029 |
|
|
|
7030 |
|
|
wire bst_swap_sel_default_g, bst_swap_sel_default_byte_7_2_g,bst_st_hw_le_g,bst_st_w_or_dbl_le_g,bst_st_x_le_g;
|
7031 |
|
|
assign lsu_swap_sel_default_g = (blkst_g ? bst_swap_sel_default_g : swap_sel_default_g) | rst_tri_en ;
|
7032 |
|
|
assign lsu_swap_sel_default_byte_7_2_g = (blkst_g ? bst_swap_sel_default_byte_7_2_g : swap_sel_default_byte_7_2_g)
|
7033 |
|
|
| rst_tri_en ;
|
7034 |
|
|
|
7035 |
|
|
assign lsu_st_hw_le_g = (blkst_g ? bst_st_hw_le_g : st_hw_le_g) & ~rst_tri_en ;
|
7036 |
|
|
assign lsu_st_w_or_dbl_le_g = (blkst_g ? bst_st_w_or_dbl_le_g : st_w_or_dbl_le_g) & ~rst_tri_en ;
|
7037 |
|
|
assign lsu_st_x_le_g = (blkst_g ? bst_st_x_le_g : st_x_le_g) & ~rst_tri_en ;
|
7038 |
|
|
|
7039 |
|
|
|
7040 |
|
|
//=========================================================================================
|
7041 |
|
|
// BLK STORE
|
7042 |
|
|
//=========================================================================================
|
7043 |
|
|
|
7044 |
|
|
// Blk-St Handling : Snap state in g-stage of issue from IFU.
|
7045 |
|
|
|
7046 |
|
|
wire snap_blk_st_m,snap_blk_st_g ;
|
7047 |
|
|
assign snap_blk_st_m = st_inst_vld_m & blk_asi_m & lsu_alt_space_m & fp_ldst_m;
|
7048 |
|
|
|
7049 |
|
|
assign lsu_snap_blk_st_m = snap_blk_st_m ;
|
7050 |
|
|
|
7051 |
|
|
wire snap_blk_st_local_m;
|
7052 |
|
|
assign snap_blk_st_local_m = snap_blk_st_m & ifu_tlu_inst_vld_m ;
|
7053 |
|
|
|
7054 |
|
|
dff_s stgg_snap (
|
7055 |
|
|
.din (snap_blk_st_local_m),
|
7056 |
|
|
.q (snap_blk_st_g),
|
7057 |
|
|
.clk (clk),
|
7058 |
|
|
.se (se), .si (), .so ()
|
7059 |
|
|
);
|
7060 |
|
|
|
7061 |
|
|
// output to be used in g-stage.
|
7062 |
|
|
dffe_s #(5) bst_state_g (
|
7063 |
|
|
.din ({lsu_swap_sel_default_g, lsu_swap_sel_default_byte_7_2_g, lsu_st_hw_le_g,
|
7064 |
|
|
lsu_st_w_or_dbl_le_g,lsu_st_x_le_g}),
|
7065 |
|
|
.q ({bst_swap_sel_default_g, bst_swap_sel_default_byte_7_2_g, bst_st_hw_le_g,
|
7066 |
|
|
bst_st_w_or_dbl_le_g,bst_st_x_le_g}),
|
7067 |
|
|
.en (snap_blk_st_g),
|
7068 |
|
|
.clk (clk),
|
7069 |
|
|
.se (se), .si (), .so ()
|
7070 |
|
|
);
|
7071 |
|
|
|
7072 |
|
|
|
7073 |
|
|
// snapped in g, used in m
|
7074 |
|
|
|
7075 |
|
|
wire [39:10] blkst_pgnum_m;
|
7076 |
|
|
|
7077 |
|
|
dffe_s #(30) bst_pg_g (
|
7078 |
|
|
.din (tlb_pgnum[39:10]),
|
7079 |
|
|
.q (blkst_pgnum_m[39:10]),
|
7080 |
|
|
.en (snap_blk_st_g),
|
7081 |
|
|
.clk (clk),
|
7082 |
|
|
.se (se), .si (), .so ()
|
7083 |
|
|
);
|
7084 |
|
|
|
7085 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b10 (.a(blkst_pgnum_m[10]), .z(lsu_blkst_pgnum_m[10]));
|
7086 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b11 (.a(blkst_pgnum_m[11]), .z(lsu_blkst_pgnum_m[11]));
|
7087 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b12 (.a(blkst_pgnum_m[12]), .z(lsu_blkst_pgnum_m[12]));
|
7088 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b13 (.a(blkst_pgnum_m[13]), .z(lsu_blkst_pgnum_m[13]));
|
7089 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b14 (.a(blkst_pgnum_m[14]), .z(lsu_blkst_pgnum_m[14]));
|
7090 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b15 (.a(blkst_pgnum_m[15]), .z(lsu_blkst_pgnum_m[15]));
|
7091 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b16 (.a(blkst_pgnum_m[16]), .z(lsu_blkst_pgnum_m[16]));
|
7092 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b17 (.a(blkst_pgnum_m[17]), .z(lsu_blkst_pgnum_m[17]));
|
7093 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b18 (.a(blkst_pgnum_m[18]), .z(lsu_blkst_pgnum_m[18]));
|
7094 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b19 (.a(blkst_pgnum_m[19]), .z(lsu_blkst_pgnum_m[19]));
|
7095 |
|
|
|
7096 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b20 (.a(blkst_pgnum_m[20]), .z(lsu_blkst_pgnum_m[20]));
|
7097 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b21 (.a(blkst_pgnum_m[21]), .z(lsu_blkst_pgnum_m[21]));
|
7098 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b22 (.a(blkst_pgnum_m[22]), .z(lsu_blkst_pgnum_m[22]));
|
7099 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b23 (.a(blkst_pgnum_m[23]), .z(lsu_blkst_pgnum_m[23]));
|
7100 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b24 (.a(blkst_pgnum_m[24]), .z(lsu_blkst_pgnum_m[24]));
|
7101 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b25 (.a(blkst_pgnum_m[25]), .z(lsu_blkst_pgnum_m[25]));
|
7102 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b26 (.a(blkst_pgnum_m[26]), .z(lsu_blkst_pgnum_m[26]));
|
7103 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b27 (.a(blkst_pgnum_m[27]), .z(lsu_blkst_pgnum_m[27]));
|
7104 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b28 (.a(blkst_pgnum_m[28]), .z(lsu_blkst_pgnum_m[28]));
|
7105 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b29 (.a(blkst_pgnum_m[29]), .z(lsu_blkst_pgnum_m[29]));
|
7106 |
|
|
|
7107 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b30 (.a(blkst_pgnum_m[30]), .z(lsu_blkst_pgnum_m[30]));
|
7108 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b31 (.a(blkst_pgnum_m[31]), .z(lsu_blkst_pgnum_m[31]));
|
7109 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b32 (.a(blkst_pgnum_m[32]), .z(lsu_blkst_pgnum_m[32]));
|
7110 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b33 (.a(blkst_pgnum_m[33]), .z(lsu_blkst_pgnum_m[33]));
|
7111 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b34 (.a(blkst_pgnum_m[34]), .z(lsu_blkst_pgnum_m[34]));
|
7112 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b35 (.a(blkst_pgnum_m[35]), .z(lsu_blkst_pgnum_m[35]));
|
7113 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b36 (.a(blkst_pgnum_m[36]), .z(lsu_blkst_pgnum_m[36]));
|
7114 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b37 (.a(blkst_pgnum_m[37]), .z(lsu_blkst_pgnum_m[37]));
|
7115 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b38 (.a(blkst_pgnum_m[38]), .z(lsu_blkst_pgnum_m[38]));
|
7116 |
|
|
bw_u1_minbuf_5x UZfix_lsu_blkst_pgnum_m_b39 (.a(blkst_pgnum_m[39]), .z(lsu_blkst_pgnum_m[39]));
|
7117 |
|
|
|
7118 |
|
|
//=========================================================================================
|
7119 |
|
|
// Prefetch Count
|
7120 |
|
|
//=========================================================================================
|
7121 |
|
|
|
7122 |
|
|
wire [3:0] lsu_cpx_pref_ack;
|
7123 |
|
|
wire [3:0] no_spc_pref;
|
7124 |
|
|
|
7125 |
|
|
wire [3:0] pref_ackcnt0,pref_ackcnt1,pref_ackcnt2,pref_ackcnt3 ;
|
7126 |
|
|
wire [3:0] pref_ackcnt0_din,pref_ackcnt1_din,pref_ackcnt2_din,pref_ackcnt3_din ;
|
7127 |
|
|
|
7128 |
|
|
wire [3:0] pref_ackcnt_incr, pref_ackcnt_decr ;
|
7129 |
|
|
wire [3:0] pref_ackcnt_mx_incr, pref_ackcnt_mx_decr ;
|
7130 |
|
|
|
7131 |
|
|
wire lsu_pref_pcx_req_d1;
|
7132 |
|
|
|
7133 |
|
|
dff_s #(1) pref_pcx_req_stg (
|
7134 |
|
|
.din (lsu_pref_pcx_req),
|
7135 |
|
|
.q (lsu_pref_pcx_req_d1),
|
7136 |
|
|
.clk (clk),
|
7137 |
|
|
.se (se), .si (), .so ()
|
7138 |
|
|
);
|
7139 |
|
|
|
7140 |
|
|
assign lsu_pcx_pref_issue[0] = lsu_pref_pcx_req_d1 & lsu_ld_pcx_rq_sel_d2[0] & ~lsu_pcx_req_squash_d1;
|
7141 |
|
|
assign lsu_pcx_pref_issue[1] = lsu_pref_pcx_req_d1 & lsu_ld_pcx_rq_sel_d2[1] & ~lsu_pcx_req_squash_d1;
|
7142 |
|
|
assign lsu_pcx_pref_issue[2] = lsu_pref_pcx_req_d1 & lsu_ld_pcx_rq_sel_d2[2] & ~lsu_pcx_req_squash_d1;
|
7143 |
|
|
assign lsu_pcx_pref_issue[3] = lsu_pref_pcx_req_d1 & lsu_ld_pcx_rq_sel_d2[3] & ~lsu_pcx_req_squash_d1;
|
7144 |
|
|
|
7145 |
|
|
|
7146 |
|
|
wire [3:0] pref_acknt_mx_incr_sel;
|
7147 |
|
|
assign pref_acknt_mx_incr_sel[3:0] = lsu_pcx_pref_issue[3:0];
|
7148 |
|
|
|
7149 |
|
|
assign pref_ackcnt_mx_incr[3:0] =
|
7150 |
|
|
(pref_acknt_mx_incr_sel[0] ? pref_ackcnt0[3:0] : 4'b0) |
|
7151 |
|
|
(pref_acknt_mx_incr_sel[1] ? pref_ackcnt1[3:0] : 4'b0) |
|
7152 |
|
|
(pref_acknt_mx_incr_sel[2] ? pref_ackcnt2[3:0] : 4'b0) |
|
7153 |
|
|
(pref_acknt_mx_incr_sel[3] ? pref_ackcnt3[3:0] : 4'b0) ;
|
7154 |
|
|
|
7155 |
|
|
|
7156 |
|
|
//====================================================================================
|
7157 |
|
|
// prefetch ack back from CPX
|
7158 |
|
|
wire dcfill_active_e;
|
7159 |
|
|
assign dcfill_active_e = lsu_dfq_ld_vld & ~memref_e ;
|
7160 |
|
|
|
7161 |
|
|
wire dfq_thread0, dfq_thread1, dfq_thread2, dfq_thread3;
|
7162 |
|
|
|
7163 |
|
|
assign dfq_thread0 = dfill_thread0;
|
7164 |
|
|
assign dfq_thread1 = dfill_thread1;
|
7165 |
|
|
assign dfq_thread2 = dfill_thread2;
|
7166 |
|
|
assign dfq_thread3 = dfill_thread3;
|
7167 |
|
|
|
7168 |
|
|
assign lsu_cpx_pref_ack[0] = dfq_thread0 & dcfill_active_e & lsu_cpx_pkt_prefetch2;
|
7169 |
|
|
assign lsu_cpx_pref_ack[1] = dfq_thread1 & dcfill_active_e & lsu_cpx_pkt_prefetch2;
|
7170 |
|
|
assign lsu_cpx_pref_ack[2] = dfq_thread2 & dcfill_active_e & lsu_cpx_pkt_prefetch2;
|
7171 |
|
|
assign lsu_cpx_pref_ack[3] = dfq_thread3 & dcfill_active_e & lsu_cpx_pkt_prefetch2;
|
7172 |
|
|
|
7173 |
|
|
wire [3:0] pref_acknt_mx_decr_sel;
|
7174 |
|
|
assign pref_acknt_mx_decr_sel[3:0] = lsu_cpx_pref_ack[3:0];
|
7175 |
|
|
|
7176 |
|
|
assign pref_ackcnt_mx_decr[3:0] =
|
7177 |
|
|
(pref_acknt_mx_decr_sel[0] ? pref_ackcnt0[3:0] : 4'b0) |
|
7178 |
|
|
(pref_acknt_mx_decr_sel[1] ? pref_ackcnt1[3:0] : 4'b0) |
|
7179 |
|
|
(pref_acknt_mx_decr_sel[2] ? pref_ackcnt2[3:0] : 4'b0) |
|
7180 |
|
|
(pref_acknt_mx_decr_sel[3] ? pref_ackcnt3[3:0] : 4'b0) ;
|
7181 |
|
|
|
7182 |
|
|
|
7183 |
|
|
assign pref_ackcnt_incr[3:0] = pref_ackcnt_mx_incr[3:0] + 4'b0001 ;
|
7184 |
|
|
assign pref_ackcnt_decr[3:0] = pref_ackcnt_mx_decr[3:0] - 4'b0001 ;
|
7185 |
|
|
|
7186 |
|
|
assign pref_ackcnt0_din[3:0] = lsu_cpx_pref_ack[0] ? pref_ackcnt_decr[3:0] : pref_ackcnt_incr[3:0] ;
|
7187 |
|
|
assign pref_ackcnt1_din[3:0] = lsu_cpx_pref_ack[1] ? pref_ackcnt_decr[3:0] : pref_ackcnt_incr[3:0] ;
|
7188 |
|
|
assign pref_ackcnt2_din[3:0] = lsu_cpx_pref_ack[2] ? pref_ackcnt_decr[3:0] : pref_ackcnt_incr[3:0] ;
|
7189 |
|
|
assign pref_ackcnt3_din[3:0] = lsu_cpx_pref_ack[3] ? pref_ackcnt_decr[3:0] : pref_ackcnt_incr[3:0] ;
|
7190 |
|
|
|
7191 |
|
|
wire [3:0] pref_ackcnt_en ;
|
7192 |
|
|
// if both occur in the same cycle then they cancel out.
|
7193 |
|
|
assign pref_ackcnt_en[0] = lsu_pcx_pref_issue[0] ^ lsu_cpx_pref_ack[0] ;
|
7194 |
|
|
assign pref_ackcnt_en[1] = lsu_pcx_pref_issue[1] ^ lsu_cpx_pref_ack[1] ;
|
7195 |
|
|
assign pref_ackcnt_en[2] = lsu_pcx_pref_issue[2] ^ lsu_cpx_pref_ack[2] ;
|
7196 |
|
|
assign pref_ackcnt_en[3] = lsu_pcx_pref_issue[3] ^ lsu_cpx_pref_ack[3] ;
|
7197 |
|
|
|
7198 |
|
|
// Thread0
|
7199 |
|
|
dffre_s #(4) pref_ackcnt0_ff (
|
7200 |
|
|
.din (pref_ackcnt0_din[3:0]),
|
7201 |
|
|
.q (pref_ackcnt0[3:0]),
|
7202 |
|
|
.rst (reset), .en (pref_ackcnt_en[0]),
|
7203 |
|
|
.clk (clk),
|
7204 |
|
|
.se (se), .si (), .so ()
|
7205 |
|
|
);
|
7206 |
|
|
|
7207 |
|
|
// Thread1
|
7208 |
|
|
dffre_s #(4) pref_ackcnt1_ff (
|
7209 |
|
|
.din (pref_ackcnt1_din[3:0]),
|
7210 |
|
|
.q (pref_ackcnt1[3:0]),
|
7211 |
|
|
.rst (reset), .en (pref_ackcnt_en[1]),
|
7212 |
|
|
.clk (clk),
|
7213 |
|
|
.se (se), .si (), .so ()
|
7214 |
|
|
);
|
7215 |
|
|
|
7216 |
|
|
// Thread2
|
7217 |
|
|
dffre_s #(4) pref_ackcnt2_ff (
|
7218 |
|
|
.din (pref_ackcnt2_din[3:0]),
|
7219 |
|
|
.q (pref_ackcnt2[3:0]),
|
7220 |
|
|
.rst (reset), .en (pref_ackcnt_en[2]),
|
7221 |
|
|
.clk (clk),
|
7222 |
|
|
.se (se), .si (), .so ()
|
7223 |
|
|
);
|
7224 |
|
|
|
7225 |
|
|
// Thread3
|
7226 |
|
|
dffre_s #(4) pref_ackcnt3_ff (
|
7227 |
|
|
.din (pref_ackcnt3_din[3:0]),
|
7228 |
|
|
.q (pref_ackcnt3[3:0]),
|
7229 |
|
|
.rst (reset), .en (pref_ackcnt_en[3]),
|
7230 |
|
|
.clk (clk),
|
7231 |
|
|
.se (se), .si (), .so ()
|
7232 |
|
|
);
|
7233 |
|
|
|
7234 |
|
|
assign no_spc_pref[0] = pref_ackcnt0[3] ;
|
7235 |
|
|
assign no_spc_pref[1] = pref_ackcnt1[3] ;
|
7236 |
|
|
assign no_spc_pref[2] = pref_ackcnt2[3] ;
|
7237 |
|
|
assign no_spc_pref[3] = pref_ackcnt3[3] ;
|
7238 |
|
|
|
7239 |
|
|
assign lsu_no_spc_pref[3:0] = no_spc_pref[3:0];
|
7240 |
|
|
|
7241 |
|
|
//====================================================================
|
7242 |
|
|
wire lsu_bist_e;
|
7243 |
|
|
|
7244 |
|
|
assign lsu_bist_e = lsu_bist_wvld_e | lsu_bist_rvld_e;
|
7245 |
|
|
|
7246 |
|
|
wire [10:0] lmq_pcx_pkt_addr_din;
|
7247 |
|
|
|
7248 |
|
|
wire [3:0] dfq_byp_thrd_sel;
|
7249 |
|
|
|
7250 |
|
|
mux4ds #(11) lmq_pcx_pkt_addr_mux (
|
7251 |
|
|
.in0 ({lmq0_pcx_pkt_addr[10:0]}),
|
7252 |
|
|
.in1 ({lmq1_pcx_pkt_addr[10:0]}),
|
7253 |
|
|
.in2 ({lmq2_pcx_pkt_addr[10:0]}),
|
7254 |
|
|
.in3 ({lmq3_pcx_pkt_addr[10:0]}),
|
7255 |
|
|
.sel0(dfq_byp_thrd_sel[0]),
|
7256 |
|
|
.sel1(dfq_byp_thrd_sel[1]),
|
7257 |
|
|
.sel2(dfq_byp_thrd_sel[2]),
|
7258 |
|
|
.sel3(dfq_byp_thrd_sel[3]),
|
7259 |
|
|
.dout({lmq_pcx_pkt_addr_din[10:0]})
|
7260 |
|
|
);
|
7261 |
|
|
|
7262 |
|
|
dffe_s #(11) lmq_pcx_pkt_addr_ff (
|
7263 |
|
|
.din ({lmq_pcx_pkt_addr_din[10:0]}),
|
7264 |
|
|
.q ({lmq_pcx_pkt_addr[10:0]}),
|
7265 |
|
|
.en (dfq_byp_ff_en),
|
7266 |
|
|
.clk (clk),
|
7267 |
|
|
.se (se), .si (), .so ()
|
7268 |
|
|
);
|
7269 |
|
|
|
7270 |
|
|
|
7271 |
|
|
wire [10:4] lmq_pcx_pkt_addr_minbf;
|
7272 |
|
|
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b10 (.a(lmq_pcx_pkt_addr[10]), .z(lmq_pcx_pkt_addr_minbf[10]));
|
7273 |
|
|
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b9 (.a(lmq_pcx_pkt_addr[9]), .z(lmq_pcx_pkt_addr_minbf[9]));
|
7274 |
|
|
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b8 (.a(lmq_pcx_pkt_addr[8]), .z(lmq_pcx_pkt_addr_minbf[8]));
|
7275 |
|
|
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b7 (.a(lmq_pcx_pkt_addr[7]), .z(lmq_pcx_pkt_addr_minbf[7]));
|
7276 |
|
|
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b6 (.a(lmq_pcx_pkt_addr[6]), .z(lmq_pcx_pkt_addr_minbf[6]));
|
7277 |
|
|
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b5 (.a(lmq_pcx_pkt_addr[5]), .z(lmq_pcx_pkt_addr_minbf[5]));
|
7278 |
|
|
bw_u1_minbuf_5x UZfix_lmq_pcx_pkt_addr_minbf_b4 (.a(lmq_pcx_pkt_addr[4]), .z(lmq_pcx_pkt_addr_minbf[4]));
|
7279 |
|
|
|
7280 |
|
|
|
7281 |
|
|
assign lmq_ld_addr_b3 = lmq_pcx_pkt_addr[3];
|
7282 |
|
|
|
7283 |
|
|
|
7284 |
|
|
assign dcache_fill_addr_e[10:0] =
|
7285 |
|
|
{11{lsu_dc_iob_access_e}} & {dcache_iob_addr_e[7:0],3'b000} |
|
7286 |
|
|
{11{lsu_bist_wvld_e | lsu_bist_rvld_e}} & {mbist_dcache_index[6:0], mbist_dcache_word, 3'b000} |
|
7287 |
|
|
{11{lsu_diagnstc_wr_src_sel_e}} & lsu_diagnstc_wr_addr_e[10:0] |
|
7288 |
|
|
{11{lsu_dfq_st_vld}} & st_dcfill_addr[10:0] |
|
7289 |
|
|
{11{lsu_dfq_ld_vld}} & {lmq_pcx_pkt_addr_minbf[10:4], lmq_pcx_pkt_addr[3:0]};
|
7290 |
|
|
|
7291 |
|
|
assign lsu_dcache_fill_addr_e[10:3] = dcache_fill_addr_e[10:3];
|
7292 |
|
|
|
7293 |
|
|
wire [10:4] dcache_fill_addr_e_tmp;
|
7294 |
|
|
assign dcache_fill_addr_e_tmp[10:4] = dcache_fill_addr_e[10:4];
|
7295 |
|
|
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b10 ( .a(dcache_fill_addr_e_tmp[10]), .z(lsu_dcache_fill_addr_e_err[10]));
|
7296 |
|
|
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b9 ( .a(dcache_fill_addr_e_tmp[9]), .z(lsu_dcache_fill_addr_e_err[9] ));
|
7297 |
|
|
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b8 ( .a(dcache_fill_addr_e_tmp[8]), .z(lsu_dcache_fill_addr_e_err[8]));
|
7298 |
|
|
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b7 ( .a(dcache_fill_addr_e_tmp[7]), .z(lsu_dcache_fill_addr_e_err[7]));
|
7299 |
|
|
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b6 ( .a(dcache_fill_addr_e_tmp[6]), .z(lsu_dcache_fill_addr_e_err[6]));
|
7300 |
|
|
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b5 ( .a(dcache_fill_addr_e_tmp[5]), .z(lsu_dcache_fill_addr_e_err[5]));
|
7301 |
|
|
bw_u1_buf_30x UZfix_lsu_dcache_fill_addr_e_err_b4 ( .a(dcache_fill_addr_e_tmp[4]), .z(lsu_dcache_fill_addr_e_err[4]));
|
7302 |
|
|
|
7303 |
|
|
// used as ld bypass
|
7304 |
|
|
assign dcache_wr_addr_e[2:0] = dcache_fill_addr_e[2:0];
|
7305 |
|
|
|
7306 |
|
|
//ldfill doesn't need to create wrt byte msk, always fill one line
|
7307 |
|
|
assign waddr_enc[3:0] =
|
7308 |
|
|
{4{lsu_dc_iob_access_e}} & {dcache_iob_addr_e[0],3'b000} |
|
7309 |
|
|
{4{lsu_bist_e}} & {mbist_dcache_word, 3'b000} |
|
7310 |
|
|
{4{lsu_diagnstc_wr_src_sel_e}} & lsu_diagnstc_wr_addr_e[3:0] |
|
7311 |
|
|
{4{lsu_dfq_st_vld}} & st_dcfill_addr[3:0] ;
|
7312 |
|
|
|
7313 |
|
|
//==============================================================
|
7314 |
|
|
/*
|
7315 |
|
|
dff_s #(4) lsu_thread_stgg (
|
7316 |
|
|
.din ({thread3_m, thread2_m, thread1_m,thread0_m}),
|
7317 |
|
|
.q (lsu_thread_g[3:0]),
|
7318 |
|
|
.clk (clk),
|
7319 |
|
|
.se (se), .si (), .so ()
|
7320 |
|
|
);
|
7321 |
|
|
*/
|
7322 |
|
|
assign lsu_thread_g[3] = thread3_g;
|
7323 |
|
|
assign lsu_thread_g[2] = thread2_g;
|
7324 |
|
|
assign lsu_thread_g[1] = thread1_g;
|
7325 |
|
|
assign lsu_thread_g[0] = thread0_g;
|
7326 |
|
|
|
7327 |
|
|
//===============================================================
|
7328 |
|
|
//LMQ thread sel
|
7329 |
|
|
//===============================================================
|
7330 |
|
|
//lmq_ldd_vld
|
7331 |
|
|
assign dfq_byp_thrd_sel[0] = ~lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0];
|
7332 |
|
|
assign dfq_byp_thrd_sel[1] = ~lsu_dfq_byp_tid[1] & lsu_dfq_byp_tid[0];
|
7333 |
|
|
assign dfq_byp_thrd_sel[2] = lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0];
|
7334 |
|
|
assign dfq_byp_thrd_sel[3] = lsu_dfq_byp_tid[1] & lsu_dfq_byp_tid[0];
|
7335 |
|
|
|
7336 |
|
|
wire lmq_ldd_vld_din;
|
7337 |
|
|
|
7338 |
|
|
mux4ds #(1) lmq_ldd_vld_mux (
|
7339 |
|
|
.in0 ({lmq0_ldd_vld}),
|
7340 |
|
|
.in1 ({lmq1_ldd_vld}),
|
7341 |
|
|
.in2 ({lmq2_ldd_vld}),
|
7342 |
|
|
.in3 ({lmq3_ldd_vld}),
|
7343 |
|
|
.sel0(dfq_byp_thrd_sel[0]),
|
7344 |
|
|
.sel1(dfq_byp_thrd_sel[1]),
|
7345 |
|
|
.sel2(dfq_byp_thrd_sel[2]),
|
7346 |
|
|
.sel3(dfq_byp_thrd_sel[3]),
|
7347 |
|
|
.dout({lmq_ldd_vld_din})
|
7348 |
|
|
);
|
7349 |
|
|
|
7350 |
|
|
dffe_s #(1) lmq_ldd_vld_ff (
|
7351 |
|
|
.din ({lmq_ldd_vld_din}),
|
7352 |
|
|
.q ({lmq_ldd_vld}),
|
7353 |
|
|
.en (dfq_byp_ff_en),
|
7354 |
|
|
.clk (clk),
|
7355 |
|
|
.se (se), .si (), .so ()
|
7356 |
|
|
);
|
7357 |
|
|
|
7358 |
|
|
//bist
|
7359 |
|
|
wire [1:0] bist_way_enc_e;
|
7360 |
|
|
wire [3:0] bist_way_e;
|
7361 |
|
|
|
7362 |
|
|
|
7363 |
|
|
assign bist_way_enc_e[1:0] = lsu_dc_iob_access_e ?
|
7364 |
|
|
lsu_dcache_iob_way_e[1:0] : mbist_dcache_way[1:0] ;
|
7365 |
|
|
|
7366 |
|
|
assign bist_way_e[0] = ~bist_way_enc_e[1] & ~bist_way_enc_e[0] ;
|
7367 |
|
|
assign bist_way_e[1] = ~bist_way_enc_e[1] & bist_way_enc_e[0] ;
|
7368 |
|
|
assign bist_way_e[2] = bist_way_enc_e[1] & ~bist_way_enc_e[0] ;
|
7369 |
|
|
assign bist_way_e[3] = bist_way_enc_e[1] & bist_way_enc_e[0] ;
|
7370 |
|
|
|
7371 |
|
|
assign lsu_bist_rsel_way_e[3:0] = bist_way_e[3:0];
|
7372 |
|
|
|
7373 |
|
|
wire lmq_l2fill_fp_din;
|
7374 |
|
|
assign lmq_l2fill_fp_din =
|
7375 |
|
|
dfq_byp_thrd_sel[0] & lmq0_l2fill_fpld |
|
7376 |
|
|
dfq_byp_thrd_sel[1] & lmq1_l2fill_fpld |
|
7377 |
|
|
dfq_byp_thrd_sel[2] & lmq2_l2fill_fpld |
|
7378 |
|
|
dfq_byp_thrd_sel[3] & lmq3_l2fill_fpld ;
|
7379 |
|
|
|
7380 |
|
|
dffe_s #(1) lmq_l2fill_fp_ff (
|
7381 |
|
|
.din (lmq_l2fill_fp_din),
|
7382 |
|
|
.q (lsu_l2fill_fpld_e),
|
7383 |
|
|
.en (dfq_byp_ff_en),
|
7384 |
|
|
.clk (clk),
|
7385 |
|
|
.se (se), .si (), .so ()
|
7386 |
|
|
);
|
7387 |
|
|
|
7388 |
|
|
wire lmq_ncache_ld_din;
|
7389 |
|
|
assign lmq_ncache_ld_din =
|
7390 |
|
|
dfq_byp_thrd_sel[0] & lmq0_ncache_ld |
|
7391 |
|
|
dfq_byp_thrd_sel[1] & lmq1_ncache_ld |
|
7392 |
|
|
dfq_byp_thrd_sel[2] & lmq2_ncache_ld |
|
7393 |
|
|
dfq_byp_thrd_sel[3] & lmq3_ncache_ld ;
|
7394 |
|
|
|
7395 |
|
|
dffe_s #(1) lmq_ncache_ld_ff (
|
7396 |
|
|
.din (lmq_ncache_ld_din),
|
7397 |
|
|
.q (lsu_ncache_ld_e),
|
7398 |
|
|
.en (dfq_byp_ff_en),
|
7399 |
|
|
.clk (clk),
|
7400 |
|
|
.se (se), .si (), .so ()
|
7401 |
|
|
);
|
7402 |
|
|
|
7403 |
|
|
//lmq
|
7404 |
|
|
wire [1:0] lmq_ldfill_way_din;
|
7405 |
|
|
|
7406 |
|
|
mux4ds #(2) lmq_ldfill_way_mux (
|
7407 |
|
|
.in0 ({lmq0_pcx_pkt_way[1:0]}),
|
7408 |
|
|
.in1 ({lmq1_pcx_pkt_way[1:0]}),
|
7409 |
|
|
.in2 ({lmq2_pcx_pkt_way[1:0]}),
|
7410 |
|
|
.in3 ({lmq3_pcx_pkt_way[1:0]}),
|
7411 |
|
|
.sel0(dfq_byp_thrd_sel[0]),
|
7412 |
|
|
.sel1(dfq_byp_thrd_sel[1]),
|
7413 |
|
|
.sel2(dfq_byp_thrd_sel[2]),
|
7414 |
|
|
.sel3(dfq_byp_thrd_sel[3]),
|
7415 |
|
|
.dout({lmq_ldfill_way_din[1:0]})
|
7416 |
|
|
);
|
7417 |
|
|
wire [1:0] lmq_ldfill_way;
|
7418 |
|
|
|
7419 |
|
|
dffe_s #(2) lmq_ldfill_way_ff (
|
7420 |
|
|
.din ({lmq_ldfill_way_din[1:0]}),
|
7421 |
|
|
.q ({lmq_ldfill_way[1:0]}),
|
7422 |
|
|
.en (dfq_byp_ff_en),
|
7423 |
|
|
.clk (clk),
|
7424 |
|
|
.se (se), .si (), .so ()
|
7425 |
|
|
);
|
7426 |
|
|
|
7427 |
|
|
wire [1:0] dcache_fill_way_enc_e;
|
7428 |
|
|
|
7429 |
|
|
assign dcache_fill_way_enc_e[1:0] =
|
7430 |
|
|
{2{lsu_dc_iob_access_e}} & lsu_dcache_iob_way_e[1:0] |
|
7431 |
|
|
{2{lsu_bist_e}} & bist_way_enc_e[1:0] |
|
7432 |
|
|
{2{lsu_diagnstc_wr_src_sel_e}} & lsu_diagnstc_wr_way_e[1:0]|
|
7433 |
|
|
{2{lsu_dfq_st_vld}} & lsu_st_way_e[1:0] |
|
7434 |
|
|
{2{lsu_dfq_ld_vld}} & lmq_ldfill_way[1:0];
|
7435 |
|
|
|
7436 |
|
|
assign lsu_dcache_fill_way_e[0] = ~dcache_fill_way_enc_e[1] & ~dcache_fill_way_enc_e[0];
|
7437 |
|
|
assign lsu_dcache_fill_way_e[1] = ~dcache_fill_way_enc_e[1] & dcache_fill_way_enc_e[0];
|
7438 |
|
|
assign lsu_dcache_fill_way_e[2] = dcache_fill_way_enc_e[1] & ~dcache_fill_way_enc_e[0];
|
7439 |
|
|
assign lsu_dcache_fill_way_e[3] = dcache_fill_way_enc_e[1] & dcache_fill_way_enc_e[0];
|
7440 |
|
|
|
7441 |
|
|
//ld_rq_type
|
7442 |
|
|
|
7443 |
|
|
wire [2:0] lmq_ld_rq_type_din;
|
7444 |
|
|
|
7445 |
|
|
mux4ds #(3) lmq_ld_rq_type_mux (
|
7446 |
|
|
.in0 ({lmq0_ld_rq_type[2:0]}),
|
7447 |
|
|
.in1 ({lmq1_ld_rq_type[2:0]}),
|
7448 |
|
|
.in2 ({lmq2_ld_rq_type[2:0]}),
|
7449 |
|
|
.in3 ({lmq3_ld_rq_type[2:0]}),
|
7450 |
|
|
.sel0(dfq_byp_thrd_sel[0]),
|
7451 |
|
|
.sel1(dfq_byp_thrd_sel[1]),
|
7452 |
|
|
.sel2(dfq_byp_thrd_sel[2]),
|
7453 |
|
|
.sel3(dfq_byp_thrd_sel[3]),
|
7454 |
|
|
.dout({lmq_ld_rq_type_din[2:0]})
|
7455 |
|
|
);
|
7456 |
|
|
|
7457 |
|
|
dffe_s #(3) lmq_ld_rq_type_e_ff (
|
7458 |
|
|
.din ({lmq_ld_rq_type_din[2:0]}),
|
7459 |
|
|
.q ({lmq_ld_rq_type_e[2:0]}),
|
7460 |
|
|
.en (dfq_byp_ff_en),
|
7461 |
|
|
.clk (clk),
|
7462 |
|
|
.se (se), .si (), .so ()
|
7463 |
|
|
);
|
7464 |
|
|
|
7465 |
|
|
//================================================================
|
7466 |
|
|
wire other_flush_pipe_w ;
|
7467 |
|
|
|
7468 |
|
|
assign other_flush_pipe_w = tlu_early_flush_pipe2_w | (lsu_ttype_vld_m2 & lsu_inst_vld_w);
|
7469 |
|
|
assign dctl_flush_pipe_w = other_flush_pipe_w | ifu_lsu_flush_w ;
|
7470 |
|
|
// Staged ifu_tlu_flush_m should be used !!
|
7471 |
|
|
assign dctl_early_flush_w = (lsu_local_early_flush_g | tlu_early_flush_pipe2_w | ifu_lsu_flush_w) ;
|
7472 |
|
|
|
7473 |
|
|
//================================================================
|
7474 |
|
|
// dcfill size
|
7475 |
|
|
wire dcfill_size_mx_sel_e;
|
7476 |
|
|
//bug6216/eco6624
|
7477 |
|
|
assign dcfill_size_mx_sel_e = lsu_dc_iob_access_e | lsu_diagnstc_wr_src_sel_e;
|
7478 |
|
|
|
7479 |
|
|
mux2ds #(2) dcache_wr_size_e_mux (
|
7480 |
|
|
.in0(2'b11),
|
7481 |
|
|
.in1(lsu_st_dcfill_size_e[1:0]),
|
7482 |
|
|
.sel0(dcfill_size_mx_sel_e),
|
7483 |
|
|
.sel1(~dcfill_size_mx_sel_e),
|
7484 |
|
|
.dout(dcache_wr_size_e[1:0])
|
7485 |
|
|
);
|
7486 |
|
|
|
7487 |
|
|
|
7488 |
|
|
//assign lsu_dcfill_data_mx_sel_e = (dcache_iob_wr_e | dcache_iob_rd_e | lsu_bist_wvld_e);
|
7489 |
|
|
wire dcfill_data_mx_sel_e_l;
|
7490 |
|
|
|
7491 |
|
|
bw_u1_nor3_8x UZsize_dcfill_data_mx_sel_e_l (.a (dcache_iob_wr_e),
|
7492 |
|
|
.b (dcache_iob_rd_e),
|
7493 |
|
|
.c (lsu_bist_wvld_e),
|
7494 |
|
|
.z (dcfill_data_mx_sel_e_l));
|
7495 |
|
|
|
7496 |
|
|
bw_u1_inv_30x UZsize_dcfill_data_mx_sel_e ( .a(dcfill_data_mx_sel_e_l), .z (lsu_dcfill_data_mx_sel_e));
|
7497 |
|
|
|
7498 |
|
|
//================================================================
|
7499 |
|
|
wire [3:0] dfq_thread_e;
|
7500 |
|
|
assign dfq_thread_e[0] = ~lsu_dfill_tid_e[1] & ~lsu_dfill_tid_e[0];
|
7501 |
|
|
assign dfq_thread_e[1] = ~lsu_dfill_tid_e[1] & lsu_dfill_tid_e[0];
|
7502 |
|
|
assign dfq_thread_e[2] = lsu_dfill_tid_e[1] & ~lsu_dfill_tid_e[0];
|
7503 |
|
|
assign dfq_thread_e[3] = lsu_dfill_tid_e[1] & lsu_dfill_tid_e[0];
|
7504 |
|
|
|
7505 |
|
|
wire [3:0] dfq_byp_sel_e;
|
7506 |
|
|
assign dfq_byp_sel_e[0] = dfq_thread_e[0] & dcfill_active_e & ~lsu_cpx_pkt_prefetch2;
|
7507 |
|
|
assign dfq_byp_sel_e[1] = dfq_thread_e[1] & dcfill_active_e & ~lsu_cpx_pkt_prefetch2;
|
7508 |
|
|
assign dfq_byp_sel_e[2] = dfq_thread_e[2] & dcfill_active_e & ~lsu_cpx_pkt_prefetch2;
|
7509 |
|
|
assign dfq_byp_sel_e[3] = dfq_thread_e[3] & dcfill_active_e & ~lsu_cpx_pkt_prefetch2;
|
7510 |
|
|
|
7511 |
|
|
wire [3:0] lmq_byp_misc_sel_e ;
|
7512 |
|
|
|
7513 |
|
|
assign lmq_byp_misc_sel_e[0] = ld_thrd_byp_sel_e[0] | // select for ldxa/raw.
|
7514 |
|
|
dfq_byp_sel_e[0] ; // select for dfq.
|
7515 |
|
|
assign lmq_byp_misc_sel_e[1] = ld_thrd_byp_sel_e[1] | // select for ldxa/raw.
|
7516 |
|
|
dfq_byp_sel_e[1] ; // select for dfq.
|
7517 |
|
|
assign lmq_byp_misc_sel_e[2] = ld_thrd_byp_sel_e[2] | // select for ldxa/raw.
|
7518 |
|
|
dfq_byp_sel_e[2] ; // select for dfq.
|
7519 |
|
|
assign lmq_byp_misc_sel_e[3] = ld_thrd_byp_sel_e[3] |
|
7520 |
|
|
dfq_byp_sel_e[3] ;
|
7521 |
|
|
|
7522 |
|
|
wire [2:0] byp_misc_addr_e;
|
7523 |
|
|
assign byp_misc_addr_e[2:0] = (lmq_byp_misc_sel_e[0] ? lmq0_pcx_pkt_addr[2:0] : 3'b0) |
|
7524 |
|
|
(lmq_byp_misc_sel_e[1] ? lmq1_pcx_pkt_addr[2:0] : 3'b0) |
|
7525 |
|
|
(lmq_byp_misc_sel_e[2] ? lmq2_pcx_pkt_addr[2:0] : 3'b0) |
|
7526 |
|
|
(lmq_byp_misc_sel_e[3] ? lmq3_pcx_pkt_addr[2:0] : 3'b0) ;
|
7527 |
|
|
|
7528 |
|
|
wire [1:0] byp_misc_sz_e;
|
7529 |
|
|
assign byp_misc_sz_e[1:0] = (lmq_byp_misc_sel_e[0] ? lmq0_byp_misc_sz[1:0] : 2'b0) |
|
7530 |
|
|
(lmq_byp_misc_sel_e[1] ? lmq1_byp_misc_sz[1:0] : 2'b0) |
|
7531 |
|
|
(lmq_byp_misc_sel_e[2] ? lmq2_byp_misc_sz[1:0] : 2'b0) |
|
7532 |
|
|
(lmq_byp_misc_sel_e[3] ? lmq3_byp_misc_sz[1:0] : 2'b0) ;
|
7533 |
|
|
|
7534 |
|
|
|
7535 |
|
|
dff_s #(5) lmq_byp_misc_stgm (
|
7536 |
|
|
.din ({byp_misc_addr_e[2:0], byp_misc_sz_e[1:0]}),
|
7537 |
|
|
.q ({lsu_byp_misc_addr_m[2:0], lsu_byp_misc_sz_m[1:0]}),
|
7538 |
|
|
.clk (clk),
|
7539 |
|
|
.se (se), .si (), .so ()
|
7540 |
|
|
);
|
7541 |
|
|
|
7542 |
|
|
endmodule
|
7543 |
|
|
|
7544 |
|
|
|