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[/] [sparc64soc/] [trunk/] [T1-CPU/] [lsu/] [lsu_excpctl.v] - Blame information for rev 2

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
2
// 
3
// OpenSPARC T1 Processor File: lsu_excpctl.v
4
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6
// 
7
// The above named program is free software; you can redistribute it and/or
8
// modify it under the terms of the GNU General Public
9
// License version 2 as published by the Free Software Foundation.
10
// 
11
// The above named program is distributed in the hope that it will be 
12
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
// General Public License for more details.
15
// 
16
// You should have received a copy of the GNU General Public
17
// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19
// 
20
// ========== Copyright Header End ============================================
21
/////////////////////////////////////////////////////////////////
22
 
23
`include "sys.h"
24
`include "lsu.h"
25
 
26
module lsu_excpctl ( /*AUTOARG*/
27
   // Outputs
28
   so, lsu_exu_st_dtlb_perr_g, lsu_ffu_st_dtlb_perr_g,
29
   lsu_defr_trp_taken_g, lsu_tlu_defr_trp_taken_g,
30
   lsu_mmu_defr_trp_taken_g, lsu_st_dtlb_perr_g,
31
   lsu_dmmu_sfsr_trp_wr, lsu_dsfsr_din_g, lsu_tlb_perr_ld_rq_kill_w,
32
   lsu_spu_early_flush_g, lsu_local_early_flush_g,
33
   lsu_tlu_early_flush_w, lsu_tlu_early_flush2_w, lsu_ttype_vld_m2,
34
   lsu_ttype_vld_m2_bf1, lsu_ifu_flush_pipe_w, lsu_exu_flush_pipe_w,
35
   lsu_mmu_flush_pipe_w, lsu_ffu_flush_pipe_w, lsu_tlu_wtchpt_trp_g,
36
   lsu_tlu_dmmu_miss_g, lsu_tlu_misalign_addr_ldst_atm_m,
37
   lsu_tlu_daccess_excptn_g, lsu_tlu_daccess_prot_g,
38
   lsu_tlu_priv_action_g, lsu_ifu_tlb_data_su, lsu_ifu_tlb_data_ue,
39
   lsu_ifu_tlb_tag_ue, lsu_tlu_ttype_m2, lsu_tlu_ttype_vld_m2,
40
   stb_cam_sqsh_msk, stb_cam_hit_bf, stb_cam_hit_bf1,
41
   tte_data_perror_unc, asi_tte_data_perror, asi_tte_tag_perror,
42
   // Inputs
43
   rclk, si, se, grst_l, arst_l, tlb_rd_tte_data_ebit,
44
   tlb_rd_tte_data_pbit, tlb_rd_tte_data_nfobit,
45
   tlb_rd_tte_data_wbit, tlb_cam_hit, tlb_pgnum_b39,
46
   lsu_ldst_va_b39_m, lsu_sun4r_va_m_l, lsu_sun4r_pgsz_b2t0_e,
47
   lsu_sun4v_pgsz_b2t0_e, tlu_early_flush_pipe_w, ifu_lsu_flush_w,
48
   ifu_lsu_nceen, lsu_tlb_asi_data_perr_g, lsu_tlb_asi_tag_perr_g,
49
   stb_state_vld0, stb_state_vld1, stb_state_vld2, stb_state_vld3,
50
   ifu_tlu_thrid_e, tlu_lsu_priv_trap_m, tlu_lsu_pstate_priv,
51
   st_inst_vld_e, ld_inst_vld_e, ifu_lsu_alt_space_e, lsu_ldst_va_m,
52
   hpv_priv_m, hpstate_en_m, stb_cam_hit, dtlb_bypass_m,
53
   lsu_alt_space_m, atomic_m, ldst_dbl_m, fp_ldst_m, lda_internal_m,
54
   sta_internal_m, cam_real_m, data_rd_vld_g, tag_rd_vld_g,
55
   ldst_sz_m, asi_internal_m, rd_only_ltlb_asi_e, wr_only_ltlb_asi_e,
56
   dfill_tlb_asi_e, ifill_tlb_asi_e, nofault_asi_m, as_if_user_asi_m,
57
   atomic_asi_m, phy_use_ec_asi_m, phy_byp_ec_asi_m, quad_asi_m,
58
   binit_quad_asi_m, blk_asi_m, recognized_asi_m, strm_asi_m,
59
   mmu_rd_only_asi_m, rd_only_asi_m, wr_only_asi_m, unimp_asi_m,
60
   lsu_nonalt_nucl_access_m, va_wtchpt_cmp_en_m,
61
   lsu_va_match_b47_b32_m, lsu_va_match_b31_b3_m,
62
   va_wtchpt_msk_match_m, ifu_tlu_inst_vld_m,
63
   exu_tlu_misalign_addr_jmpl_rtn_m, exu_tlu_va_oor_m,
64
   tlu_dsfsr_flt_vld, tlu_lsu_pstate_cle, tlu_lsu_pstate_am,
65
   lsu_excpctl_asi_state_m, lsu_tlu_nonalt_ldst_m,
66
   lsu_squash_va_oor_m, lsu_tlu_xslating_ldst_m, lsu_tlu_ctxt_sel_m,
67
   lsu_tlu_write_op_m, lsu_memref_m, lsu_flsh_inst_m,
68
   tte_data_parity_error, tte_tag_parity_error
69
   );
70
 
71
 
72
   input rclk;
73
   input si;
74
   input se;
75
   input grst_l;
76
   input arst_l;
77
   output so;
78
 
79
   //=================================================================
80
   // input from tlb
81
//   input [`STLB_DATA_NFO:`STLB_DATA_W] tlb_rd_tte_data ; // tte data from tlb
82
   input  tlb_rd_tte_data_ebit;
83
   input  tlb_rd_tte_data_pbit;
84
   input  tlb_rd_tte_data_nfobit;
85
   input  tlb_rd_tte_data_wbit;
86
 
87
 
88
   input                               tlb_cam_hit;
89
   input                               tlb_pgnum_b39;
90
//   input                               tlb_rd_tte_data_locked ;    // lock bit from tte
91
   //=================================================================
92
 
93
   input        lsu_ldst_va_b39_m ;
94
   input        lsu_sun4r_va_m_l ;
95
   input [2:0]   lsu_sun4r_pgsz_b2t0_e ;
96
   input [2:0]   lsu_sun4v_pgsz_b2t0_e ;
97
 
98
   input         tlu_early_flush_pipe_w;
99
   input         ifu_lsu_flush_w;
100
   input [3:0]   ifu_lsu_nceen ;             // uncorrectible error enable 
101
 
102
   input        lsu_tlb_asi_data_perr_g ;
103
   input        lsu_tlb_asi_tag_perr_g ;
104
 
105
   input [7:0]  stb_state_vld0 ;  // valid bits - stb0
106
   input [7:0]   stb_state_vld1 ;  // valid bits - stb1
107
   input [7:0]  stb_state_vld2 ;  // valid bits - stb2
108
   input [7:0]  stb_state_vld3 ;  // valid bits - stb3
109
 
110
   input [1:0]  ifu_tlu_thrid_e ; // thread-id.
111
 
112
   input        tlu_lsu_priv_trap_m ;   // daccess-excp in tlu
113
 
114
   output       lsu_exu_st_dtlb_perr_g ;
115
   output       lsu_ffu_st_dtlb_perr_g ;
116
 
117
   output       lsu_defr_trp_taken_g ;
118
   output       lsu_tlu_defr_trp_taken_g ;
119
   output       lsu_mmu_defr_trp_taken_g ;
120
 
121
   output [3:0]  lsu_st_dtlb_perr_g ;
122
 
123
   output [3:0]  lsu_dmmu_sfsr_trp_wr;      // sfsr wr based on trap.
124
   output [23:0] lsu_dsfsr_din_g;
125
 
126
 
127
   output lsu_tlb_perr_ld_rq_kill_w ;
128
   output lsu_spu_early_flush_g;
129
   output lsu_local_early_flush_g;   //to lsu
130
 
131
//   output lsu_dctl_early_flush_w;
132
   output lsu_tlu_early_flush_w;
133
   output lsu_tlu_early_flush2_w;
134
 
135
   output lsu_ttype_vld_m2;
136
   output lsu_ttype_vld_m2_bf1;
137
 
138
 
139
//   output     lsu_stbctl_flush_pipe_w ;
140
//   output     lsu_stbrwctl_flush_pipe_w ;
141
   //output lsu_flush_pipe_w;
142
   output lsu_ifu_flush_pipe_w;
143
   output lsu_exu_flush_pipe_w;
144
   output lsu_mmu_flush_pipe_w;
145
   output lsu_ffu_flush_pipe_w;
146
 
147
   output lsu_tlu_wtchpt_trp_g ;        // watchpt trap has occurred.
148
   output lsu_tlu_dmmu_miss_g;
149
   output lsu_tlu_misalign_addr_ldst_atm_m ; // mem_addr unaligned
150
//   output lsu_tlu_priv_violtn_g;
151
   wire   lsu_tlu_priv_violtn_g;
152
   output lsu_tlu_daccess_excptn_g;
153
   output lsu_tlu_daccess_prot_g;
154
   output lsu_tlu_priv_action_g;
155
//   output lsu_tlu_tte_ebit_g;
156
//   output lsu_tlu_spec_access_epage_g;
157
//   output lsu_tlu_uncache_atomic_g;
158
//   output lsu_tlu_illegal_asi_action_g;
159
//   output lsu_tlu_flt_ld_nfo_pg_g;
160
 
161
   //output lsu_tlu_asi_rd_unc;
162
 
163
   output lsu_ifu_tlb_data_su ;   // specific to st ue
164
   output lsu_ifu_tlb_data_ue ;   // dtlb data asi rd parity error ; now ld ue
165
   output lsu_ifu_tlb_tag_ue ;    // dtlb tag asi rd parity error
166
 
167
output [8:0]            lsu_tlu_ttype_m2;
168
output                  lsu_tlu_ttype_vld_m2;
169
 
170
   output  [7:0]   stb_cam_sqsh_msk ;  // squash spurious hits
171
 
172
   output       stb_cam_hit_bf;           // buffered stb_cam_hit for qctl1.
173
   output       stb_cam_hit_bf1;                // buffered stb_cam_hit for stb_rwctl, dctl.
174
 
175
   input [3:0]          tlu_lsu_pstate_priv ;
176
//   input [3:0]          tlu_lsu_hpv_priv;
177
//   input [3:0]          tlu_lsu_hpstate_en;
178
 
179
 
180
   input                st_inst_vld_e;
181
   input                ld_inst_vld_e;
182
   input                ifu_lsu_alt_space_e;        // alternate space ld/st
183
 
184
   //interface between lsu_dctldp
185
   input [7:0]          lsu_ldst_va_m;
186
 
187
   //interface between lsu_excpctl and lsu_dctl
188
 
189
   output               tte_data_perror_unc;
190
   //output               tte_data_perror_corr;
191
   output               asi_tte_data_perror ;
192
   output               asi_tte_tag_perror ;
193
 
194
 
195
   input hpv_priv_m;
196
   input hpstate_en_m;
197
 
198
   input                stb_cam_hit ;
199
 
200
   input                dtlb_bypass_m;
201
 
202
   input                lsu_alt_space_m;
203
   input                atomic_m;
204
//   input                atomic_g;
205
   input                ldst_dbl_m;
206
   input                fp_ldst_m;
207
//   input                lsu_inst_vld_w;
208
   input                lda_internal_m;
209
   input                sta_internal_m;
210
   input                cam_real_m;
211
//   input                va_wtchpt_match;
212
 
213
   input                data_rd_vld_g;
214
   input                tag_rd_vld_g;
215
   input [1:0]          ldst_sz_m;
216
   input                asi_internal_m;
217
 
218
//   input                dfill_thread0;
219
//   input                dfill_thread1;
220
//   input                dfill_thread2;
221
//   input                dfill_thread3;
222
 
223
   wire                ld_inst_vld_unflushed;
224
   wire                st_inst_vld_unflushed;
225
//   input                flsh_inst_g;
226
//   input                unc_err_trap_g;
227
 
228
   //asi decode
229
   input                rd_only_ltlb_asi_e;
230
   input                wr_only_ltlb_asi_e;
231
   input                dfill_tlb_asi_e;
232
   input                ifill_tlb_asi_e;
233
 
234
   input                nofault_asi_m;
235
   input                as_if_user_asi_m;
236
 
237
   input                atomic_asi_m;
238
   input                phy_use_ec_asi_m;
239
   input                phy_byp_ec_asi_m;
240
//   input                tlb_byp_asi_m;
241
   input                quad_asi_m;
242
   input                binit_quad_asi_m;
243
   input                blk_asi_m;
244
//   input                blk_cmt_asi_m;
245
   input                recognized_asi_m;
246
   input                strm_asi_m;
247
   input                mmu_rd_only_asi_m;
248
   input                rd_only_asi_m;
249
   input                wr_only_asi_m;
250
   input                unimp_asi_m;
251
   input                lsu_nonalt_nucl_access_m ;
252
 
253
   input    va_wtchpt_cmp_en_m;    //from dctl
254
   input    lsu_va_match_b47_b32_m;        //from qdp1
255
   input    lsu_va_match_b31_b3_m;         //from qdp1
256
 
257
   input    va_wtchpt_msk_match_m; //from dctldp
258
 
259
   input                ifu_tlu_inst_vld_m ;
260
 
261
input           exu_tlu_misalign_addr_jmpl_rtn_m;// misaligned addr - jmpl or return addr
262
input           exu_tlu_va_oor_m;               // ??? - to be used in sfsr
263
input [3:0]     tlu_dsfsr_flt_vld;
264
input [3:0]      tlu_lsu_pstate_cle ;       // current little endian
265
input [3:0]      tlu_lsu_pstate_am ;        // address mask
266
input  [7:0]    lsu_excpctl_asi_state_m ;   // ASI State + imm asi
267
input           lsu_tlu_nonalt_ldst_m ; // non-alternate load or store // FORCE
268
input           lsu_squash_va_oor_m ;   // squash va_oor for mem-op. // FORCE
269
input           lsu_tlu_xslating_ldst_m ;// xslating ldst,atomic etc // FORCE
270
input   [2:0]   lsu_tlu_ctxt_sel_m;           // context selected:0-p,1-s,2-n // FORCE
271
input           lsu_tlu_write_op_m; // FORCE
272
input           lsu_memref_m ;
273
input           lsu_flsh_inst_m ;
274
 
275
 
276
input    tte_data_parity_error ;
277
input    tte_tag_parity_error ;
278
 
279
wire    other_flush_pipe_w ;
280
wire    defr_trp_taken ;
281
wire    defr_trp_taken_m, defr_trp_taken_byp, defr_trp_taken_m_din ;
282
wire    tlb_tte_vld_m, tlb_tte_vld_g ;
283
wire    priv_pg_usr_mode_m, priv_pg_usr_mode_g, priv_pg_usr_mode;
284
wire    nfo_pg_nonnfo_asi_m, nfo_pg_nonnfo_asi_g, nfo_pg_nonnfo_asi;
285
wire    spec_access_epage_m, spec_access_epage_g, spec_access_epage ;
286
wire    nonwr_pg_st_access;
287
 
288
//=========================================================================================
289
// MISCELLANEOUS
290
//=========================================================================================
291
 
292
   wire       clk;
293
   assign     clk = rclk;
294
   wire       reset;
295
 
296
   wire       dbb_reset_l;
297
 
298
    dffrl_async rstff(.din (grst_l),
299
                        .q   (dbb_reset_l),
300
                        .clk (clk), .se(se), .si(), .so(),
301
                        .rst_l (arst_l));
302
 
303
   assign reset = ~dbb_reset_l ;
304
 
305
bw_u1_buf_30x UZsize_stb_cam_hit_bf1  (.a(stb_cam_hit),   .z(stb_cam_hit_bf1));  //to dctl, stb_rwctl
306
bw_u1_buf_30x UZsize_stb_cam_hit_bf   (.a(stb_cam_hit),   .z(stb_cam_hit_bf ));  //to qctl1
307
 
308
wire                ld_inst_vld_m;
309
wire                st_inst_vld_m;
310
 
311
dff_s #(2) inst_vld_stgm (
312
   .din ({ld_inst_vld_e, st_inst_vld_e}),
313
   .q   ({ld_inst_vld_m, st_inst_vld_m}),
314
   .clk    (clk),
315
   .se     (se),       .si (),          .so ()
316
);
317
 
318
dff_s #(2) inst_vld_stgg (
319
   .din ({ld_inst_vld_m, st_inst_vld_m}),
320
   .q   ({ld_inst_vld_unflushed, st_inst_vld_unflushed}),
321
   .clk    (clk),
322
   .se     (se),       .si (),          .so ()
323
);
324
 
325
wire    tlu_priv_trap_g ;
326
dff_s #(1) tprivtrp_g (
327
   .din (tlu_lsu_priv_trap_m),
328
   .q   (tlu_priv_trap_g),
329
   .clk    (clk),
330
   .se     (se),       .si (),          .so ()
331
);
332
 
333
 
334
//=========================================================================================
335
//  Thread Staging
336
//=========================================================================================
337
 
338
wire [1:0] thrid_m, thrid_g ;
339
dff_s #(2)  tid_stgm (
340
        .din    (ifu_tlu_thrid_e[1:0]),
341
        .q      (thrid_m[1:0]),
342
        .clk    (clk),
343
        .se     (se),       .si (),          .so ()
344
        );
345
 
346
wire    thread0_m, thread1_m, thread2_m, thread3_m;
347
 
348
assign  thread0_m = ~thrid_m[1] & ~thrid_m[0] ;
349
assign  thread1_m = ~thrid_m[1] &  thrid_m[0] ;
350
assign  thread2_m =  thrid_m[1] & ~thrid_m[0] ;
351
assign  thread3_m =  thrid_m[1] &  thrid_m[0] ;
352
 
353
wire thread0_g, thread1_g, thread2_g, thread3_g ;
354
dff_s #(4)  tid_stgg (
355
        .din    ({thread0_m, thread1_m, thread2_m, thread3_m}),
356
        .q      ({thread0_g, thread1_g, thread2_g, thread3_g}),
357
        .clk    (clk),
358
        .se     (se),       .si (),          .so ()
359
        );
360
 
361
//=========================================================================================
362
//  INST_VLD_W GENERATION
363
//=========================================================================================
364
 
365
 
366
assign  thrid_g[0] = thread1_g | thread3_g ;
367
assign  thrid_g[1] = thread2_g | thread3_g ;
368
 
369
wire    flush_w_inst_vld_m ;
370
wire    lsu_inst_vld_w ;
371
wire    lsu_flush_pipe_w;
372
assign  flush_w_inst_vld_m =
373
        ifu_tlu_inst_vld_m &
374
        ~(lsu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
375
 
376
dff_s  stgw_ivld (
377
        .din    (flush_w_inst_vld_m),
378
        .q      (lsu_inst_vld_w),
379
        .clk    (clk),
380
        .se     (se),       .si (),          .so ()
381
        );
382
 
383
//========================================================================
384
//      Miscellaneous
385
//========================================================================
386
 
387
 
388
// Moved to excpctl from stb_rwctl as excpctl is closer to stb-cam.
389
mux4ds  #(8) stbvld_mx (
390
  .in0  (~stb_state_vld0[7:0]),
391
  .in1  (~stb_state_vld1[7:0]),
392
  .in2  (~stb_state_vld2[7:0]),
393
  .in3  (~stb_state_vld3[7:0]),
394
  .sel0 (thread0_g),
395
  .sel1 (thread1_g),
396
  .sel2 (thread2_g),
397
  .sel3 (thread3_g),
398
  .dout (stb_cam_sqsh_msk[7:0])
399
);
400
 
401
//========================================================================
402
//  Exception Handling Begin
403
//========================================================================
404
 
405
//va watch point
406
   wire va_match_g;
407
   wire va_wtchpt_msk_match_g;
408
 
409
 
410
wire    va_wtchpt_en_m ;
411
 
412
assign  va_wtchpt_en_m =
413
va_wtchpt_cmp_en_m &
414
(((~asi_internal_m & recognized_asi_m) & lsu_alt_space_m) | ~lsu_alt_space_m) // Bug5226
415
& (ld_inst_vld_m | st_inst_vld_m) & //bug 3681
416
 ~(hpv_priv_m & hpstate_en_m)  // ECO 4178
417
& ~cam_real_m ;                // ECO 5470 (TO_2_0)
418
 
419
//bug6480   
420
   wire lsu_va_match_m;
421
   wire pstate_am_m ;
422
 
423
assign lsu_va_match_m = ((lsu_va_match_b47_b32_m & lsu_va_match_b31_b3_m) & ~pstate_am_m) |
424
                          (lsu_va_match_b31_b3_m & pstate_am_m);
425
 
426
dff_s #(3)  stgwtch_g (
427
        .din    ({va_wtchpt_en_m,
428
                  lsu_va_match_m,
429
                  va_wtchpt_msk_match_m}),
430
        .q      ({va_wtchpt_en_g,
431
                  va_match_g,
432
                  va_wtchpt_msk_match_g}),
433
        .clk    (clk),
434
        .se     (se),       .si (),          .so ()
435
        );
436
 
437
 
438
// These signals will eventually generate exceptions.
439
   wire va_wtchpt_match;
440
 
441
assign  va_wtchpt_match =
442
        va_match_g &  va_wtchpt_msk_match_g & lsu_inst_vld_w & va_wtchpt_en_g;
443
 
444
assign  lsu_tlu_wtchpt_trp_g = va_wtchpt_match ;
445
 
446
 
447
// tlb related exceptions/errors
448
wire  tlb_daccess_excptn_e, tlb_daccess_excptn_m ;
449
wire  tlb_daccess_excptn_e_d1;
450
wire    tlb_illgl_pgsz_m ;
451
 
452
assign  tlb_daccess_excptn_e  =
453
  ((rd_only_ltlb_asi_e &  st_inst_vld_e)  |
454
   (wr_only_ltlb_asi_e &  ld_inst_vld_e)) & ifu_lsu_alt_space_e   ;
455
 
456
dff_s  #(1) tlbex_stgm (
457
        .din    ({tlb_daccess_excptn_e}),
458
        .q      ({tlb_daccess_excptn_e_d1}),
459
        .clk    (clk),
460
        .se     (se),       .si (),          .so ()
461
        );
462
 
463
assign tlb_daccess_excptn_m = tlb_daccess_excptn_e_d1 | tlb_illgl_pgsz_m;
464
 
465
wire pstate_priv_m;
466
//wire pstate_priv;
467
 
468
mux4ds  #(1) pstate_priv_m_mux (
469
        .in0    (tlu_lsu_pstate_priv[0]),
470
        .in1    (tlu_lsu_pstate_priv[1]),
471
        .in2    (tlu_lsu_pstate_priv[2]),
472
        .in3    (tlu_lsu_pstate_priv[3]),
473
        .sel0   (thread0_m),
474
        .sel1   (thread1_m),
475
        .sel2   (thread2_m),
476
        .sel3   (thread3_m),
477
        .dout   (pstate_priv_m)
478
);
479
 
480
//dff #(1)  priv_stgg (
481
//        .din    (pstate_priv_m),
482
//        .q      (pstate_priv),
483
//        .clk    (clk),
484
//        .se     (se),       .si (),          .so ()
485
//        );
486
 
487
// privilege violation - priv page accessed in user mode
488
//timing 
489
//assign  priv_pg_usr_mode =  // data access exception; TT=h30
490
//  (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~(pstate_priv | hpv_priv) & tlb_rd_tte_data_pbit ;
491
 
492
//SC2   wire hpv_priv_m;
493
 
494
   assign priv_pg_usr_mode_m = (ld_inst_vld_m | st_inst_vld_m) & ~(pstate_priv_m | hpv_priv_m);
495
 
496
dff_s #(1) priv_pg_usr_mode_stgg  (
497
        .din    (priv_pg_usr_mode_m),
498
        .q      (priv_pg_usr_mode_g),
499
        .clk    (clk),
500
        .se     (se),       .si (),          .so ()
501
        );
502
 
503
   assign priv_pg_usr_mode = priv_pg_usr_mode_g & tlb_rd_tte_data_pbit ;
504
 
505
// protection violation - store to a page that does not have write permission
506
//timing
507
//assign  nonwr_pg_st_access =  // data access protection; TT=h33
508
//  st_inst_vld_unflushed   & 
509
//  ~tlb_rd_tte_data_wbit & ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
510
//   //lsu_dtlb_bypass_g) ; // W=1 in bypass mode - In bypass mode this trap will never happen !!!
511
 
512
   assign nonwr_pg_st_access = ~tlb_rd_tte_data_wbit & st_inst_vld_unflushed & tlb_tte_vld_g;
513
 
514
wire  daccess_prot ;
515
assign  daccess_prot = nonwr_pg_st_access  ;
516
    //((~lsu_dtlb_bypass_g & tlb_cam_hit_g) | (tlb_byp_asi_g & lsu_alt_space_g)) ;
517
 
518
// access to a page marked with the nfo with an asi other than nfo asi.
519
//timing
520
//assign  nfo_pg_nonnfo_asi  =  // data access exception; TT=h30
521
//  (ld_inst_vld_unflushed | st_inst_vld_unflushed) &   // any access
522
//  ((~nofault_asi_g & lsu_alt_space_g) | ~lsu_alt_space_g) // in alternate space or not
523
//  & tlb_rd_tte_data_nfobit ;
524
 
525
assign nfo_pg_nonnfo_asi_m = (ld_inst_vld_m | st_inst_vld_m) &
526
                             ((~nofault_asi_m & lsu_alt_space_m) | ~lsu_alt_space_m) ;
527
 
528
dff_s #(1) nfo_pg_nonnfo_asi_stgg   (
529
        .din    (nfo_pg_nonnfo_asi_m),
530
        .q      (nfo_pg_nonnfo_asi_g),
531
        .clk    (clk),
532
        .se     (se),       .si (),          .so ()
533
        );
534
assign    nfo_pg_nonnfo_asi = nfo_pg_nonnfo_asi_g & tlb_rd_tte_data_nfobit ;
535
 
536
// as_if_usr asi accesses priv page.
537
//timing
538
//assign  as_if_usr_priv_pg  =  // data access exception; TT=h30
539
//  (ld_inst_vld_unflushed | st_inst_vld_unflushed) & as_if_user_asi_g & lsu_alt_space_g & 
540
//      tlb_rd_tte_data_pbit ;
541
 
542
   wire   as_if_usr_priv_pg_m, as_if_usr_priv_pg_g, as_if_usr_priv_pg;
543
   assign as_if_usr_priv_pg_m = (ld_inst_vld_m | st_inst_vld_m) & as_if_user_asi_m & lsu_alt_space_m;
544
 
545
dff_s #(1) as_if_usr_priv_pg_stgg   (
546
        .din    (as_if_usr_priv_pg_m),
547
        .q      (as_if_usr_priv_pg_g),
548
        .clk    (clk),
549
        .se     (se),       .si (),          .so ()
550
        );
551
   assign  as_if_usr_priv_pg =  as_if_usr_priv_pg_g & tlb_rd_tte_data_pbit ;
552
 
553
// non-cacheable address - iospace PA[39] = 1 
554
// atomic access to non-cacheable space.
555
   wire    atm_access_w_nc, atomic_g;
556
 
557
dff_s #(1) atm_stgg (
558
        .din    (atomic_m),
559
        .q      (atomic_g),
560
        .clk    (clk),
561
        .se     (se),       .si (),          .so ()
562
        );
563
 
564
 
565
assign  atm_access_w_nc = atomic_g & tlb_pgnum_b39 ; // io space 
566
 
567
// atomic inst with unsupported asi.
568
//timing
569
//assign  atm_access_unsup_asi = atomic_g & ~atomic_asi_g & lsu_alt_space_g ;
570
   wire atm_access_unsup_asi_m, atm_access_unsup_asi;
571
 
572
assign  atm_access_unsup_asi_m = atomic_m & ~atomic_asi_m & lsu_alt_space_m;
573
 
574
dff_s #(1) atm_access_unsup_asi_stgg   (
575
        .din    (atm_access_unsup_asi_m),
576
        .q      (atm_access_unsup_asi),
577
        .clk    (clk),
578
        .se     (se),       .si (),          .so ()
579
        );
580
 
581
 
582
//timing
583
//assign  tlb_tte_vld_g = ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
584
 
585
wire    dmmu_va_oor_m ;
586
assign  tlb_tte_vld_m = ~dtlb_bypass_m & tlb_cam_hit &
587
                        ~((unimp_asi_m | asi_internal_m | ~recognized_asi_m) &
588
                                lsu_alt_space_m) & // Bug 3541,5186
589
                        ~dmmu_va_oor_m ; // Bug 5070
590
 
591
dff_s #(1) tlb_tte_vld_stgg   (
592
        .din    (tlb_tte_vld_m),
593
        .q      (tlb_tte_vld_g),
594
        .clk    (clk),
595
        .se     (se),       .si (),          .so ()
596
        );
597
 
598
wire  pg_with_ebit_m, pg_with_ebit_g, pg_with_ebit  ;
599
//timing   
600
//assign        pg_with_ebit = 
601
//      (tlb_rd_tte_data_ebit & tlb_tte_vld_g)  | // tte
602
//        (lsu_dtlb_bypass_g & ~(phy_use_ec_asi_g & lsu_alt_space_g)) | // regular bypass 
603
//        (tlb_byp_asi_g & ~phy_use_ec_asi_g & lsu_alt_space_g) ; // phy_byp
604
 
605
assign  pg_with_ebit_m =
606
        (dtlb_bypass_m & ~(phy_use_ec_asi_m & lsu_alt_space_m) &
607
        (lsu_ldst_va_b39_m & ~pstate_am_m)) |
608
        // regular bypass // Bug 4296,5050 related.
609
        (dtlb_bypass_m & (phy_byp_ec_asi_m & lsu_alt_space_m)) ; // phy_byp
610
 
611
dff_s #(1) pg_with_ebit_stgg   (
612
        .din    (pg_with_ebit_m),
613
        .q      (pg_with_ebit_g),
614
        .clk    (clk),
615
        .se     (se),       .si (),          .so ()
616
        );
617
assign  pg_with_ebit = (tlb_rd_tte_data_ebit & tlb_tte_vld_g)  | // tte  
618
                              pg_with_ebit_g;
619
 
620
//timing
621
//assign  spec_access_epage = 
622
//  ((ld_inst_vld_unflushed & nofault_asi_g & lsu_alt_space_g) |  // spec load
623
//  flsh_inst_g) & // flush inst
624
//  pg_with_ebit ; // page with side effects
625
////  tlb_rd_tte_data_ebit ; // page with side effects
626
 
627
assign  spec_access_epage_m =
628
// Bug 5166
629
((ld_inst_vld_m & ~atomic_m) & nofault_asi_m & lsu_alt_space_m);   // spec load
630
dff_s #(1) spec_access_epage_stgg   (
631
        .din    (spec_access_epage_m),
632
        .q      (spec_access_epage_g),
633
        .clk    (clk),
634
        .se     (se),       .si (),          .so ()
635
        );
636
// remove flsh_inst_g ??   
637
//assign spec_access_epage = (spec_access_epage_g  | flsh_inst_g) & pg_with_ebit;
638
assign spec_access_epage = (spec_access_epage_g) & pg_with_ebit;
639
 
640
 
641
   wire quad_asi_non_ldstda_m;
642
   // covers regular quad asi AND binit. 
643
   assign quad_asi_non_ldstda_m =
644
        quad_asi_m & lsu_alt_space_m &
645
                ((~ldst_dbl_m & ld_inst_vld_m) | // only lddbl should use
646
                (fp_ldst_m & (ld_inst_vld_m | st_inst_vld_m))) ; // float should not use
647
 
648
   wire true_quad_non_ldda_m ;
649
   // catches case where st or non-ldd uses asi
650
   assign true_quad_non_ldda_m =
651
        (quad_asi_m & ~binit_quad_asi_m) & lsu_alt_space_m &
652
  ((~ldst_dbl_m & ld_inst_vld_m) | st_inst_vld_m) ;
653
 
654
wire  blk_asi_non_ldstdfa_m ;
655
 
656
assign  blk_asi_non_ldstdfa_m = blk_asi_m & lsu_alt_space_m &
657
     ~(ldst_dbl_m & fp_ldst_m) & (ld_inst_vld_m | st_inst_vld_m) ;
658
 
659
// trap on illegal asi
660
wire  illegal_asi_trap_m, illegal_asi_trap_g, illegal_asi_trap_m_d1 ;
661
 
662
assign  illegal_asi_trap_m =
663
((ld_inst_vld_m | st_inst_vld_m) & lsu_alt_space_m & ~recognized_asi_m) |
664
((ld_inst_vld_m | st_inst_vld_m) & asi_internal_m & fp_ldst_m & lsu_alt_space_m) | // Bug 4382
665
blk_asi_non_ldstdfa_m |
666
quad_asi_non_ldstda_m |
667
true_quad_non_ldda_m  ;
668
 
669
dff_s #(1) illegal_asi_trap_stgg   (
670
        .din    (illegal_asi_trap_m),
671
        .q      (illegal_asi_trap_m_d1),
672
        .clk    (clk),
673
        .se     (se),       .si (),          .so ()
674
        );
675
   //need lsu_inst_vld_w ??
676
//   assign illegal_asi_trap_g = illegal_asi_trap_m_d1 & lsu_inst_vld_w;
677
   assign illegal_asi_trap_g = illegal_asi_trap_m_d1;
678
 
679
wire wr_to_strm_sync_m ;
680
//timing
681
//assign        wr_to_strm_sync =       
682
//  strm_asi & ((ldst_va_g[7:0] == 8'hA0) | (ldst_va_g[7:0] == 8'h68)) &
683
//  st_inst_vld_unflushed & lsu_alt_space_g ;
684
 
685
assign  wr_to_strm_sync_m =     // Bug 5742
686
  strm_asi_m & (lsu_ldst_va_m[7:0] == 8'hA0) & st_inst_vld_m & lsu_alt_space_m ;
687
 
688
/*dff #(1) wr_to_strm_sync_stgg   (
689
        .din    (wr_to_strm_sync_m),
690
        .q      (wr_to_strm_sync),
691
        .clk    (clk),
692
        .se     (se),       .si (),          .so ()
693
        );*/
694
 
695
 
696
// HPV Changes 
697
// Push back into previous stage.
698
// qualification with hpv_priv and hpstate_en required to ensure hypervisor
699
// is not trying to access.
700
//SC2   wire hpv_priv_e;
701
 
702
//SC2 mux4ds  #(1) hpv_priv_e_mux (
703
//SC2        .in0    (tlu_lsu_hpv_priv[0]),
704
//SC2        .in1    (tlu_lsu_hpv_priv[1]),
705
//SC2        .in2    (tlu_lsu_hpv_priv[2]),
706
//SC2        .in3    (tlu_lsu_hpv_priv[3]),
707
//SC2        .sel0   (thread0_e),  
708
//SC2        .sel1   (thread1_e),
709
//SC2        .sel2   (thread2_e),  
710
//SC2        .sel3   (thread3_e),
711
//SC2       .dout   (hpv_priv_e)
712
//SC2);
713
 
714
//SC2   wire hpstate_en_e;
715
 
716
//SC2 mux4ds  #(1) hpstate_en_e_mux (
717
//SC2        .in0    (tlu_lsu_hpstate_en[0]),
718
//SC2        .in1    (tlu_lsu_hpstate_en[1]),
719
//SC2        .in2    (tlu_lsu_hpstate_en[2]),
720
//SC2        .in3    (tlu_lsu_hpstate_en[3]),
721
//SC2        .sel0   (thread0_e),  
722
//SC2        .sel1   (thread1_e),
723
//SC2        .sel2   (thread2_e),  
724
//SC2        .sel3   (thread3_e),
725
//SC2        .dout   (hpstate_en_e)
726
//SC2);
727
//SC2   wire hpstate_en_m;
728
 
729
//SC2 dff #(2) hpv_stgm (
730
//SC2        .din    ({hpv_priv_e, hpstate_en_e}),
731
//SC2        .q         ({hpv_priv_m, hpstate_en_m}),
732
//SC2        .clk    (clk),
733
//SC2        .se     (se),       .si (),          .so ()
734
//SC2        );
735
//SC2   wire hpv_priv, hpstate_en;
736
 
737
 
738
//SC2 dff #(2) hpv_stgg (
739
//SC2        .din    ({hpv_priv_m, hpstate_en_m}),
740
//SC2        .q         ({hpv_priv,   hpstate_en}),
741
//SC2        .clk    (clk),
742
//SC2        .se     (se),       .si (),          .so ()
743
//SC2        );
744
 
745
/*assign  priv_action = (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~lsu_asi_state[7] &
746
      ~pstate_priv & ~(hpv_priv & hpstate_en) & lsu_alt_space_g ;*/
747
// Generate a stage earlier
748
   wire priv_action_m, priv_action;
749
 
750
assign  priv_action_m = (ld_inst_vld_m | st_inst_vld_m) &
751
        ((~lsu_excpctl_asi_state_m[7] & lsu_alt_space_m) |      // alt_space
752
        lsu_nonalt_nucl_access_m) &             // non-alt space - nucleus ctxt
753
      ~pstate_priv_m & ~(hpv_priv_m & hpstate_en_m) ;
754
 
755
/*assign  priv_action_m = (ld_inst_vld_m | st_inst_vld_m) & ~lsu_excpctl_asi_state_m[7] &
756
      ~pstate_priv_m & ~(hpv_priv_m & hpstate_en_m) & lsu_alt_space_m ;*/
757
 
758
dff_s  pact_stgg (
759
        .din    (priv_action_m),
760
        .q      (priv_action),
761
        .clk    (clk),
762
        .se     (se),       .si (),          .so ()
763
        );
764
 
765
// Take data_access exception if supervisor uses hypervisor asi  
766
   wire hpv_asi_range_m;
767
   wire spv_use_hpv_m ;
768
//timing
769
//assign  hpv_asi_range =
770
//                    ~lsu_asi_state[7] & (
771
//                         (~lsu_asi_state[6] & lsu_asi_state[5] & lsu_asi_state[4]) | // 0x3?
772
//                         ( lsu_asi_state[6]));  
773
 
774
assign  hpv_asi_range_m =
775
                         ~lsu_excpctl_asi_state_m[7] & (
776
                         (~lsu_excpctl_asi_state_m[6] & lsu_excpctl_asi_state_m[5] & lsu_excpctl_asi_state_m[4]) | // 0x3?
777
                         ( lsu_excpctl_asi_state_m[6]));                                   // 0x4?,5?,6?,7?
778
 
779
// Take data_access exception if supervisor uses hypervisor asi
780
 
781
assign  spv_use_hpv_m = (ld_inst_vld_m | st_inst_vld_m) &
782
                         hpv_asi_range_m &
783
                         pstate_priv_m & ~hpv_priv_m & lsu_alt_space_m ;
784
 
785
// EARLY TRAPS
786
 
787
// memory address not aligned
788
wire  qw_align_addr,blk_align_addr ;
789
wire  hw_align_addr,wd_align_addr,dw_align_addr;
790
 
791
assign  hw_align_addr = ~lsu_ldst_va_m[0] ;         // half-word addr
792
assign  wd_align_addr = ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ;     // word addr
793
assign  dw_align_addr = ~lsu_ldst_va_m[2] & ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // dw addr
794
assign  qw_align_addr = ~lsu_ldst_va_m[3] & ~lsu_ldst_va_m[2] & ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // qw addr
795
assign  blk_align_addr =
796
~lsu_ldst_va_m[5] & ~lsu_ldst_va_m[4] & ~lsu_ldst_va_m[3] &
797
~lsu_ldst_va_m[2] & ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // 64B aligned addr for block ld/st
798
 
799
wire  hw_size,wd_size,dw_size;
800
 
801
//assign  byte_size = ~ldst_sz_m[1] &  ~ldst_sz_m[0] ; // byte size    
802
assign  hw_size = ~ldst_sz_m[1] &  ldst_sz_m[0] ; // half-word size 
803
assign  wd_size =  ldst_sz_m[1] & ~ldst_sz_m[0] ; // word size
804
assign  dw_size =  ldst_sz_m[1] &  ldst_sz_m[0] ; // double-word size
805
 
806
wire  mem_addr_not_align ;
807
 
808
assign  mem_addr_not_align
809
  = (((hw_size & ~hw_align_addr) | // half-word check
810
    (wd_size & ~wd_align_addr)  | // word check
811
    (dw_size & ~dw_align_addr)  | // double word check
812
    //((quad_asi_m | binit_quad_asi_m) & lsu_alt_space_m & ldst_dbl_m & ~qw_align_addr) | // quad word check
813
    (blk_asi_m & lsu_alt_space_m & fp_ldst_m & ldst_dbl_m & ~blk_align_addr)) & // 64B blk ld/st check
814
    //(blk_asi_m & lsu_alt_space_m & blk_asi_m & ~blk_align_addr)) & // 64B blk ld/st check
815
    (ld_inst_vld_m | st_inst_vld_m)) |
816
    // check only for loads 
817
    (((quad_asi_m | binit_quad_asi_m) & lsu_alt_space_m & ldst_dbl_m & ~qw_align_addr) & ld_inst_vld_m) ; // quad word check
818
 
819
// To be removed !! Now supported for both ld and st thru unimp_asi.
820
//wire  blkst_cmt_daccess_excp_m ;
821
//assign        blkst_cmt_daccess_excp_m =
822
//    (blk_cmt_asi_m & lsu_alt_space_m & fp_ldst_m & ldst_dbl_m & st_inst_vld_m) ;
823
 
824
   wire    stdf_maddr_not_align, lddf_maddr_not_align ;
825
 
826
assign  stdf_maddr_not_align
827
    = st_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr
828
      & ~((blk_asi_m | quad_asi_m) & lsu_alt_space_m);
829
 
830
assign  lddf_maddr_not_align
831
    = ld_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr
832
      & ~((blk_asi_m | quad_asi_m) & lsu_alt_space_m);
833
 
834
// internal asi access by ld/st other than ldxa/stxa/lddfa/stdfa.
835
wire  asi_internal_non_xdw ;
836
 
837
assign  asi_internal_non_xdw
838
    = (st_inst_vld_m | ld_inst_vld_m) & lsu_alt_space_m & asi_internal_m  &
839
      ~(dw_size & (~ldst_dbl_m | fp_ldst_m)) ; //bug4149;
840
 
841
 
842
// asi related
843
// rd-only mmu asi requiring va decode.
844
wire    mmu_rd_only_asi_wva_m ;
845
assign  mmu_rd_only_asi_wva_m =
846
        ((lsu_excpctl_asi_state_m[7:0]==8'h58) & (
847
                (lsu_ldst_va_m[7:0] == 8'h00) |  // dtag_target
848
                (lsu_ldst_va_m[7:0] == 8'h20))) |        // dsync_far
849
        ((lsu_excpctl_asi_state_m[7:0]==8'h50) &
850
                (lsu_ldst_va_m[7:0] == 8'h00)) ;         // itag_target
851
 
852
wire  wr_to_rd_only_asi, rd_of_wr_only_asi, unimp_asi_used;
853
 
854
assign  wr_to_rd_only_asi =
855
        ((mmu_rd_only_asi_wva_m |// mmu with non-unique asi
856
        mmu_rd_only_asi_m |     // mmu with unique asi
857
        rd_only_asi_m)          // non mmu
858
         &  st_inst_vld_m & lsu_alt_space_m) |
859
        wr_to_strm_sync_m ;     // Bug 5399
860
 
861
assign  rd_of_wr_only_asi = wr_only_asi_m &  ld_inst_vld_m & lsu_alt_space_m ;
862
assign  unimp_asi_used = unimp_asi_m &  (ld_inst_vld_m | st_inst_vld_m) & lsu_alt_space_m ;
863
 
864
   wire asi_related_trap_m ; // asi_related_trap_g;
865
 
866
assign  asi_related_trap_m = wr_to_rd_only_asi | rd_of_wr_only_asi | unimp_asi_used | asi_internal_non_xdw ;
867
 
868
// Illegal page size for tlb fill
869
 
870
wire    [2:0]    pgszr_m,pgszv_m ;
871
dff_s #(6)   pgsz_stgm (
872
        .din    ({lsu_sun4r_pgsz_b2t0_e[2:0],lsu_sun4v_pgsz_b2t0_e[2:0]}),
873
        .q      ({pgszr_m[2:0],pgszv_m[2:0]}),
874
        .clk    (clk),
875
        .se     (se),       .si (),          .so ()
876
        );
877
 
878
wire    [2:0]    pgsz_m ;
879
 
880
assign  pgsz_m[2:0] = lsu_sun4r_va_m_l ? pgszv_m[2:0] : pgszr_m[2:0] ;
881
 
882
wire    illgl_pgsz_m ;
883
assign  illgl_pgsz_m =
884
        (~pgsz_m[2] &  pgsz_m[1] & ~pgsz_m[0]) | // 010 ; 512K
885
        ( pgsz_m[2] & ~pgsz_m[1] & ~pgsz_m[0]) | // 100 ; 32M
886
        ( pgsz_m[2] &  pgsz_m[1] & ~pgsz_m[0]) | // 110 ; 2G
887
        ( pgsz_m[2] &  pgsz_m[1] &  pgsz_m[0]) ; // 111 ; 16G
888
 
889
wire    ifill_tlb_asi_m,dfill_tlb_asi_m ;
890
dff_s #(2)   idfill_stgm (
891
        .din    ({ifill_tlb_asi_e,dfill_tlb_asi_e}),
892
        .q      ({ifill_tlb_asi_m,dfill_tlb_asi_m}),
893
        .clk    (clk),
894
        .se     (se),       .si (),          .so ()
895
        );
896
 
897
assign  tlb_illgl_pgsz_m =
898
        (ifill_tlb_asi_m | dfill_tlb_asi_m) & st_inst_vld_m & lsu_alt_space_m & illgl_pgsz_m ;
899
 
900
wire  [8:0] early_ttype_m,early_ttype_g ;
901
wire    early_trap_vld_m, early_trap_vld_g ;
902
assign  early_trap_vld_m =
903
                        stdf_maddr_not_align | lddf_maddr_not_align |
904
                        mem_addr_not_align ;
905
 
906
wire    lsu_tlu_misalign_addr_ldst_atm_m ;
907
assign  lsu_tlu_misalign_addr_ldst_atm_m = early_trap_vld_m ;
908
 
909
// mux select order must be maintained
910
assign  early_ttype_m[8:0] =
911
      stdf_maddr_not_align ? 9'h036 :
912
        lddf_maddr_not_align ? 9'h035 :
913
           mem_addr_not_align ?  9'h034 : 9'hxxx ;
914
 
915
dff_s #(10)   etrp_stgg (
916
        .din    ({early_ttype_m[8:0],early_trap_vld_m}),
917
        .q      ({early_ttype_g[8:0],early_trap_vld_g}),
918
        .clk    (clk),
919
        .se     (se),       .si (),          .so ()
920
        );
921
 
922
wire daccess_excptn_early_m, daccess_excptn_early_g ;
923
 
924
wire atm_access_w_nc_byp_m,atm_access_w_nc_byp_g ;
925
assign atm_access_w_nc_byp_m =
926
atomic_m & dtlb_bypass_m & (lsu_ldst_va_b39_m & ~pstate_am_m) ;
927
                                                //Bug 5050
928
 
929
dff_s   atmbyp_stgg (
930
        .din    (atm_access_w_nc_byp_m),
931
        .q      (atm_access_w_nc_byp_g),
932
        .clk    (clk),
933
        .se     (se),       .si (),          .so ()
934
        );
935
 
936
assign daccess_excptn_early_m =
937
    asi_related_trap_m | tlb_daccess_excptn_m |
938
    spv_use_hpv_m |
939
    atm_access_w_nc_byp_m ; // Bug 4281.
940
 
941
dff_s  #(1) dearly_stgg (
942
        .din    (daccess_excptn_early_m),
943
        .q      (daccess_excptn_early_g),
944
        .clk    (clk),
945
        .se     (se),       .si (),          .so ()
946
        );
947
 
948
   wire daccess_excptn;
949
 
950
assign  daccess_excptn =
951
    (priv_pg_usr_mode | as_if_usr_priv_pg | nfo_pg_nonnfo_asi |
952
      atm_access_w_nc ) & tlb_tte_vld_g |
953
      illegal_asi_trap_g | daccess_excptn_early_g | atm_access_unsup_asi | //bug4622
954
        spec_access_epage ;
955
 
956
   wire [3:0] lsu_nceen_d1;
957
dff_s #(4)  nceen_d1_ff (
958
        .din    (ifu_lsu_nceen[3:0]),
959
        .q      (lsu_nceen_d1[3:0]),
960
        .clk    (clk),
961
        .se     (se),       .si (),          .so ()
962
        );
963
 
964
wire nceen_pipe_g ;
965
assign  nceen_pipe_g =
966
  (thread0_g & lsu_nceen_d1[0]) | (thread1_g & lsu_nceen_d1[1]) |
967
  (thread2_g & lsu_nceen_d1[2]) | (thread3_g & lsu_nceen_d1[3]) ;
968
 
969
 // correctible dtlb data parity error on cam will cause dmmu miss.
970
// prefetch will rely on the ld_inst_vld/st_inst_vld not being asserted
971
// to prevent mmu_miss from being signalled if prefetch does not translate.
972
// Timing Change : Remove data perror from dmmu_miss ; to be treated as disrupting trap.
973
   wire dmmu_miss_m, dmmu_miss_m_d1;
974
 
975
assign dmmu_miss_m =
976
  ~tlb_cam_hit & ~dtlb_bypass_m &
977
  (ld_inst_vld_m | st_inst_vld_m) &
978
  ~(lda_internal_m | sta_internal_m | early_trap_vld_m) ;
979
 
980
dff_s #(1)  dmmu_miss_stgg (
981
        .din    (dmmu_miss_m),
982
        .q      (dmmu_miss_m_d1),
983
        .clk    (clk),
984
        .se     (se),       .si (),          .so ()
985
        );
986
//need lsu_inst_vld_w ??
987
   wire dmmu_miss_g;
988
 
989
   assign dmmu_miss_g = dmmu_miss_m_d1 & lsu_inst_vld_w;
990
 
991
 
992
wire [8:0] dmiss_type ;
993
   wire    cam_real_g;
994
 
995
dff_s #(1) cam_real_stgg (
996
   .din (cam_real_m),
997
   .q   (cam_real_g),
998
   .clk    (clk),
999
   .se     (se),       .si (),          .so ()
1000
   );
1001
 assign        dmiss_type[8:0] = cam_real_g ? 9'h03f : 9'h068 ;
1002
 
1003
// two wtchpt matches
1004
//assign  lsu_tlu_ttype_m2[8:0] = 
1005
//  early_trap_vld_g ? early_ttype_g[8:0] : 
1006
//    priv_action ? 9'h037 : 
1007
//      va_wtchpt_match ? 9'h062 :
1008
//        daccess_excptn ? 9'h030 : 
1009
//          dmmu_miss_g ? dmiss_type[8:0] :  // dmmu_miss
1010
//            daccess_error ? 9'h032 : 
1011
//              daccess_prot ? 9'h06c :
1012
//                    spubyp_trap_active_g ? {3'b000,spubyp_ttype[5:0]} : // should be no other tttype to compare to. 
1013
//                  9'bx_xxxx_xxxx ;
1014
 
1015
wire early_trap_vld_sel, priv_action_sel, va_wtchpt_match_sel, daccess_excptn_sel, dmmu_miss_sel,
1016
     daccess_prot_sel ;
1017
 
1018
// Need to maintain this order in selects. Based on priority of traps    
1019
   assign early_trap_vld_sel = early_trap_vld_g;
1020
   assign priv_action_sel = ~early_trap_vld_sel & priv_action;
1021
   assign va_wtchpt_match_sel = ~early_trap_vld_sel & ~priv_action_sel & va_wtchpt_match;
1022
   assign daccess_excptn_sel = ~early_trap_vld_sel & ~priv_action_sel & ~va_wtchpt_match_sel &
1023
                               daccess_excptn;
1024
   assign dmmu_miss_sel = ~early_trap_vld_sel & ~priv_action_sel & ~va_wtchpt_match_sel &
1025
                          ~daccess_excptn_sel & dmmu_miss_g;
1026
 
1027
   assign daccess_prot_sel = ~early_trap_vld_sel & ~priv_action_sel & ~va_wtchpt_match_sel &
1028
                             ~daccess_excptn_sel & ~dmmu_miss_sel & daccess_prot;
1029
 
1030
assign  lsu_tlu_ttype_m2[8:0] =
1031
          ({9{early_trap_vld_sel}}     &  early_ttype_g[8:0]) |
1032
          ({9{priv_action_sel}}        &  9'h037            ) |
1033
          ({9{va_wtchpt_match_sel}}    &  9'h062            ) |
1034
          ({9{daccess_excptn_sel}}     &  9'h030            ) |
1035
          ({9{dmmu_miss_sel}}          &  dmiss_type[8:0]   ) |
1036
          ({9{daccess_prot_sel}}       &  9'h06c            ) ;
1037
 
1038
assign  lsu_tlu_ttype_vld_m2 =  dmmu_miss_g | daccess_excptn | daccess_prot |
1039
        priv_action | early_trap_vld_g  |
1040
              va_wtchpt_match ;
1041
 
1042
assign lsu_ttype_vld_m2 = lsu_tlu_ttype_vld_m2 | defr_trp_taken ;  //to stb_rwctl
1043
 
1044
assign lsu_ttype_vld_m2_bf1 =    lsu_ttype_vld_m2; //to dctl, qctl1
1045
 
1046
wire    squash_priority_g ; // Bug 4678
1047
assign  squash_priority_g = priv_action | early_trap_vld_g | va_wtchpt_match ;
1048
 
1049
assign  lsu_tlu_dmmu_miss_g = dmmu_miss_g & ~squash_priority_g ;
1050
assign  lsu_tlu_priv_violtn_g = (priv_pg_usr_mode | as_if_usr_priv_pg) & tlb_tte_vld_g ;
1051
wire    dmmu_va_oor_g ;
1052
assign  lsu_tlu_daccess_excptn_g =
1053
(daccess_excptn | dmmu_va_oor_g  // Bug 5036
1054
| tlu_priv_trap_g) & ~squash_priority_g ;
1055
 
1056
// prioritize daccess_excptn higher than daccess_prot. This may
1057
// be a critical path which needs to be resolved -> qual. now
1058
// in mmu.
1059
//assign  lsu_tlu_daccess_prot_g = daccess_prot ;
1060
   wire daccess_prot_g;
1061
assign  daccess_prot_g = daccess_prot &
1062
        ~(tlu_priv_trap_g | daccess_excptn | squash_priority_g) ;
1063
assign  lsu_tlu_daccess_prot_g = daccess_prot & ~squash_priority_g ; // Bug 5336.
1064
assign  lsu_tlu_priv_action_g = priv_action ;
1065
//assign  lsu_tlu_tte_ebit_g = tlb_rd_tte_data_ebit & tlb_tte_vld_g ;
1066
wire    lsu_tlu_tte_ebit_g;
1067
assign  lsu_tlu_tte_ebit_g = pg_with_ebit ;
1068
//assign  lsu_tlu_spec_access_epage_g = spec_access_epage & tlb_tte_vld_g ; // page with side effects
1069
wire    lsu_tlu_spec_access_epage_g ;
1070
assign  lsu_tlu_spec_access_epage_g = spec_access_epage ; // page with side effects
1071
wire    lsu_tlu_uncache_atomic_g;
1072
assign  lsu_tlu_uncache_atomic_g =
1073
        (atm_access_w_nc & tlb_tte_vld_g) |
1074
        (atm_access_w_nc_byp_g) ;
1075
// Define illegal asi actions
1076
// see sfsr description - excludes cases where 02 and 04 are set for ftype !!!
1077
wire lsu_tlu_flt_ld_nfo_pg_g;
1078
assign  lsu_tlu_flt_ld_nfo_pg_g = nfo_pg_nonnfo_asi & tlb_tte_vld_g ;
1079
 
1080
wire illgl_asi_action_pre_m,illgl_asi_action_pre_g ;
1081
assign  illgl_asi_action_pre_m = asi_related_trap_m | tlb_daccess_excptn_m | illegal_asi_trap_m | spv_use_hpv_m ; // bug 4181; //bug3660        
1082
 
1083
dff_s  illglasi_g (
1084
        .din    (illgl_asi_action_pre_m),
1085
        .q      (illgl_asi_action_pre_g),
1086
        .clk    (clk),
1087
        .se     (se),       .si (),          .so ()
1088
        );
1089
 
1090
wire lsu_tlu_illegal_asi_action_g;
1091
assign  lsu_tlu_illegal_asi_action_g =
1092
atm_access_unsup_asi | (illgl_asi_action_pre_g) & // Bug 4825
1093
~(lsu_tlu_spec_access_epage_g | lsu_tlu_uncache_atomic_g) ;
1094
//(illgl_asi_action_pre_g | (atm_access_unsup_asi)) & 
1095
//~(lsu_tlu_spec_access_epage_g | lsu_tlu_uncache_atomic_g) ;
1096
 
1097
//=========================================================================================
1098
//  Generate Flush Pipe
1099
//=========================================================================================
1100
 
1101
 
1102
assign  other_flush_pipe_w =
1103
tlu_early_flush_pipe_w | (lsu_tlu_ttype_vld_m2 & lsu_inst_vld_w) |
1104
defr_trp_taken ;        // deferred trap.
1105
assign  lsu_ifu_flush_pipe_w = other_flush_pipe_w ;
1106
assign  lsu_exu_flush_pipe_w = other_flush_pipe_w ;
1107
assign  lsu_mmu_flush_pipe_w = other_flush_pipe_w ;
1108
assign  lsu_ffu_flush_pipe_w = other_flush_pipe_w ;
1109
 
1110
 
1111
assign  lsu_flush_pipe_w = other_flush_pipe_w | ifu_lsu_flush_w ;
1112
 
1113
//assign        lsu_qctl1_flush_pipe_w = lsu_flush_pipe_w ;
1114
//assign        lsu_stbctl_flush_pipe_w = lsu_flush_pipe_w ;
1115
//assign        lsu_stbrwctl_flush_pipe_w = lsu_flush_pipe_w ;
1116
 
1117
//=========================================================================================
1118
//  Early Traps to SPU
1119
//=========================================================================================
1120
 
1121
// detect st to ma/strm sync - data-access exception.
1122
//wire  st_to_sync_dexcp_m ;
1123
// qual with alt_space not required - spu will do it.
1124
//assign        st_to_sync_dexcp_m = // Bug 5704
1125
//strm_asi_m & ((lsu_ldst_va_m[7:0] == 8'ha0) | (lsu_ldst_va_m[7:0] == 8'h68)) & st_inst_vld_m ;  
1126
 
1127
wire    early_flush_m ;
1128
 
1129
assign  early_flush_m =
1130
        (atomic_m & lsu_alt_space_m) |  // Bug 4650 - alt-space atomics should flush.
1131
        priv_action_m           |
1132
        early_trap_vld_m        |       // mem-addr-not-aligned.
1133
        illegal_asi_trap_m      |       // for fp non use of internal asi.
1134
        //st_to_sync_dexcp_m    |       // Bug 5742
1135
        //wr_to_strm_sync_m     |       // Bug 5890 - redundant - make room.
1136
        defr_trp_taken_m_din    |       // Bug 5890
1137
        daccess_excptn_early_m  ;
1138
        /*asi_related_trap_m    |       // Bug 2592
1139
        spv_use_hpv_m       |
1140
        wr_to_strm_sync_m;*/
1141
 
1142
 
1143
dff_s  eflushspu_g (
1144
        .din    (early_flush_m),
1145
        .q      (lsu_spu_early_flush_g),
1146
        .clk    (clk),
1147
        .se     (se),       .si (),          .so ()
1148
        );
1149
 
1150
dff_s  eflushspu2_g (
1151
        .din    (early_flush_m),
1152
        .q      (lsu_local_early_flush_g),
1153
        .clk    (clk),
1154
        .se     (se),       .si (),          .so ()
1155
        );
1156
 
1157
dff_s  eflushtlu_g (
1158
        .din    (early_flush_m),
1159
        .q      (lsu_tlu_early_flush_w),
1160
        .clk    (clk),
1161
        .se     (se),       .si (),          .so ()
1162
        );
1163
 
1164
dff_s  eflushtlu2_g (
1165
        .din    (early_flush_m),
1166
        .q      (lsu_tlu_early_flush2_w),
1167
        .clk    (clk),
1168
        .se     (se),       .si (),          .so ()
1169
        );
1170
 
1171
 
1172
//=========================================================================================
1173
//  Parity Error Checking
1174
//=========================================================================================
1175
 
1176
// DTLB Parity Errors. 
1177
// ASI read of Tag/Data :
1178
//  - uncorrectible error
1179
//  - logging occurs on read.
1180
//  - precise trap is taken when ldxa completes if nceen set.
1181
//  - if not set then ldxa is allowed to complete.
1182
// CAM Read of Tag/Data :
1183
//  - correctible if locked bit not set.
1184
//    - takes disrupting trap later.
1185
//  - uncorrectible if locked bit set.
1186
//  - both are treated as precise traps.
1187
//  - if errors not enabled, then load completes as if hit in L1.
1188
// ** TLB error will cause a trap which will preclude concurrent dcache,dtag  **
1189
// ** parity errors.                **
1190
 
1191
// cam related tte data parity error - error assumed correctible if locked
1192
// bit is not set. Will cause a dmmu_miss for correction.
1193
// qualify with cam_hit ??
1194
wire  tte_data_perror_unc ;
1195
 
1196
assign  lsu_tlb_perr_ld_rq_kill_w =
1197
        //tte_data_perror_corr | (tte_data_perror_unc & nceen_pipe_g) ;
1198
        (tte_data_perror_unc & nceen_pipe_g) ;
1199
 
1200
// correctible dtlb errors no longer supported.
1201
/*assign  tte_data_perror_corr =
1202
  tte_data_parity_error & ~tlb_rd_tte_data_locked & tlb_tte_vld_g &
1203
  (ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w ;*/
1204
 
1205
// caused for both locked and unlocked entries.
1206
assign  tte_data_perror_unc  =
1207
  //tte_data_parity_error &  tlb_rd_tte_data_locked & tlb_tte_vld_g & 
1208
  tte_data_parity_error &  tlb_tte_vld_g &
1209
  (ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w &
1210
  ~lsu_flush_pipe_w ;
1211
 
1212
// Asi rd parity error detection
1213
wire  asi_tte_data_perror,asi_tte_tag_perror ;
1214
 
1215
assign  asi_tte_data_perror =
1216
  tte_data_parity_error & data_rd_vld_g ;
1217
// For data tte read, both tag and data arrays are read.
1218
// Parity error on asi read of tag should not be reported.
1219
assign  asi_tte_tag_perror =
1220
  tte_tag_parity_error & tag_rd_vld_g & ~data_rd_vld_g ;
1221
 
1222
wire    st_dtlb_perror ;
1223
assign  st_dtlb_perror =   tte_data_parity_error &  tlb_tte_vld_g &
1224
   st_inst_vld_unflushed & lsu_inst_vld_w ;
1225
 // ~lsu_flush_pipe_w ;
1226
 
1227
wire    cancel_err_flush ;
1228
assign  cancel_err_flush = // Bug 5165
1229
((priv_pg_usr_mode | nfo_pg_nonnfo_asi |
1230
atm_access_w_nc) & tlb_tte_vld_g) | // bug6052/eco6620
1231
spec_access_epage |
1232
nonwr_pg_st_access ;
1233
 
1234
// Bug 6877
1235
wire squash_err ;
1236
assign squash_err =
1237
// assume always higher priority. BE - share common terms elsewhere.
1238
tlu_early_flush_pipe_w | defr_trp_taken | ifu_lsu_flush_w |
1239
// isolate to daccess_excptn/daccess_prot as per Bug 5165.
1240
(lsu_tlu_ttype_vld_m2 & ~(daccess_excptn_sel | daccess_prot_sel)) |
1241
((daccess_excptn_sel | daccess_prot_sel) & ~cancel_err_flush) ;
1242
 
1243
wire    tlb_data_su_g ;
1244
assign  tlb_data_su_g =   st_dtlb_perror & ~atomic_g &
1245
  ~squash_err ;
1246
  //~(lsu_flush_pipe_w & ~cancel_err_flush) ; // Bug 6877
1247
 
1248
wire    ld_dtlb_perror ;
1249
assign  ld_dtlb_perror =   tte_data_parity_error &  tlb_tte_vld_g &
1250
  ld_inst_vld_unflushed  & lsu_inst_vld_w &
1251
  ~squash_err ;
1252
 
1253
wire  tlb_data_ue_g ;
1254
assign  tlb_data_ue_g =
1255
        ld_dtlb_perror |        // synchronous to pipe - xslate ; ue is for ld now.
1256
        lsu_tlb_asi_data_perr_g ; // asychronous to pipe - asi rd
1257
 
1258
/* Simplify for Bug 5888.
1259
wire    st_noatom_dtlb_perr ; // atomics not represented.
1260
assign  st_noatom_dtlb_perr = st_dtlb_perror & ~lsu_flush_pipe_w & ~atomic_g ;
1261
wire    st_noatom_dtlb_perr_en ;
1262
assign  st_noatom_dtlb_perr_en = st_noatom_dtlb_perr & nceen_pipe_g ; */
1263
wire    st_noatom_dtlb_perr_en ;
1264
wire    st_dtlb_perr_en ;
1265
assign  st_noatom_dtlb_perr_en = st_dtlb_perr_en & ~atomic_g ;
1266
 
1267
// rm corr err. reporting
1268
dff_s  #(3) terr_stgd1 (
1269
        .din    ({tlb_data_su_g,tlb_data_ue_g,lsu_tlb_asi_tag_perr_g}),
1270
        //.din    ({st_noatom_dtlb_perr,tlb_data_ue_g,lsu_tlb_asi_tag_perr_g}),
1271
        .q      ({lsu_ifu_tlb_data_su,lsu_ifu_tlb_data_ue,lsu_ifu_tlb_tag_ue}),
1272
        .clk    (clk),
1273
        .se     (se),       .si (),          .so ()
1274
        );
1275
 
1276
// If st dtlb parity error detected, then need to invalidate st in stb.
1277
// Considered unrecoverable for the thread itself.
1278
 
1279
assign  st_dtlb_perr_en = st_dtlb_perror & ~lsu_flush_pipe_w & nceen_pipe_g ;
1280
 
1281
// Kill will happen for atomics also.
1282
//assign        lsu_exu_st_dtlb_perr_g = st_dtlb_perr_en ;
1283
assign  lsu_exu_st_dtlb_perr_g = st_noatom_dtlb_perr_en ; // Bug 5888
1284
 
1285
assign  lsu_ffu_st_dtlb_perr_g = st_noatom_dtlb_perr_en ; // Bug 5910/ECO 6529
1286
 
1287
assign  lsu_st_dtlb_perr_g[0] = st_dtlb_perr_en & thread0_g ;
1288
assign  lsu_st_dtlb_perr_g[1] = st_dtlb_perr_en & thread1_g ;
1289
assign  lsu_st_dtlb_perr_g[2] = st_dtlb_perr_en & thread2_g ;
1290
assign  lsu_st_dtlb_perr_g[3] = st_dtlb_perr_en & thread3_g ;
1291
 
1292
//==========================================================================
1293
// DEFERRED TRAP DUE TO STORE 
1294
//==========================================================================
1295
 
1296
// Cases :
1297
// defr_trp_m=1,ifu_flush_w=0. 
1298
//      - defr_trp is generated.
1299
//      - next inst will not take redundant deferred trap as
1300
//      its inst_vld will be annulled by trap flush.
1301
// defr_trp_m=1,ifu_flush_w=1. 
1302
//      - defr_trp is generated. TLU annuls.
1303
//      - Other units see redundant defr_trp flush ORed with ifu_flush_w.
1304
//      - next inst will not take redundant deferred trap as
1305
//      its inst_vld will be annulled by ifu_flush_w .
1306
 
1307
 
1308
// Log Deferred trap. Take on next available inst from thread.
1309
// Inst vld must be qualified with flush.
1310
 
1311
wire    st_defr_trp_en0,st_defr_trp_en1,st_defr_trp_en2,st_defr_trp_en3 ;
1312
wire    st_defr_trp0,st_defr_trp1,st_defr_trp2,st_defr_trp3 ;
1313
 
1314
assign  st_defr_trp_en0 = st_noatom_dtlb_perr_en & thread0_g ;
1315
assign  st_defr_trp_en1 = st_noatom_dtlb_perr_en & thread1_g ;
1316
assign  st_defr_trp_en2 = st_noatom_dtlb_perr_en & thread2_g ;
1317
assign  st_defr_trp_en3 = st_noatom_dtlb_perr_en & thread3_g ;
1318
 
1319
wire    stpend_rst0_m,stpend_rst1_m,stpend_rst2_m,stpend_rst3_m;
1320
wire    stpend_rst0_w,stpend_rst1_w,stpend_rst2_w,stpend_rst3_w;
1321
wire    stpend_rst0,stpend_rst1,stpend_rst2,stpend_rst3;
1322
assign  stpend_rst0_m = reset |
1323
((st_defr_trp0 | st_defr_trp_en0) & thread0_m & flush_w_inst_vld_m);
1324
assign  stpend_rst1_m = reset |
1325
((st_defr_trp1 | st_defr_trp_en1) & thread1_m & flush_w_inst_vld_m);
1326
assign  stpend_rst2_m = reset |
1327
((st_defr_trp2 | st_defr_trp_en2) & thread2_m & flush_w_inst_vld_m);
1328
assign  stpend_rst3_m = reset |
1329
((st_defr_trp3 | st_defr_trp_en3) & thread3_m & flush_w_inst_vld_m);
1330
 
1331
// Postphone reset by a cycle - 4916
1332
dff_s #(4)  stpend_d1 (
1333
           .din    ({stpend_rst3_m,stpend_rst2_m,stpend_rst1_m,stpend_rst0_m}),
1334
           .q      ({stpend_rst3_w,stpend_rst2_w,stpend_rst1_w,stpend_rst0_w}),
1335
           .clk    (clk),
1336
           .se     (se),       .si (),          .so ()
1337
           );
1338
 
1339
// Prevent reset if inst is flushed by ifu.
1340
assign  stpend_rst3 = stpend_rst3_w & ~ifu_lsu_flush_w ;
1341
assign  stpend_rst2 = stpend_rst2_w & ~ifu_lsu_flush_w ;
1342
assign  stpend_rst1 = stpend_rst1_w & ~ifu_lsu_flush_w ;
1343
assign  stpend_rst0 = stpend_rst0_w & ~ifu_lsu_flush_w ;
1344
 
1345
dffre_s #(1)  deftrp_t0 (
1346
           .din    (st_defr_trp_en0),
1347
           .q      (st_defr_trp0),
1348
           .rst    (stpend_rst0),
1349
           .en     (st_defr_trp_en0),
1350
           .clk    (clk),
1351
           .se     (se),       .si (),          .so ()
1352
           );
1353
 
1354
dffre_s #(1)  deftrp_t1 (
1355
           .din    (st_defr_trp_en1),
1356
           .q      (st_defr_trp1),
1357
           .rst    (stpend_rst1),
1358
           .en     (st_defr_trp_en1),
1359
           .clk    (clk),
1360
           .se     (se),       .si (),          .so ()
1361
           );
1362
 
1363
dffre_s #(1)  deftrp_t2 (
1364
           .din    (st_defr_trp_en2),
1365
           .q      (st_defr_trp2),
1366
           .rst    (stpend_rst2),
1367
           .en     (st_defr_trp_en2),
1368
           .clk    (clk),
1369
           .se     (se),       .si (),          .so ()
1370
           );
1371
 
1372
dffre_s #(1)  deftrp_t3 (
1373
           .din    (st_defr_trp_en3),
1374
           .q      (st_defr_trp3),
1375
           .rst    (stpend_rst3),
1376
           .en     (st_defr_trp_en3),
1377
           .clk    (clk),
1378
           .se     (se),       .si (),          .so ()
1379
           );
1380
 
1381
// Deferred trap can be taken on any instruction.
1382
// Selection is based on next thread available.
1383
 
1384
//instruction n+2, and the following...
1385
 
1386
assign  defr_trp_taken_m =
1387
        //ifu_tlu_inst_vld_m & (
1388
        flush_w_inst_vld_m & (  // <= rely of flush by defr-trp to clear
1389
                                // pended defr-trp
1390
        (st_defr_trp0 & thread0_m) |
1391
        (st_defr_trp1 & thread1_m) |
1392
        (st_defr_trp2 & thread2_m) |
1393
        (st_defr_trp3 & thread3_m)) ;
1394
 
1395
assign defr_trp_taken_byp =
1396
        //ifu_tlu_inst_vld_m & (
1397
        flush_w_inst_vld_m & (
1398
        (st_defr_trp_en0 & thread0_m) |
1399
        (st_defr_trp_en1 & thread1_m) |
1400
        (st_defr_trp_en2 & thread2_m) |
1401
        (st_defr_trp_en3 & thread3_m) );
1402
 
1403
 
1404
assign defr_trp_taken_m_din = defr_trp_taken_m |  defr_trp_taken_byp;
1405
 
1406
dff_s #(1) defr_trp_taken_stgg (
1407
     .din (defr_trp_taken_m_din),
1408
     .q   (defr_trp_taken),
1409
     .clk    (clk),
1410
     .se     (se),       .si (),          .so ()
1411
    );
1412
 
1413
assign  lsu_defr_trp_taken_g = defr_trp_taken ;
1414
assign  lsu_tlu_defr_trp_taken_g = defr_trp_taken ;
1415
assign  lsu_mmu_defr_trp_taken_g = defr_trp_taken ;
1416
 
1417
//==========================================================================
1418
// DSFSR/SFAR WR 
1419
//==========================================================================
1420
 
1421
 
1422
 
1423
wire    [3:0]    pstate_cle,pstate_am ;
1424
// flop'n use to prevent timing path.
1425
dff_s #(8)  cle_stg (
1426
        .din    ({tlu_lsu_pstate_cle[3:0],tlu_lsu_pstate_am[3:0]}),
1427
        .q      ({pstate_cle[3:0],pstate_am[3:0]}),
1428
        .clk    (clk),
1429
        .se     (se),       .si (),          .so ()
1430
        );
1431
 
1432
wire    pstate_cle_m ;
1433
assign  pstate_cle_m =
1434
        (thread0_m & pstate_cle[0]) |
1435
        (thread1_m & pstate_cle[1]) |
1436
        (thread2_m & pstate_cle[2]) |
1437
        (thread3_m & pstate_cle[3]);
1438
 
1439
wire    [3:0]    dsfsr_asi_sel_m ;
1440
wire    prim_asi_sel ;
1441
assign  prim_asi_sel =
1442
exu_tlu_misalign_addr_jmpl_rtn_m | (lsu_tlu_nonalt_ldst_m & ~lsu_nonalt_nucl_access_m) ;
1443
assign  dsfsr_asi_sel_m[0] =  // ASI_PRIMARY
1444
                 prim_asi_sel & ~pstate_cle_m;
1445
// Does asi_primary_little make sense for jmpl/return ?
1446
assign  dsfsr_asi_sel_m[1] =  // ASI_PRIMARY_LITTLE
1447
                prim_asi_sel  &  pstate_cle_m;
1448
assign  dsfsr_asi_sel_m[2] =  // ASI_NUCLEUS
1449
                lsu_nonalt_nucl_access_m &  ~pstate_cle_m;
1450
assign  dsfsr_asi_sel_m[3] =  // ASI_NUCLEUS_LITTLE
1451
                lsu_nonalt_nucl_access_m &   pstate_cle_m;
1452
/*assign  dsfsr_asi_sel_m[4] =  // assigned asi
1453
        ~(exu_tlu_misalign_addr_jmpl_rtn_m | lsu_tlu_nonalt_ldst_m);*/
1454
 
1455
wire    [7:0]    asi_state_g ;
1456
// flop'n use to prevent timing path.
1457
dff_s #(8)  asistate_stgg (
1458
        .din    (lsu_excpctl_asi_state_m[7:0]),
1459
        .q      (asi_state_g[7:0]),
1460
        .clk    (clk),
1461
        .se     (se),       .si (),          .so ()
1462
        );
1463
 
1464
wire    [7:0]    dsfsr_asi_g ;
1465
wire    [3:0]    dsfsr_asi_sel_g ;
1466
 
1467
/*assign dsfsr_asi_g[7:0] =(dsfsr_asi_sel_g[0] ? 8'h80 : 8'h00) |
1468
                         (dsfsr_asi_sel_g[1] ? 8'h88 : 8'h00) |
1469
                         (dsfsr_asi_sel_g[2] ? asi_state_g[7:0] : 8'h00);*/
1470
// Bug 4212 - spec problem
1471
assign dsfsr_asi_g[7:0] =(dsfsr_asi_sel_g[0] ? 8'h80 :
1472
                                (dsfsr_asi_sel_g[1] ? 8'h88 :
1473
                                        (dsfsr_asi_sel_g[2] ? 8'h04 :
1474
                                                (dsfsr_asi_sel_g[3] ?  8'h0C : asi_state_g[7:0]))));
1475
 
1476
assign  pstate_am_m =
1477
        (thread0_m & pstate_am[0]) |
1478
        (thread1_m & pstate_am[1]) |
1479
        (thread2_m & pstate_am[2]) |
1480
        (thread3_m & pstate_am[3]);
1481
 
1482
assign  dmmu_va_oor_m = exu_tlu_va_oor_m & ~pstate_am_m & lsu_memref_m & ~lsu_squash_va_oor_m;
1483
 
1484
wire    [3:0]     dsfsr_flt_vld;
1485
dff_s #(4)  fltvld_stgd1 (
1486
        .din    (tlu_dsfsr_flt_vld[3:0]),
1487
        .q      (dsfsr_flt_vld[3:0]),
1488
        .clk    (clk),
1489
        .se     (se),       .si (),          .so ()
1490
        );
1491
 
1492
wire    dsfsr_flt_vld_m ;
1493
assign  dsfsr_flt_vld_m =
1494
        (thread0_m & dsfsr_flt_vld[0]) |
1495
        (thread1_m & dsfsr_flt_vld[1]) |
1496
        (thread2_m & dsfsr_flt_vld[2]) |
1497
        (thread3_m & dsfsr_flt_vld[3]);
1498
 
1499
wire    ldst_xslate_g,flsh_inst_g,dsfsr_flt_vld_g,dsfsr_wr_op_g ;
1500
wire    misalign_addr_jmpl_rtn_g,misalign_addr_ldst_atm_g ;
1501
wire    [2:0]    dsfsr_ctxt_sel ;
1502
 
1503
// flop flt_vld and use
1504
dff_s #(14)  dsfsr_stgg (
1505
        .din    ({dsfsr_asi_sel_m[3:0],dmmu_va_oor_m,// memref_m,
1506
                lsu_tlu_xslating_ldst_m,lsu_flsh_inst_m,lsu_tlu_ctxt_sel_m[2:0],
1507
                dsfsr_flt_vld_m,lsu_tlu_write_op_m,exu_tlu_misalign_addr_jmpl_rtn_m,
1508
                lsu_tlu_misalign_addr_ldst_atm_m}),
1509
        .q      ({dsfsr_asi_sel_g[3:0],dmmu_va_oor_g,ldst_xslate_g,// memref_g,
1510
                flsh_inst_g,dsfsr_ctxt_sel[2:0],dsfsr_flt_vld_g, dsfsr_wr_op_g,
1511
                misalign_addr_jmpl_rtn_g,misalign_addr_ldst_atm_g}),
1512
        .clk    (clk),
1513
        .se     (se),       .si (),          .so ()
1514
        );
1515
 
1516
// To be set only for data_access_exception traps - only one can be
1517
// reported at any time.        
1518
 
1519
wire    [6:0]    dsfsr_ftype_g ;
1520
assign  dsfsr_ftype_g[6] = 1'b0;
1521
assign  dsfsr_ftype_g[5] = dmmu_va_oor_g | lsu_tlu_wtchpt_trp_g;
1522
assign  dsfsr_ftype_g[4] = lsu_tlu_flt_ld_nfo_pg_g;
1523
assign  dsfsr_ftype_g[3] = lsu_tlu_illegal_asi_action_g
1524
                        | tlu_priv_trap_g ; // Bug 4799
1525
//assign  dsfsr_ftype_g[3] = lsu_tlu_illegal_asi_action_g | tlu_mmu_sync_data_excp_g;
1526
assign  dsfsr_ftype_g[2] = (lsu_tlu_uncache_atomic_g & ~atm_access_unsup_asi);
1527
assign  dsfsr_ftype_g[1] = lsu_tlu_spec_access_epage_g;
1528
assign  dsfsr_ftype_g[0] = lsu_tlu_priv_violtn_g;
1529
 
1530
wire    dsfsr_side_effect_g ;
1531
assign  dsfsr_side_effect_g = lsu_tlu_tte_ebit_g & (ldst_xslate_g | flsh_inst_g);
1532
 
1533
// Fault Type based on Priority Encoding of Traps
1534
wire    [6:0]    dsfsr_pe_ftype_g ;
1535
wire    dsfsr_ftype_zero ;
1536
// Is this needed ? Doesn't it default to zero ?
1537
assign  dsfsr_pe_ftype_g[6:0] = dsfsr_ftype_zero ? 7'h00 : dsfsr_ftype_g[6:0];
1538
 
1539
// set to 11 when the access does not have a translating asi.
1540
wire    [1:0]    dsfsr_ctxt_g ;
1541
assign  dsfsr_ctxt_g[1:0] =
1542
        dsfsr_ctxt_sel[0] ? 2'b00 :
1543
                dsfsr_ctxt_sel[1] ? 2'b01 :
1544
                        dsfsr_ctxt_sel[2] ? 2'b10 : 2'b11;
1545
 
1546
 
1547
assign  lsu_dsfsr_din_g[23:0] =
1548
        {dsfsr_asi_g[7:0],
1549
        2'b0,
1550
        dsfsr_pe_ftype_g[6:0],
1551
        dsfsr_side_effect_g,
1552
        dsfsr_ctxt_g[1:0],
1553
        1'b0, // Bug 3323 - Arch change
1554
        //pstate_priv,  
1555
        dsfsr_wr_op_g,  // pipe
1556
        dsfsr_flt_vld_g,
1557
        1'b1};
1558
 
1559
// This is going to be a critical path !!!
1560
// Assume that traps in front-end cause instructions to be no`oped
1561
// further down the pipeline. Thus there is no need to qualify writes
1562
// to dsfsr with writes to isfsr
1563
wire    dsfsr_trp_wr_g ;
1564
wire    dsfsr_trp_wr_pre_m,dsfsr_trp_wr_pre_g ;
1565
 
1566
 
1567
assign  dsfsr_trp_wr_pre_m =
1568
        spv_use_hpv_m   | // Bug 3254 ; add new data-access-excp
1569
        // spec_access_epage_m | // Bug 3515
1570
        priv_action_m |
1571
        exu_tlu_misalign_addr_jmpl_rtn_m |
1572
        lsu_tlu_misalign_addr_ldst_atm_m ;
1573
 
1574
dff_s   dsfsrtrg_stgg (
1575
        .din    (dsfsr_trp_wr_pre_m),
1576
        .q      (dsfsr_trp_wr_pre_g),
1577
        .clk    (clk),
1578
        .se     (se),       .si (),          .so ()
1579
        );
1580
 
1581
assign  dsfsr_trp_wr_g =
1582
        ((lsu_tlu_priv_violtn_g  |
1583
        lsu_tlu_spec_access_epage_g |   // Bug 3515 - uncomment out.
1584
        lsu_tlu_uncache_atomic_g | lsu_tlu_illegal_asi_action_g |
1585
        lsu_tlu_flt_ld_nfo_pg_g  | dmmu_va_oor_g) |     // data access exceptions                       
1586
        daccess_prot |  // daccess_excptn not excluded.
1587
        lsu_tlu_wtchpt_trp_g     |      // watchpoint trap      
1588
        dsfsr_trp_wr_pre_g |
1589
        tlu_priv_trap_g                 // scratchpad/queue daccess;Bug 4799
1590
        ) &
1591
        lsu_inst_vld_w & ~(ifu_lsu_flush_w | defr_trp_taken) ; // Bug 4444,5196
1592
 
1593
assign  dsfsr_ftype_zero =
1594
        daccess_prot_g | lsu_tlu_priv_action_g | lsu_tlu_wtchpt_trp_g |
1595
        misalign_addr_jmpl_rtn_g | misalign_addr_ldst_atm_g;
1596
 
1597
// terms below can be made common. (grape)
1598
assign  lsu_dmmu_sfsr_trp_wr[0] = dsfsr_trp_wr_g & thread0_g;
1599
assign  lsu_dmmu_sfsr_trp_wr[1] = dsfsr_trp_wr_g & thread1_g;
1600
assign  lsu_dmmu_sfsr_trp_wr[2] = dsfsr_trp_wr_g & thread2_g;
1601
assign  lsu_dmmu_sfsr_trp_wr[3] = dsfsr_trp_wr_g & thread3_g;
1602
 
1603
//==========================================================================
1604
// Exception Handling End
1605
//==========================================================================
1606
 
1607
endmodule // lsu_dctl1
1608
 

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